CN102938406B - Gate-division type flash memory and forming method thereof - Google Patents
Gate-division type flash memory and forming method thereof Download PDFInfo
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Abstract
A kind of gate-division type flash memory, including: Semiconductor substrate, it is positioned at the wordline of described semiconductor substrate surface, is positioned at two discrete storage bit unit of described wordline both sides, between said two storage bit unit and wordline, there is tunnel oxide；Described storage bit unit includes being positioned at the first insulating barrier of described semiconductor substrate surface, being positioned at the floating boom of described first surface of insulating layer, it is positioned at second insulating barrier on described floating boom surface, is positioned at the control gate of described second surface of insulating layer and covers described floating boom, the sidewall structure of control gate；Described floating boom includes the spacing spacing more than described second floating boom with wordline of the first floating boom and the second floating boom, described first floating boom and wordline.Big due to the first floating boom and the gap ratio prior art of wordline so that the coupling capacity ratio prior art between described floating boom and wordline little so that the coupling electric capacity between wordline and floating boom is the least, thus improves the erasing of flash memory and the efficiency of read-write.
Description
Technical field
The present invention relates to semiconductor technology, particularly to a kind of gate-division type flash memory and forming method thereof.
Background technology
In the prior art, flash memory (Flash) memorizer has become as the main flow of non-volatile semiconductor storage technology,
In various flush memory devices, substantially it is divided into two types: fold gate flash memory and gate-division type flash memory, owing to folded gate flash memory is deposited
Crossing erasing problem, and gate-division type flash memory control gate is simultaneously as selecting transistor (Select transister), has
Imitate avoided erasure effect, and circuit design is relatively easy.And, compare folded gate flash memory, gate-division type flash memory utilizes source
Thermoelectron injects and is programmed, and has a higher programming efficiency, thus be widely used all kinds of such as smart cards, SIM,
In the electronic product such as microcontroller, mobile phone.
The Chinese patent literature of Publication No. CN101465161A discloses a kind of gate-division type flash memory, specifically refer to Fig. 1,
Including: Semiconductor substrate 10, the first storage bit unit 50 and second being positioned at the arrangement of described Semiconductor substrate 10 spaced surface is deposited
Storage space unit 60, fills the full wordline 40 of groove between described first storage bit unit 50 and the second storage bit unit 60, described
It is formed with tunnel oxide between wordline 40 and first storage bit unit the 50, second storage bit unit 60 and Semiconductor substrate 10
70, it is positioned at described Semiconductor substrate 10 surface and is positioned at the source electrode 20 of described first storage bit unit 50 side and is positioned at described the
The drain electrode 30 of two storage bit unit 60 opposite sides.Wherein, described first storage bit unit 40 includes: be positioned at described Semiconductor substrate
The first multi-crystal silicon floating bar 52 on 10 and the first polysilicon control grid 51 being positioned at described first multi-crystal silicon floating bar 52 surface；Described
Second storage bit unit 60 includes: the second multi-crystal silicon floating bar 62 of being positioned in described Semiconductor substrate 10 and be positioned at described more than second
The second polysilicon control grid 61 on crystal silicon floating boom 62.
But existing gate-division type flash memory work efficiency is the best.
Summary of the invention
The problem that the present invention solves is to provide a kind of gate-division type flash memory and forming method thereof, keeping control gate and can float
In the case of coupling electric capacity is constant between grid, reduces the electric capacity that couples of floating boom and wordline, thus improve between floating boom and control gate
The coefficient of coup, reduce the coefficient of coup between floating boom and wordline, improve the work efficiency of gate-division type flash memory.
For solving the problems referred to above, technical solution of the present invention provides a kind of gate-division type flash memory, including: Semiconductor substrate, position
In the wordline of described semiconductor substrate surface, being positioned at two discrete storage bit unit of described wordline both sides, said two is deposited
Between storage space unit and wordline, there is tunnel oxide, be located in one of the storage bit unit quasiconductor lining away from wordline side
Source electrode at the end, is positioned at the drain electrode away from the Semiconductor substrate of wordline side of another storage bit unit；Described storage position is single
Unit includes being positioned at the first insulating barrier of described semiconductor substrate surface, being positioned at the floating boom of described first surface of insulating layer, is positioned at institute
State second insulating barrier on floating boom surface, be positioned at the control gate of described second surface of insulating layer and cover described floating boom, control gate
Sidewall structure；Described floating boom includes the first floating boom and the second floating boom, and described first floating boom is near between the sidewall and wordline of wordline
Away from the spacing more than described second floating boom sidewall near wordline with wordline.
Optionally, described floating boom is notch cuttype near the sidewall of wordline, and described first floating boom is positioned at the top half of floating boom,
Described second floating boom is positioned at the latter half of floating boom.
Optionally, the total thickness of described floating boom is 1000 angstroms ~ 2000 angstroms, and the thickness range of described second floating boom is
100 angstroms ~ 300 angstroms.
Optionally, described first floating boom includes silicon oxide, nitridation near the insulant between the sidewall and wordline of wordline
Silicon, silicon oxynitride therein one or more.
Optionally, described first floating boom near the spacing range between the sidewall and tunnel oxide of wordline be 300 angstroms ~
500 angstroms..
Optionally, described control gate is more than or equal to described first floating boom near the spacing between the sidewall and wordline of wordline
Spacing between sidewall and the wordline of wordline.
Optionally, the section shape of described floating boom is rectangle, and described second insulating barrier and control gate are positioned at described floating boom
Top surface and sidewall surfaces.
Technical solution of the present invention additionally provides the forming method of a kind of gate-division type flash memory, including: Semiconductor substrate is provided,
Described semiconductor substrate surface forms the first insulation material layer, forms floating gate material layer on described first insulation material layer surface,
Form the second insulation material layer on described floating gate material layer surface, form control gate material on described second insulation material layer surface
Layer, forms mask layer in described control gate material surface；Described mask layer is performed etching, until exposing control gate material
Layer, forms the first side wall at described mask layer sidewall, exposes part control gate material surface between described first side wall；With
Described first side wall is mask, enters the floating gate material layer of described control gate material layer, the second insulation material layer and segment thickness
Row etching, exposes part floating gate material layer, forms the first opening；The second side wall is formed at described first opening sidewalls, described
Between second side wall, part floating gate material layer surface is exposed；With described second side wall as mask, to remaining floating gate material layer
Performing etching with the first insulating barrier, until expose Semiconductor substrate, form the second opening, described floating gate material layer is divided into and being positioned at
First floating gate material layer of top half and the second floating gate material layer being positioned at the latter half；In the bottom of described second opening and
Sidewall surfaces forms tunnel oxide, forms wordline on the tunnel oxide surface of described second opening, and described wordline is filled full
Described second opening；Remove described mask layer, with described first side wall and wordline as mask, etch described control gate material layer,
Second insulation material layer, floating gate material layer, the first insulation material layer, form two discrete storage positions single in described wordline both sides
Unit；A storage bit unit is away from forming source electrode in the Semiconductor substrate of wordline side wherein, in another storage bit unit
Away from forming drain electrode in the Semiconductor substrate of wordline side.
Technical solution of the present invention additionally provides the forming method of another kind of gate-division type flash memory, including: Semiconductor substrate is provided,
Form the first insulation material layer at described semiconductor substrate surface, form floating gate material on described first insulation material layer surface
Layer, forms the second insulation material layer on described floating gate material layer surface, forms control gate on described second insulation material layer surface
Material layer, forms mask layer in described control gate material surface；Described mask layer is performed etching, until exposing control gate
Material layer, forms the first side wall at described mask layer sidewall, exposes part and control gate material layer table between described first side wall
Face；With described first side wall as mask, first described control gate material layer, the second insulation material layer are performed etching, form the 3rd
Opening；The 4th side wall, the floating gate material with described 4th side wall as mask, to segment thickness is formed at described 3rd opening sidewalls
Layer performs etching, and forms the 4th opening；The 5th side wall is formed at described 4th opening sidewalls, with described 5th side wall as mask,
Remaining floating gate material layer and the first insulating barrier being performed etching, until exposing Semiconductor substrate, forming the 5th opening, described
Floating gate material layer is divided into the first floating gate material layer being positioned at top half and the 5th floating gate material layer being positioned at the latter half；Institute
Bottom and the sidewall surfaces of stating the 5th opening form tunnel oxide, form word on the tunnel oxide surface of described 5th opening
Line, described wordline fills full described 5th opening；Remove described mask layer, with described first side wall and wordline as mask, etching
Described control gate material layer, the second insulation material layer, floating gate material layer, the first insulation material layer, formed in described wordline both sides
Two discrete storage bit unit；A storage bit unit is away from forming source electrode in the Semiconductor substrate of wordline side wherein,
Drain electrode is formed in another storage bit unit is away from the Semiconductor substrate of wordline side.
Compared with prior art, the invention have the advantages that
The floating boom of the gate-division type flash memory of the embodiment of the present invention includes the first floating boom and the second floating boom, and described first floating boom is close
The sidewall of wordline and the spacing of wordline are more than described second floating boom sidewall near wordline and the spacing of wordline.Due to the first floating boom
Sidewall and the gap ratio prior art of wordline big of close wordline so that the coupling capacity ratio between described floating boom and wordline
Prior art little, can keep coupling between control gate and floating boom electric capacity constant in the case of, reduce floating boom and wordline
Coupling electric capacity, thus improve the coefficient of coup between floating boom and control gate, reduce the coefficient of coup between floating boom and wordline, improve
The work efficiency of gate-division type flash memory.And in erasing operation, the electronics in floating boom still can utilize the sidewall of the second floating boom to lead to
Cross tunnel oxide and enter in wordline, erasing operation will not be produced impact.
The section shape of the floating boom of the embodiment of the present invention is rectangle so that control gate can be formed at the top of described floating boom
And sidewall surfaces, improve the overlapping area between floating boom and control gate so that the electric capacity between floating boom and control gate becomes big, control
Grid processed become strong to the Capacitance Coupled ability of floating boom, and control ability becomes strong.
Accompanying drawing explanation
Fig. 1 is the structural representation of the gate-division type flash memory of prior art；
Fig. 2 ~ Figure 11 is the structural representation of the forming process of the gate-division type flash memory of first embodiment of the invention；
Figure 12 ~ Figure 18 is the structural representation of the forming process of the gate-division type flash memory of second embodiment of the invention.
Detailed description of the invention
Owing to existing gate-division type flash memory work efficiency is the best, inventor, through research, finds that this is mainly due to existing
Multi-crystal silicon floating bar and wordline between be only spaced tunnel oxide so that the voltage in described wordline can be affected by Capacitance Coupled
Voltage on multi-crystal silicon floating bar, thus affect gate-division type flash memory work efficiency.To this end, the invention provides a kind of sub-gate sudden strain of a muscle
Depositing, the floating boom of described gate-division type flash memory includes the first floating boom and the second floating boom, and described first floating boom is near the sidewall of wordline and word
The spacing of line is more than the spacing of described second floating boom sidewall near wordline with wordline.Due to described floating boom include the first floating boom and
Second floating boom, the sidewall of the close wordline of the first floating boom is big with the gap ratio prior art of wordline so that described floating boom and word
Coupling capacity ratio prior art between line little, can keep coupling between control gate and floating boom the situation that electric capacity is constant
Under, reduce the electric capacity that couples of floating boom and wordline, thus improve the coefficient of coup between floating boom and control gate, reduce floating boom and wordline
Between the coefficient of coup, improve gate-division type flash memory work efficiency.And in erasing operation, the electronics in floating boom still can be in order to
Enter in wordline with the sidewall of the second floating boom by tunnel oxide, erasing operation will not be produced impact.
Understandable, below in conjunction with the accompanying drawings to the present invention for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
Detailed description of the invention be described in detail.
Elaborate detail in the following description so that fully understanding the present invention.But the present invention can with multiple not
Being same as alternate manner described here to implement, those skilled in the art can do class in the case of intension of the present invention
Like promoting.Therefore the present invention is not limited by following public being embodied as.
First embodiment
First embodiment of the invention provide firstly the forming method of a kind of gate-division type flash memory, refer to Fig. 2 to Figure 11, for
The structural representation of the forming process of the gate-division type flash memory of first embodiment of the invention.
Refer to Fig. 2, it is provided that Semiconductor substrate 100, form the first insulation material layer on described Semiconductor substrate 100 surface
110, form floating gate material layer 120 on described first insulation material layer 110 surface, formed on described floating gate material layer 120 surface
Second insulation material layer 130, is formed on described second insulation material layer 130 surface and controls gate material layer 140, at described control gate
Material layer 140 surface forms mask layer 150.
Described Semiconductor substrate 100 is selected from p-type or the silicon substrate of N-type, germanium substrate, germanium silicon substrate, silicon-on-insulator substrate
One therein.
The material of described first insulation material layer the 110, second insulation material layer 130 is silicon oxide, is formed described first exhausted
The technique of edge material layer the 110, second insulation material layer 130 is thermal oxidation technology, atom layer deposition process or chemical gaseous phase deposition
Technique.
Described floating gate material layer 120 is used for being formed floating boom, and described control gate material layer 140 is used for forming control gate.Described
Floating gate material layer 120, the material controlling gate material layer 140 are doped with N-type or the polysilicon of p type impurity ion or metal, shape
The technique becoming described polysilicon is chemical vapor deposition method or sputtering technology.
Refer to Fig. 3, Fig. 2 is the Fig. 3 cross-sectional view along AA ' line direction, the section of described floating gate material layer 120
Being shaped as rectangle, described floating gate material layer 120 is strip structure, Semiconductor substrate corresponding below described floating gate material layer 120
It is isolated by fleet plough groove isolation structure 105 so that any one bar shaped floating gate material layer and other bar shaped floating gate material layer electricity
Isolation, each is individually formed a gate-division type flash memory.The technique forming described bar shaped floating gate material layer 120 is: described
One insulation material layer 110 surface utilizes chemical vapor deposition method to form one layer of floating gate material (not shown), to described floating boom material
Material performs etching and forms the bar shaped floating gate material layer 120 that cross-section structure is rectangle.Due to described floating gate material layer 120 section shape
For rectangle, the second insulation material layer 130 and the control gate material layer 140 that are subsequently formed are not made only in described floating gate material layer
The top surface of 120, is also formed in the sidewall surfaces of described floating gate material layer 120 so that the floating boom ultimately formed and control gate
Between overlapping area become big, the electric capacity between floating boom and control gate becomes big, and control gate becomes strong to the Capacitance Coupled ability of floating boom,
Control ability becomes strong, is conducive to improving the work efficiency of gate-division type flash memory.
In other embodiments, it is also possible to be formed without the floating gate material layer that described section shape is rectangle, described first
After insulation material layer surface utilizes chemical vapor deposition method to form one layer of floating gate material layer, directly at described floating gate material layer table
Face forms the second insulation material layer and controls gate material layer.
The material of described mask layer 150 is photoresist, silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon etc. therein
Planting or several, the technique forming described mask layer is chemical vapor deposition method.In the present embodiment, described mask layer 150
Material is silicon nitride.
Refer to Fig. 4, described mask layer 150 is performed etching, until exposing control gate material layer 140, covering described
Film layer 150 sidewall forms the first side wall 161, exposes part and control gate material layer 140 surface between described first side wall 161.
Concrete technology includes: form patterned photoresist layer (not shown), with described figure on described mask layer 150 surface
The photoresist layer of shape is mask, performs etching described mask layer 150, until exposing control gate material layer 140；Described
Mask layer 150 and control gate material layer 140 surface exposed form the first spacer material layer (not shown), to described first side
The walling bed of material is etched back to, and forms the first side wall 161 at described mask layer 150 sidewall.In the present embodiment, described first side
The material of wall 161 is silicon oxide.By controlling the width of described first spacer material layer, described first side wall 161 can be controlled
The width of bottommost, thus control floating boom and the width of control gate ultimately formed.Wherein, the width of indication in the embodiment of the present invention
Degree is parallel to the distance from left to right in semiconductor substrate surface direction for semiconductor structure edge in figure 4.
Refer to Fig. 5, with described first side wall 161 as mask, to described control gate material layer the 140, second insulant
The floating gate material layer 120 of layer 130 and segment thickness performs etching, and exposes part floating gate material layer 120, forms the first opening
171。
By the control to etch period, remove, in etching, the control gate material layer that described first side wall 161 exposes
140, after the second insulation material layer 130, then the floating gate material layer 120 of segment thickness is removed.In the present embodiment, described floating boom material
The thickness range of the bed of material 120 is 1000 angstroms ~ 2000 angstroms, be not removed the thickness range of remaining floating gate material layer be 100 angstroms ~
300 angstroms.
In other embodiments, those skilled in the art can also be formed as required the floating boom of other thickness, first float
Grid and the second floating boom.
Refer to Fig. 6, refer to Fig. 5 at described first opening 171() sidewall forms the second side wall 162, described second side
Between wall 162, part floating gate material layer 120 surface is exposed.
The technique forming described second side wall 162 includes: in the bottom of described first opening 171 and sidewall surfaces, described
Mask layer 150 surface forms the second spacer material layer (not shown), is etched back to, described second spacer material layer described
First opening 171 sidewall forms the second side wall 162.By controlling the thickness of described second spacer material layer, can control described
The width of the second side wall 162 bottommost, thus control the distance between the first floating boom and the tunnel oxide ultimately formed.At this
In embodiment, the thickness range of described second side wall 162 is 300 angstroms ~ 500 angstroms.Due between the floating boom ultimately formed and wordline
Parasitic capacitance be inversely proportional to distance between the two, when the segment thickness that is etched ultimately formed floating boom (the first floating boom) with
When spacing between wordline is bigger, when the width of the most described second side wall 162 bottommost is bigger, between described floating boom and wordline
Parasitic capacitance is the least so that described wordline is less to the voltage influence of floating boom, thus is not easy impact point
Gate flash memory read-write and the efficiency of erasing.
The material of described second side wall 162 includes silicon oxide, silicon nitride or silicon oxynitride so that described between the first floating boom
With parasitic capacitance between wordline is the least, so that total parasitic capacitance of described floating boom and wordline is as far as possible
Little, thus reduce the coefficient of coup between floating boom and wordline, improve the read-write efficiency of erasing of flash memory..
Refer to Fig. 7, with described second side wall 162 as mask, to remaining floating gate material layer 120 and the first insulating barrier
110 perform etching, until exposing Semiconductor substrate 100, form the second opening 172, and described floating gate material layer 120 is divided into position
In the first floating gate material layer 121 of top half be positioned at the second floating gate material layer 122 of the latter half, wherein said first floats
The thickness of gate material layer 121 is equal to the thickness of the floating gate material layer 120 etched away in Fig. 5.Described first floating gate material layer 121 with
Having the second side wall 162 between the sidewall of the second opening 172, described second floating gate material layer 122 sidewall is formed without side wall.
Refer to Fig. 8, refer to Fig. 7 at described second opening 172() bottom and sidewall surfaces formed tunnel oxide
181, wordline 180 is formed on tunnel oxide 181 surface of described second opening 172, described wordline 180 fills full described second
Opening 172.
In the present embodiment, utilize chemical vapor deposition method or atom layer deposition process at described second opening 172
Bottom and sidewall surfaces, mask layer 150 surface form silica material layer (not shown), in described silica material layer surface shape
Become polysilicon material layer (not shown), and described polysilicon material layer fills full described second opening 172, with described mask layer
Described polysilicon material layer, silica material layer are ground by 150 as grinding barrier layer, until exposing described mask layer
150 surfaces, form tunnel oxide 181 in described second opening 172 and are positioned at the polysilicon material on tunnel oxide 181 surface
Material, described in be positioned at tunnel oxide 181 surface polycrystalline silicon material formed wordline 180.Wherein, in described floating gate material layer 120
The sidewall of the second floating gate material layer 122 contact with tunnel oxide 181 so that follow-up gate-division type flash memory is carried out erasing behaviour
In work, the electronics in floating boom still can enter wordline 180, Bu Huiying by the second floating gate material layer 122 and tunnel oxide 181
Ring the erasing ability of gate-division type flash memory.
Refer to Fig. 9, remove described mask layer 150(and refer to Fig. 8), with described first side wall 161 and wordline 180 for covering
Film, etches described control gate material layer 140(and refer to Fig. 8), the second insulation material layer 130(refer to Fig. 8), floating gate material layer
120(refer to Fig. 8), the first insulation material layer 110(refer to Fig. 8), respectively formed control gate the 145, second insulating barrier 135,
Floating gate layer 125 and the first insulating barrier 115, wherein said floating boom 125 includes the second floating boom being positioned at the first insulating barrier 115 surface
127 and be positioned at first floating boom 126 on the second floating boom 127 surface, have between described first floating boom 126 and tunnel oxide 181
Second side wall 162, described second floating boom 127 contacts with tunnel oxide 181.
Refer to Figure 10, the first side wall 161 after described etching, control gate the 145, second insulating barrier 135, floating gate layer
125 and first insulating barrier 115 sidewall formed the 3rd side wall 163, described first side wall the 161, second side wall the 162, the 3rd side wall
163 constitute sidewall structure 160, and described sidewall structure 160, control gate the 145, second insulating barrier 135, floating gate layer 125 and first are exhausted
Edge layer 115 constitutes storage bit unit 200 so that described wordline 180 both sides form two discrete storage bit unit 200.
Refer to Figure 11, a storage bit unit 200 is away from shape in the Semiconductor substrate 100 of wordline 180 side wherein
Become source electrode 191, in another storage bit unit 200 is away from the Semiconductor substrate 100 of wordline 180 side, forms drain electrode 192.
The technique forming described source electrode 191 and drain electrode 192 is ion implantation technology.Form described source electrode 191 and drain electrode 192
After, form conductive plunger (not shown) at described source electrode 191 and 192 surfaces that drain so that source electrode 191 and drain electrode 192 and control
Circuit is connected.
First embodiment of the invention additionally provides a kind of gate-division type flash memory, refer to Figure 11, specifically includes: Semiconductor substrate
100, it is positioned at the wordline 180 on described Semiconductor substrate 100 surface, is positioned at two discrete storage positions of described wordline 180 both sides
Unit 200, has tunnel oxide 181 between said two storage bit unit 200 and wordline 180, be located in one of storage
Bit location 200, away from the source electrode 191 in the Semiconductor substrate 100 of wordline 180 side, is positioned at another storage bit unit 200 remote
Drain electrode 192 in the Semiconductor substrate 100 of wordline 180 side；Described storage bit unit 200 includes being positioned at described quasiconductor lining
First insulating barrier 115 on surface, the end 100, it is positioned at the floating boom 125 on described first insulating barrier 115 surface, is positioned at described floating boom 125 table
Second insulating barrier 135 in face, is positioned at the control gate 145 on described second insulating barrier 135 surface and covers described floating boom 125, controls
The sidewall structure 160 of grid 145；Described sidewall structure 160, by being positioned at first side wall 161 on control gate 145 surface, is positioned at the first side
Wall 161, control gate the 145, second insulating barrier 135, second side wall 162 of floating boom 125 side of segment thickness, be positioned at the first side wall
161, control gate the 145, second insulating barrier 135, the 3rd side wall 163 of floating boom the 125, first insulating barrier 115 opposite side are constituted；Described
Floating boom 125 includes the first floating boom 126 and the second floating boom 127, and described first floating boom 126 is positioned at the top half of floating boom 125, described
Second floating boom 127 is positioned at the latter half of floating boom 125, has second between described first floating boom 126 and tunnel oxide 181
Side wall 165, described second floating boom 127 contacts with tunnel oxide 181 ' so that described first floating boom 126 is near wordline 180
The spacing of sidewall and wordline 180 more than the spacing of described second floating boom 127 sidewall near wordline 180 with wordline 180.
Owing to described first floating boom 126 is more than described second floating boom near the sidewall of wordline 180 with the spacing of wordline 180
127 near the spacing of sidewall and the wordline 180 of wordline 180 so that floating boom and wordline in the gate-division type flash memory of the embodiment of the present invention
Between parasitic capacitance less than parasitic capacitance between floating boom and wordline in existing gate-division type flash memory, the voltage of wordline is not easy
Affect the normal work of gate-division type flash memory.
And by controlling thickness and material, the surface area of the first floating gate side walls of the second side wall, floating boom and word can be controlled
Total parasitic capacitance between line, thus ensure that gate-division type flash memory works normally.
In the prior art, refer to Fig. 1, during gate-division type flash memory is programmed, the electricity of described wordline 40
Pressure is 1.5V, and the voltage of described first polysilicon control grid 51 is 5V, and the voltage of described second polysilicon control grid 61 is 10V,
The voltage of described source electrode 20 is 0V, and the voltage of described drain electrode 30 is 5V, utilizes the high pressure of described second polysilicon control grid 61 to lead to
Cross Capacitance Coupled to be raised by the voltage of the second multi-crystal silicon floating bar 62, so that the electron tunneling of channel region enters the second polysilicon
Floating boom 62, thus complete programming operation.Owing to only there is tunnel oxide between described second multi-crystal silicon floating bar 62 and wordline 40
70, the second multi-crystal silicon floating bar 62 is easily subject to the impact of relatively low wordline 40 voltage, causes the voltage of the second multi-crystal silicon floating bar 62
It is not easy to raise, it is not easy to the electron tunneling of channel region enters the second multi-crystal silicon floating bar 62, affects programming efficiency.But the present invention
Parasitic capacitance between floating boom 125 and the wordline 180 of embodiment is relatively low, and Capacitance Coupled ability is poor, and floating boom 125 is not readily susceptible to
The impact of relatively low word line voltage, floating gate is controlled the Capacitance Coupled of grid and is easy to raise, can be relatively easily by ditch
The electron tunneling in road district enters floating boom 125, completes programming operation.
In like manner, refer to Fig. 1, during wiping gate-division type flash memory, the voltage of described wordline 40 is 8V, institute
The voltage stating the first polysilicon control grid 51 is 0V, and the voltage of described second polysilicon control grid 61 is 0V, described source electrode 20
Voltage is 0V, and the voltage of described drain electrode 30 is 0V, utilizes the high pressure of described wordline 40 that electronics is passed through wordline 40 from the first polycrystalline
Silicon floating gate the 52, second multi-crystal silicon floating bar 62 is removed, thus completes erasing operation.Due to described first multi-crystal silicon floating bar 52,
Only there is between two multi-crystal silicon floating bars 62 and wordline 40 tunnel oxide 70, first multi-crystal silicon floating bar the 52, second multi-crystal silicon floating bar
62 impacts being easily subject to higher word line voltage, cause first multi-crystal silicon floating bar the 52, second multi-crystal silicon floating bar 62 and wordline 40
Between voltage difference diminish, it is not easy to the electron tunneling of first multi-crystal silicon floating bar the 52, second multi-crystal silicon floating bar 62 is entered wordline,
Affect efficiency of erasing.But the parasitic capacitance between the floating boom 125 of the embodiment of the present invention and wordline 180 is relatively low, Capacitance Coupled ability
Poor, floating boom 125 is not readily susceptible to the impact of higher word line voltage, and floating gate is the most relatively low, between floating boom and wordline
Voltage difference is relatively big, relatively easily the electron tunneling of floating boom can be entered wordline, completes erasing operation.
In like manner, refer to Fig. 1, during being read out gate-division type flash memory, the voltage of described wordline 40 is 2.5V,
The voltage of described first polysilicon control grid 51 is 0V, and the voltage of described second polysilicon control grid 61 is 3V, described source electrode 20
Voltage be 0V, the voltage of described drain electrode 30 is 1V, by judging whether channel region has current lead-through, it is achieved to the first polysilicon
The read operation of floating boom 52.Owing to only having between described first multi-crystal silicon floating bar the 52, second multi-crystal silicon floating bar 62 and wordline 40
Tunnel oxide 70, first multi-crystal silicon floating bar the 52, second multi-crystal silicon floating bar 62 is easily subject to the impact of higher word line voltage, leads
The voltage causing the first multi-crystal silicon floating bar 52 is affected by word line voltage and is raised, consequently, it is possible to cause the first multi-crystal silicon floating bar 52
The unlatching of corresponding channel region is owing to being affected by word line voltage, it is impossible to make correct read operation.But the present invention is real
Executing the parasitic capacitance between the floating boom 125 of example and wordline 180 relatively low, Capacitance Coupled ability is poor, and floating boom 125 is not readily susceptible to word
The impact of line voltage, the channel region that floating boom is corresponding be turned on and off depending entirely in floating boom whether there is electronics, it is thus possible to
Complete read operation accurately.
Second embodiment
Second embodiment of the invention additionally provides the forming method of a kind of gate-division type flash memory, refer to Figure 12 to Figure 18, for
The structural representation of the forming process of the gate-division type flash memory of second embodiment of the invention.
In the forming process of the gate-division type flash memory of second embodiment of the invention, formed the first side wall and technique before with
First embodiment of the invention is identical, specifically refer to Fig. 2 to Fig. 4, does not repeats at this.
Refer to Figure 12, with described first side wall 161 as mask, first insulate material to described control gate material layer 140, second
The bed of material 130 performs etching, and forms the 3rd opening 173.
Refer to Figure 13, form the 4th side wall 164 at described 3rd opening sidewalls, with described 4th side wall 164 as mask,
The floating gate material layer 120 of segment thickness is performed etching, forms the 4th opening 174.
By the control to etch period, remove the floating gate material layer 120 of segment thickness.In the present embodiment, described floating
The thickness range of gate material layer 120 is 1000 angstroms ~ 2000 angstroms, and the thickness range of the most removed floating gate material is 100 angstroms ~ 300
Angstrom.
In other embodiments, those skilled in the art can also be formed as required the floating boom of other thickness, first float
Grid and the second floating boom.
The material of described 4th side wall 164 is silicon oxide or silicon oxynitride.Due to the isolation of described 4th side wall 164,
Distance between control gate and wordline that end form becomes more than the distance of floating boom and wordline, formed between control gate and wordline electricity every
From, will not leak electricity between control gate and wordline when erasing and read-write.
Refer to Figure 14, form the 5th side wall 165 at described 4th opening sidewalls, with described 5th side wall 165 as mask,
Remaining floating gate material layer 120 and the first insulating barrier 110 being performed etching, until exposing Semiconductor substrate 100, forming the 5th
Opening 175, described floating gate material layer 120 is divided into the first floating gate material layer 121 ' being positioned at top half and is positioned at the latter half
5th floating gate material layer 122 '.
The material of described 5th side wall 165 includes silicon oxide, silicon nitride or silicon oxynitride.In the present embodiment, described
The thickness range of five side walls 165 is 300 angstroms ~ 500 angstroms.Owing to parasitic capacitance between described floating boom and wordline is with between the two
Distance is inversely proportional to, by controlling thickness and the material of described 5th side wall 165, when floating of the segment thickness that is etched ultimately formed
When spacing between grid (the first floating boom) and wordline is bigger, when the width of the most described second side wall 162 bottommost is bigger, described floating
Parasitic capacitance between grid and wordline is the least so that described wordline is less to the voltage influence of floating boom, from
And be not easy to affect gate-division type flash memory read-write and the efficiency of erasing.
Refer to Figure 15, refer to Figure 14 at described 5th opening 175() bottom and sidewall surfaces formed tunnel oxide
Layer 181 ', forms wordline 180 ' on the tunnel oxide 181 ' surface of described 5th opening 175, and described wordline 180 ' fills full institute
State the 5th opening 175.
Refer to Figure 16, remove described mask layer 150(and refer to Figure 15), with described first side wall 161 and wordline 180 '
For mask, etch described control gate material layer 140(and refer to Figure 15), the second insulation material layer 130(refer to Figure 15), floating boom
Material layer 120(refer to Figure 15), the first insulation material layer 110(refer to Figure 15), form control gate 145 ', second exhausted respectively
Edge layer 135 ', floating gate layer 125 ' and the first insulating barrier 115 ', wherein said floating boom 125 ' includes being positioned at the first insulating barrier 115 ' table
Second floating boom 127 ' in face and the first floating boom 126 ' being positioned at the second floating boom 127 ' surface, described first floating boom 126 ' and tunnelling oxygen
Changing and have the 5th side wall 165 between layer 181 ', described second floating boom 127 ' contacts with tunnel oxide 181 ', described control gate
There is between 145 ' and tunnel oxide 181 ' the 5th side wall 165 and the 4th side wall 164.
Refer to Figure 17, the first side wall 161 after described etching, control gate 145 ', the second insulating barrier 135 ', floating gate layer
125 ' and first insulating barrier 115 ' sidewall formed the 6th side wall 166, described first side wall the 161, the 4th side wall the 164, the 5th side
Wall the 165, the 6th side wall 166 constitutes sidewall structure 160 ', described sidewall structure 160 ', control gate 145 ', the second insulating barrier 135 ',
Floating gate layer 125 ' and the first insulating barrier 115 ' constitute storage bit unit 200 ' so that described wordline 180 ' both sides formation two is discrete
Storage bit unit 200 '.
Refer to Figure 18, wherein in storage bit unit 200 ' Semiconductor substrate 100 away from wordline 180 ' side
Form source electrode 191 ', in another storage bit unit 200 ' is away from the Semiconductor substrate 100 of wordline 180 ' side, forms drain electrode
192′。
Second embodiment of the invention additionally provides a kind of gate-division type flash memory, refer to Figure 18, specifically includes: Semiconductor substrate
100, it is positioned at the wordline 180 ' on described Semiconductor substrate 100 surface, is positioned at two discrete storages of described wordline 180 ' both sides
Bit location 200 ', has tunnel oxide 181 ' between said two storage bit unit 200 ' and wordline 180 ', is located therein one
Individual storage bit unit 200 ', away from the source electrode 191 ' in the Semiconductor substrate 100 of wordline 180 ' side, is positioned at another storage position
Unit 200 ' is away from the drain electrode 192 ' in the Semiconductor substrate 100 of wordline 180 ' side；Described storage bit unit 200 ' includes position
The first insulating barrier 115 ' in described Semiconductor substrate 100 surface, it is positioned at the floating boom 125 ' on described first insulating barrier 115 ' surface,
Be positioned at second insulating barrier 135 ' on described floating boom 125 ' surface, be positioned at described second insulating barrier 135 ' surface control gate 145 ' and
Cover the sidewall structure 160 ' of described floating boom 125 ', control gate 145 '；Described sidewall structure 160 ' is by being positioned at control gate 145 ' table
First side wall 161 ' in face, is positioned at the first side wall 161, control gate 145 ', the 4th side wall 164 of the second insulating barrier 135 ' side,
It is positioned at the 5th side wall 165 of the floating boom 125 ' side of the 4th side wall 164 and segment thickness, is positioned at the first side wall 161, control gate
145 ', second insulating barrier 135 ', floating boom 125 ', the 6th side wall 166 of the first insulating barrier 115 ' opposite side are constituted；Described floating boom
125 ' include that the first floating boom 126 ' and the second floating boom 127 ', described first floating boom 126 ' are positioned at the top half of floating boom 125 ', institute
State the second floating boom 127 ' and be positioned at the latter half of floating boom 125 ', have between described first floating boom 126 ' and tunnel oxide 181 '
5th side wall 165, described second floating boom 127 ' contacts with tunnel oxide 181 ' so that described first floating boom 126 ' is near word
The sidewall of line 180 ' and the spacing of wordline 180 ' are more than sidewall and the wordline 180 ' of the described second close wordline 180 ' of floating boom 127 '
Spacing；There is between described control gate 145 ' and tunnel oxide 181 ' the 5th side wall 165 and the 4th side wall 164 so that
Distance between control gate and wordline that end form becomes is more than the distance of floating boom with wordline so that floating gate is mutual with word line voltage
Unaffected.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the method for the disclosure above and technology contents to this
Bright technical scheme makes possible variation and amendment, therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variations and modification that above example is made, belong to technical solution of the present invention
Protection domain.
Claims (14)
1. a gate-division type flash memory, it is characterised in that including: Semiconductor substrate, is positioned at the wordline of described semiconductor substrate surface,
It is positioned at two discrete storage bit unit of described wordline both sides, there is between said two storage bit unit and wordline tunnelling oxygen
Change layer, be located in one of storage bit unit away from the source electrode in the Semiconductor substrate of wordline side, be positioned at another storage position
Unit is away from the drain electrode in the Semiconductor substrate of wordline side；Described storage bit unit includes being positioned at described semiconductor substrate surface
The first insulating barrier, be positioned at the floating boom of described first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, be positioned at institute
State the control gate of the second surface of insulating layer and cover described floating boom, the sidewall structure of control gate；Described floating boom includes the first floating boom
With the second floating boom, described first floating boom is more than described second floating boom near the side of wordline near the sidewall of wordline with the spacing of wordline
Wall and the spacing of wordline；Described first floating boom is positioned at the top half of floating boom, and described second floating boom is positioned at the latter half of floating boom.
2. gate-division type flash memory as claimed in claim 1, it is characterised in that described floating boom is notch cuttype near the sidewall of wordline.
3. gate-division type flash memory as claimed in claim 2, it is characterised in that the total thickness of described floating boom be 1000 angstroms～
2000 angstroms, the thickness range of described second floating boom is 100 angstroms～300 angstroms.
4. gate-division type flash memory as claimed in claim 1, it is characterised in that described first floating boom is near the sidewall of wordline and wordline
Between insulant include silicon oxide, silicon nitride, silicon oxynitride therein one or more.
5. gate-division type flash memory as claimed in claim 1, it is characterised in that described first floating boom is near the sidewall of wordline and tunnelling
Spacing range between oxide layer is 300 angstroms～500 angstroms.
6. gate-division type flash memory as claimed in claim 1, it is characterised in that described control gate near wordline sidewall and wordline it
Between spacing more than or equal to described first floating boom near the spacing between the sidewall and wordline of wordline.
7. the forming method of a gate-division type flash memory, it is characterised in that including:
Semiconductor substrate is provided, forms the first insulation material layer at described semiconductor substrate surface, at described first insulant
Layer surface forms floating gate material layer, forms the second insulation material layer on described floating gate material layer surface, at described second insulation material
Bed of material surface is formed and controls gate material layer, forms mask layer in described control gate material surface；
Described mask layer being performed etching, until exposing control gate material layer, forming the first side wall at described mask layer sidewall,
Between described first side wall, part control gate material surface is exposed；
Floating boom material with described first side wall as mask, to described control gate material layer, the second insulation material layer and segment thickness
The bed of material performs etching, and exposes part floating gate material layer, forms the first opening；
Form the second side wall at described first opening sidewalls, between described second side wall, expose part floating gate material layer surface；
With described second side wall as mask, remaining floating gate material layer and the first insulating barrier are performed etching, until exposing half
Conductor substrate, forms the second opening, under described floating gate material layer is divided into the first floating gate material layer being positioned at top half and is positioned at
Second floating gate material layer of half part；
Tunnel oxide is formed, at the tunnel oxide table of described second opening in the bottom of described second opening and sidewall surfaces
Face forms wordline, and described wordline fills full described second opening；
Remove described mask layer, with described first side wall and wordline as mask, etch described control gate material layer, the second insulation material
The bed of material, floating gate material layer, the first insulation material layer, form two discrete storage bit unit in described wordline both sides；
A storage bit unit is away from forming source electrode in the Semiconductor substrate of wordline side wherein, in another storage bit unit
Away from forming drain electrode in the Semiconductor substrate of wordline side.
8. the forming method of gate-division type flash memory as claimed in claim 7, it is characterised in that the gross thickness of described floating gate material layer
Scope is 1000 angstroms～2000 angstroms, and the thickness range of described second floating gate material layer is 100 angstroms～300 angstroms.
9. the forming method of gate-division type flash memory as claimed in claim 7, it is characterised in that the thickness range of described second side wall
It it is 300 angstroms～500 angstroms.
10. the forming method of gate-division type flash memory as claimed in claim 7, it is characterised in that the material bag of described second side wall
Include silicon oxide, silicon nitride, silicon oxynitride therein one or more.
The forming method of 11. 1 kinds of gate-division type flash memories, it is characterised in that including:
Semiconductor substrate is provided, forms the first insulation material layer at described semiconductor substrate surface, at described first insulant
Layer surface forms floating gate material layer, forms the second insulation material layer on described floating gate material layer surface, at described second insulation material
Bed of material surface is formed and controls gate material layer, forms mask layer in described control gate material surface；
Described mask layer being performed etching, until exposing control gate material layer, forming the first side wall at described mask layer sidewall,
Between described first side wall, part control gate material surface is exposed；
With described first side wall as mask, first described control gate material layer, the second insulation material layer are performed etching, form the 3rd
Opening；
The 4th side wall, the floating gate material with described 4th side wall as mask, to segment thickness is formed at described 3rd opening sidewalls
Layer performs etching, and forms the 4th opening；
Form the 5th side wall at described 4th opening sidewalls, with described 5th side wall as mask, to remaining floating gate material layer and
First insulating barrier performs etching, until exposing Semiconductor substrate, forms the 5th opening, and described floating gate material layer is divided into and being positioned at
First floating gate material layer of half part and the 5th floating gate material layer being positioned at the latter half；
Tunnel oxide is formed, at the tunnel oxide table of described 5th opening in the bottom of described 5th opening and sidewall surfaces
Face forms wordline, and described wordline fills full described 5th opening；
Remove described mask layer, with described first side wall and wordline as mask, etch described control gate material layer, the second insulation material
The bed of material, floating gate material layer, the first insulation material layer, form two discrete storage bit unit in described wordline both sides；
A storage bit unit is away from forming source electrode in the Semiconductor substrate of wordline side wherein, in another storage bit unit
Away from forming drain electrode in the Semiconductor substrate of wordline side.
The forming method of 12. gate-division type flash memories as claimed in claim 11, it is characterised in that the total thickness of described floating gate material layer
Degree scope is 1000 angstroms～2000 angstroms, and the thickness range of described 5th floating gate material layer is 100 angstroms～300 angstroms.
The forming method of 13. gate-division type flash memories as claimed in claim 11, it is characterised in that the thickness model of described 5th side wall
Enclose is 300 angstroms～500 angstroms.
The forming method of 14. gate-division type flash memories as claimed in claim 11, it is characterised in that the material bag of described 5th side wall
Include silicon oxide, silicon nitride, silicon oxynitride therein one or more.
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