CN104103587B - A kind of manufacture method of semiconductor devices - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, sequentially forming a high-k dielectric layer, a cover layer, and a sacrificial gate electrode layer on the semiconductor substrate; forming a patterned first gate electrode layer on the sacrificial gate electrode layer A hard mask layer; using the patterned first hard mask layer as a mask, etching the sacrificial gate electrode layer to form a stacked structure on the cover layer; forming a sidewall material layer surrounding the stacked structure; etching the sidewall material layer to form sidewalls on both sides of the stack structure; sequentially etch the capping layer and the high-k dielectric layer. According to the present invention, a dummy gate structure with the following structural features can be formed on a semiconductor substrate: the width of the cover layer and the high-k dielectric layer in the dummy gate structure is greater than the width of the sacrificial gate electrode layer, further improving the final formation performance of semiconductor devices.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a method for forming a dummy gate structure.

Background technique

In the manufacturing process of next-generation integrated circuits, a high-k-metal gate process is usually used for the fabrication of complementary metal-oxide-semiconductor (CMOS) gates. For transistor structures with higher process nodes, the high-k-metal gate process is usually a gate-last process, and its typical implementation process includes: first, forming a dummy gate on a semiconductor substrate structure, the dummy gate structure is composed of a bottom-up interface layer, a high-k dielectric layer, a cover layer and a sacrificial gate electrode layer; then, a gate spacer structure is formed on both sides of the dummy gate structure, and then removing the sacrificial gate electrode layer in the dummy gate structure, leaving a trench between the gate spacer structures; then, sequentially depositing a workfunction metal layer (workfunction metal layer), barrier layer (barrier layer) and wetting layer (wetting layer); finally filling with metal gate material to form a metal gate structure on the covering layer.

In the above process, the width of the formed metal gate structure is greater than or equal to the width of the cover layer/high-k dielectric layer, and the electrical performance test shows that the performance of the semiconductor device with the above structural characteristics is inferior to that of the metal gate The performance of semiconductor devices where the width of the structure is smaller than the width of the capping layer/high-k dielectric layer.

Since the width of the metal gate structure is determined by the width of the sacrificial gate electrode layer in the previously formed dummy gate structure, it is necessary to propose a method to form a dummy gate structure in which The width of the sacrificial gate electrode layer is less than the width of the cap layer/high-k dielectric layer.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a high-k dielectric layer, a cover layer, and a sacrificial gate electrode layer are sequentially formed; Forming a patterned first hard mask layer on the sacrificial gate electrode layer; using the patterned first hard mask layer as a mask, etching the sacrificial gate electrode layer to form a laminated layer on the cover layer structure; forming a layer of sidewall material surrounding the stacked structure; etching the layer of sidewall material to form sidewalls on both sides of the stacked structure; sequentially etching the capping layer and the high-k dielectric Floor.

Further, after etching the covering layer and the high-k dielectric layer, the step of overetching is further included to further reduce the width of the covering layer and the high-k dielectric layer.

Further, after the over-etching is completed, the width of the stacked structure is smaller than the width of the covering layer and the high-k dielectric layer.

Further, an interface layer is formed under the high-k dielectric layer.

Further, the material of the interface layer includes oxide.

Further, the material of the high-k dielectric layer is hafnium oxide; the material of the covering layer is titanium nitride.

Further, the material of the first hard mask layer includes dielectric material, metal and its nitride, polysilicon or a combination thereof.

Further, the material of the first hard mask layer is a dielectric material formed by a chemical vapor deposition process.

Further, the source gas used to form the sidewall material layer is CH ₄ or SiCl ₄ /O ₂ .

Further, the sidewall material layer is formed by an in-situ curing process.

According to the present invention, a dummy gate structure with the following structural features can be formed on a semiconductor substrate: the width of the cover layer and the high-k dielectric layer in the dummy gate structure is greater than the width of the sacrificial gate electrode layer, further improving the final formation performance of semiconductor devices.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

FIG. 1A-FIG. 1F are schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention;

FIG. 2 is a flowchart of a method for forming a dummy gate structure according to an exemplary embodiment of the present invention.

detailed description

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be presented in the following description to illustrate the method for forming the dummy gate structure proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or Multiple other features, integers, steps, operations, elements, components and/or combinations thereof.

Hereinafter, detailed steps of forming a dummy gate structure according to a method according to an exemplary embodiment of the present invention will be described with reference to FIG. 1A-FIG. 1F and FIG. 2 .

Referring to FIG. 1A-FIG. 1F , there are shown schematic cross-sectional views of devices respectively obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention.

Firstly, as shown in FIG. 1A , a semiconductor substrate 100 is provided. The constituent material of the semiconductor substrate 100 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI) and the like. As an example, in this embodiment, single crystal silicon is selected as the constituent material of the semiconductor substrate 100 . Isolation structures, various well structures, and the like are formed in the semiconductor substrate 100 , which are omitted from illustration for simplicity.

An interface layer 101 , a high-k dielectric layer 102 , a capping layer 103 and a sacrificial gate electrode layer 104 are sequentially formed on a semiconductor substrate 100 . The material of the interface layer 101 includes oxide, such as silicon dioxide (SiO ₂ ). The material of the high-k dielectric layer 102 includes hafnium-containing materials, metal oxides or combinations thereof, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., particularly preferred is hafnium oxide (HfO ₂ ). The material of the cover layer 103 includes metal or metal nitride, particularly preferably titanium nitride (TiN). The material of the sacrificial gate electrode layer 104 includes polysilicon. Various suitable processes familiar to those skilled in the art can be used to form the above layers, such as chemical vapor deposition process or physical vapor deposition process. It should be noted that the interface layer 101 is optional, and the function of forming the interface layer 101 is to improve the interface characteristics between the high-k dielectric layer 101 and the semiconductor substrate 100 .

Next, as shown in FIG. 1B , a first hard mask layer 105 and a second hard mask layer 106 are sequentially formed on the sacrificial gate electrode layer 104 . In this embodiment, the material of the first hard mask layer 105 includes SiN, SiON, SiO ₂ or a combination thereof; the material of the second hard mask layer 106 includes dielectric materials (such as SiC, SiCN, etc.), metals and their combinations. Nitride (such as TiN, TaN, Ti, etc.), polysilicon, or combinations thereof, are particularly preferred as dielectric materials that can be formed using a chemical vapor deposition process.

Next, the second hard mask layer 106 is patterned. Embodiments of this patterning are photolithography, nanoimprinting or digital angiography (DSA) followed by dry etching. The process steps involved in this patterned embodiment are photolithography and subsequent dry etching include: forming a photoresist layer on the second hard mask layer 106; Adhesive layer; With the patterned photoresist layer as a mask, perform etching to the second hard mask layer 106, which is dry etching and terminates when the first hard mask layer 105 is exposed; remove the photoresist layer, the removal of the photoresist layer can be performed using an ashing process. In order to ensure the quality of exposure, before forming the photoresist layer, an organic dielectric layer (ODL) and a bottom anti-reflective coating (BARC) are sequentially formed on the second hard mask layer 106: the function of the organic dielectric layer is to make the formation The top surface of the semiconductor substrate 100 after the aforementioned layers is flat, and the function of the bottom anti-reflection coating is to improve the quality of exposure and ensure the formation of a photoresist layer with expected patterns after development.

It should be noted that, when forming gates with different widths on the semiconductor substrate 100 , at least one patterning of the second hard mask layer 106 is performed. In addition, the second hard mask layer 106 may not be formed, and the first hard mask layer 105 may be directly patterned. At this time, the material of the first hard mask layer 105 includes a dielectric material (such as SiC, SiCN, etc.) , metals and their nitrides (such as TiN, TaN, Ti, etc.), polysilicon or combinations thereof, and dielectric materials that can be formed by chemical vapor deposition are particularly preferred.

Next, as shown in FIG. 1C , using the patterned second hard mask layer 106 as a mask, the first hard mask layer 105 and the sacrificial gate electrode layer 104 are sequentially etched, and the etching ends when the cover layer 103 is exposed. The patterned second hard mask layer 106 together with the etched first hard mask layer 105 and the sacrificial gate electrode layer 104 form a stacked structure 107 . The etching gas for etching the first hard mask layer 105 and the sacrificial gate electrode layer 104 includes HBr, NF ₃ , Cl ₂ , O ₂ , N ₂ and so on.

Next, as shown in FIG. 1D , a sidewall material layer 108 surrounding the stacked structure 107 is formed. Forming the sidewall material layer 108 may adopt various suitable processes familiar to those skilled in the art, such as an in-situ curing process, that is, the curing process is performed in the chamber where the aforementioned etching is performed. The source gas used to form the sidewall material layer 108 is CH ₄ or SiCl ₄ /O ₂ .

Next, as shown in FIG. 1E, the sidewall material layer 108 is etched to form sidewalls on both sides of the stacked structure 107. 108 were removed.

Next, the capping layer 103 and the high-k dielectric layer 102 are sequentially etched, and the etching is terminated when the interface layer 101 is exposed. The etching gas for etching the capping layer 103 and the high-k dielectric layer 102 includes Cl ₂ , BCl ₃ , NF ₃ , CH ₄ and the like.

Next, as shown in FIG. 1F , overetching is performed on the capping layer 103 and the high-k dielectric layer 102 to further reduce the widths of the capping layer 103 and the high-k dielectric layer 102 . It should be noted that the over-etching is optional, and after the over-etching is completed, the width of the stacked structure 107 is still smaller than the widths of the covering layer 103 and the high-k dielectric layer 102 .

So far, all the process steps implemented by the method according to the exemplary embodiment of the present invention are completed. Next, the fabrication of the entire semiconductor device can be completed through a subsequent process, which is exactly the same as a traditional semiconductor device processing process. According to the present invention, a dummy gate structure with the following structural features can be formed on a semiconductor substrate: the width of the cover layer and the high-k dielectric layer in the dummy gate structure is greater than the width of the sacrificial gate electrode layer, further improving the final formation performance of semiconductor devices.

Referring to FIG. 2 , there is shown a flowchart of a method for forming a dummy gate structure according to an exemplary embodiment of the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

In step 201, a semiconductor substrate is provided, and a high-k dielectric layer, a cover layer and a sacrificial gate electrode layer are sequentially formed on the semiconductor substrate;

In step 202, a patterned first hard mask layer is formed on the sacrificial gate electrode layer;

In step 203, using the patterned first hard mask layer as a mask, etching the sacrificial gate electrode layer to form a laminated structure on the covering layer;

In step 204, a layer of sidewall material surrounding the laminated structure is formed;

In step 205, etching the sidewall material layer to form sidewalls on both sides of the laminated structure;

In step 206, the capping layer and the high-k dielectric layer are sequentially etched.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (10)

1. a kind of manufacture method of semiconductor devices, including：

Semiconductor substrate is provided, high k dielectric layer, coating and sacrificial gate dielectric layer are sequentially formed on the semiconductor substrate；

Patterned first hard mask layer is formed in the sacrificial gate dielectric layer；

Using patterned first hard mask layer as mask, the sacrificial gate dielectric layer is etched, is formed on the coating Laminated construction, the width of the laminated construction is equal to the width for the metal gates being subsequently formed；

Form the side-wall material layer for surrounding the laminated construction；

The side-wall material layer is etched, to form side wall in the both sides of the laminated construction；

The coating and the high k dielectric layer are etched successively.

2. according to the method described in claim 1, it is characterised in that in the etching to the coating and the high k dielectric layer Afterwards, in addition to overetched step is implemented, further to reduce the width of the coating and the high k dielectric layer.

3. method according to claim 2, it is characterised in that after the overetch terminates, the width of the laminated construction Less than the coating and the width of the high k dielectric layer.

4. according to the method described in claim 1, it is characterised in that be also formed with boundary layer below the high k dielectric layer.

5. method according to claim 4, it is characterised in that the material of the boundary layer includes oxide.

6. according to the method described in claim 1, it is characterised in that the material of the high k dielectric layer is hafnium oxide；The covering The material of layer is titanium nitride.

7. according to the method described in claim 1, it is characterised in that the material of first hard mask layer include dielectric material, Metal and its nitride, polysilicon or its combination.

8. method according to claim 7, it is characterised in that the material of first hard mask layer is to use chemical gaseous phase The dielectric material of depositing operation formation.

9. according to the method described in claim 1, it is characterised in that the source gas that the formation side-wall material layer is used is CH₄ Or SiCl₄/O₂。

10. method according to claim 9, it is characterised in that the side-wall material layer is formed using in-situ solidifying technique.