CN104090625A - Current mirror for low supply voltage - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, in particular to a current mirror. The current mirror of the present invention is characterized in that the current mirror is composed of PMOS transistors MP1, MP2, NMOS transistor MN1, capacitors C1, C2, resistor R1, input current source, output terminal current source and bias current source; wherein, MP1 The source is connected to the power supply VCC, its gate is connected to the gate of MP2, and its drain is connected to the positive pole of the input current source; the negative pole of the input current source is grounded to VSS; the drain of MN1 is connected to the power supply VCC, and its gate is connected to the positive pole of the input current source , its source is connected to the positive pole of the bias current source, and its substrate is connected to the connection point between the MP1 gate and the MP2 gate through R1; the connection point between the source of MP1 and the drain of MN1 is connected to the gate of MN1 through C1 and C2 in turn The connection point with the positive pole of the input current source; the source of MP2 is connected to the power supply VCC, and its drain is connected to the positive pole of the output current source. The beneficial effect of the invention is that it is suitable for use under low power supply voltage; meanwhile, the PSR of the current mirror is improved. The invention is particularly applicable to current mirror circuits.

Description

A Current Mirror for Low Supply Voltage

technical field

The invention relates to the technical field of integrated circuits, in particular to a current mirror.

Background technique

A current mirror is an important circuit unit in an analog circuit. It can be used as a bias unit or a signal processing unit, and is widely used in analog circuits and radio frequency circuits.

FIG. 1 is a schematic diagram of an existing current mirror circuit, which is composed of an input current source I _in , an output current source I _out and PMOS transistors MP1 and MP2. Among them, the gate and drain of the MP1 tube are short-circuited, so the overdrive voltage of the MP1 tube is:

V _OV1 = V _SG1 −|V _THP1 |

The source-drain voltage of the MP1 tube is:

V _SD1 = V _SG1

Where |V _THP1 | is the absolute value of the threshold voltage of the PMOS transistor MP1, and V _SG1 is the voltage between the source and the gate of the MP1 transistor. From the above two formulas, it can be seen that V _SD1 is greater than the overdrive voltage V _OV1 of MP1 by the absolute value of the threshold voltage of PMOS transistor MP1, which leads to a reduction in voltage margin. Therefore, this traditional current mirror circuit does not Suitable for operation at low supply voltages.

Contents of the invention

The object of the present invention is to propose a current mirror suitable for low power supply voltage in view of the above-mentioned problem that the traditional current mirror circuit is not suitable for working under low power supply voltage.

The technical solution of the present invention is a current mirror for low power supply voltage, which is characterized in that the current mirror is composed of PMOS transistors MP1 and MP2, NMOS transistor MN1, capacitors C1 and C2, resistor R1, input current source, and output terminal The current source and the bias current source are composed; among them, the source of MP1 is connected to the power supply VCC, its gate is connected to the gate of MP2, and its drain is connected to the positive pole of the input current source; the negative pole of the input current source is grounded to VSS; the drain of MN1 Connect to the power supply VCC, its gate is connected to the positive pole of the input current source, its source is connected to the positive pole of the bias current source, and its substrate is connected to the connection point between the gate of MP1 and the gate of MP2 through R1; the negative pole of the bias current source is grounded to VSS ; The connection point between the source of MP1 and the drain of MN1 is connected to the connection point between the gate of MN1 and the positive pole of the input current source through C1 and C2 in turn; the source of MP2 is connected to the power supply VCC, and its drain is connected to the positive pole of the output current source; output The negative terminal of the current source is grounded to VSS.

The beneficial effect of the present invention is that it is suitable for use under low power supply voltage; at the same time, the PSR of the current mirror (suppression of power supply noise) is also improved.

Description of drawings

Fig. 1 is a schematic diagram of a traditional current mirror structure;

Fig. 2 is a schematic structural diagram of the current mirror of the present invention.

Detailed ways

The specific embodiment of the present invention is described below in conjunction with accompanying drawing

As shown in Figure 2, the current mirror of the present invention is made of PMOS tubes MP1, MP2, NMOS tube MN1, capacitors C1, C2, resistor R1, input current source, output terminal current source and bias current source; wherein, MP1 The source is connected to the power supply VCC, its gate is connected to the gate of MP2, and its drain is connected to the positive pole of the input current source; the negative pole of the input current source is grounded to VSS; the drain of MN1 is connected to the power supply VCC, and its gate is connected to the positive pole of the input current source , its source is connected to the positive pole of the bias current source, and its substrate is connected to the connection point between the gate of MP1 and the gate of MP2 through R1; the negative pole of the bias current source is grounded to VSS; the connection point of the source of MP1 and the drain of MN1 Connect the connection point between the gate of MN1 and the positive pole of the input current source through C1 and C2 in turn; the source of MP2 is connected to the power supply VCC, and its drain is connected to the positive pole of the output current source; the negative pole of the output current source is grounded to VSS.

Compared with the existing current mirror, the gate of the MP1 transistor is not shorted to the drain, but the drain voltage of the MP1 transistor is lowered through a source-following amplifier composed of an NMOS transistor MN1 and a bias current source I _b The gate-source voltage V _GS1 of a MN1 transistor is connected in series with a large resistor to the gate of the MP1 transistor. The NMOS transistor MN1 in the source follower amplifier works in the subthreshold region, and the V _GS1 of the MN1 transistor is approximately equal to the threshold of the NMOS transistor. Voltage V _THN1 , because the threshold voltage V _THN1 of the NMOS transistor is smaller than the absolute value |V _THP1 | of the threshold voltage of the PMOS transistor MP1, so the MP1 transistor can still work in the saturation region and realize the principle of current mirroring. At the same time, the drain voltage of the MP1 tube is increased by V _THN1 , and the voltage between the source and the drain of the MP1 tube is reduced by V _THN1 . The voltage between the source and drain of the MP1 tube is:

V _SD(MP1) ≈ V _SG(MP1) -V _THN1 (1)

In the formula (1), V _{SG (MP1)} represents the voltage between the source and the gate of the MP1 tube.

In this way, the current mirror saves the voltage margin of V _THN1 , making the current mirror especially suitable for working under low power supply voltage.

The invention has the characteristic of high PSR, and the capacitor C1, like the existing current mirror, couples the power supply noise to the gate of the PMOS tube to improve the PSR of the current mirror. However, in the branch composed of the NMOS transistor MN1 and the bias current source _Ib , the source of the MN1 transistor is greatly affected by power supply noise. Using the power path formed by capacitors C1 and C2 and the power path of the drain of the MN1 tube, it can be seen that

${\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&ap;</span>{\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; CC</span>}}\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&ap;</span>{\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; CC</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

A large resistor R1 is introduced here to reduce the voltage division of the power supply noise from the gates of MP1 and MP2 to the source of MN1.

${\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&ap;</span>{\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>{\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; CC</span>}}<span\; class="notranslate">\; \{</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \}</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

From formula (2) and formula (3), it can be concluded that the gates of MP1 and MP2 are affected by power supply noise as:

${\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&ap;</span>{\stackrel{<span\; class="notranslate">\; ~</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}}_{\mathrm{<span\; class="notranslate">\; CC</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In formula (2)～(4) Refers to power supply noise, and Respectively represent the source of MN1 tube and the gates of MP1 and MP2 Affected voltage small signal, g _m(MN1) refers to the transconductance of the MN1 tube. From formula (4), it can be concluded that the gates of MP1 and MP2 are affected by power supply noise and the gain is approximately 1, which ensures that the gate-source voltage of MP1 and MP2 is close to zero in all frequency ranges, improving the PSR of the current mirror.

In addition, the capacitor C2 and MP1 form a Miller compensation structure, combined with the capacitor C1, the gate of the MP1 transistor is set as a high-capacitance node. Through the setting of the large resistance R1, the main pole of the feedback loop in this structure can be set at the gate of the MP1 tube, so as to ensure the stable operation of the system.

Claims (1)

1. for a current mirror for low supply voltage, it is characterized in that, this current mirror is managed MP1, MP2 by PMOS, and NMOS manages MN1, capacitor C 1, C2, and resistance R 1, input current source, output current source and bias current sources form; Wherein, the source electrode of MP1 meets power supply VCC, and its grid connects the grid of MP2, and its drain electrode connects the positive pole of input current source; The minus earth VSS of input current source; The drain electrode of MN1 meets power supply VCC, and its grid connects the positive pole of input current source, and its source electrode connects the positive pole of bias current sources, and its substrate connects the tie point of MP1 grid and MP2 grid by R1; The minus earth VSS of bias current sources; The tie point of the source electrode of MP1 and the drain electrode of MN1 connects the tie point of MN1 grid and input current source positive pole successively by C1, C2; The source electrode of MP2 meets power supply VCC, and its drain electrode connects the positive pole of output current source; The minus earth VSS of output current source.