CN103199807B - Division based on inverter input structure compensates two-stage calculation amplifier - Google Patents

Abstract

The invention belongs to electronic technology field, relate to the frequency acquisition and tracking of operational amplifier in analog integrated circuit.Comprise two stage amplifer, first order amplifier is by NMOS tube M _1N, M _2N, M ₃, M ₄with PMOS M _1P, M _2P, M ₀composition, second level amplifier is by PMOS M _5Pwith NMOS tube M _5Ncomposition.The present invention is by traditional miller capacitance C _mbe split into C _m1and C _m2two parts, complete the frequency compensation of operational amplifier with this; Wherein first frequency building-out capacitor C _m1be connected between the output of first order amplifier and the output of whole two-stage calculation amplifier, second frequency building-out capacitor C _m2be connected to NMOS tube M in first order amplifier _2Nsource electrode and NMOS tube M ₄drain junction and the output of whole two-stage calculation amplifier between.The non-dominant pole of the present invention and parasitic parameter have nothing to do, and have stronger robustness, have higher unity gain bandwidth simultaneously and export Slew Rate.

Description

Split Compensation Two-Stage Operational Amplifier Based on Inverter Input Structure

technical field

The invention belongs to the field of electronic technology and relates to the frequency compensation technology of operational amplifiers in analog integrated circuits.

Background technique

Increasing demand from the semiconductor and communications industries has accelerated the development of analog integrated circuits. As an important module in analog integrated circuits, operational amplifiers are widely used in bandgap references, DC-DC converters and data converters. Commonly used operational amplifiers include single-stage amplifiers, two-stage operational amplifiers, and three-stage operational amplifiers. Two-stage operational amplifiers are widely used because of their high gain and wide output swing. However, since the two-stage operational amplifier has two close low-frequency poles, frequency compensation is required to push the two close low-frequency poles apart.

The frequency compensation technology commonly used in two-stage operational amplifiers is Miller compensation. Its circuit structure is shown in Figure 1. It uses pole splitting to stabilize the output of the operational amplifier. However, traditional Miller compensation produces a right-half-plane zero due to the bidirectional path of the Miller capacitance C _m , thereby reducing the unity-gain bandwidth (GBW) of the op amp.

In order to eliminate the right-half-plane zero point of the traditional Miller-compensated two-stage operational amplifier, different solutions are given in the prior art: 1) As shown in Figure 2, a resistor R is connected in series with the Miller capacitor C _m to eliminate the right-half plane zero point Half-plane zero point, but the required resistor resistance is larger, which consumes more chip area; 2) As shown in Figure 3, a voltage (or current) buffer is connected in series on the Miller capacitor to destroy its bidirectional path so that Eliminate the right-half-plane zero point, but this requires additional bias current, making the circuit structure more complex; 3) cascode compensation (as shown in Figure 4), using the principle of the current buffer can make the non-dominant pole of the operational amplifier It is pushed to a higher frequency position and does not require additional bias current, but its performance parameters are related to the parasitic capacitance of the first-stage output, and its reliability is low.

Existing searches use traditional Miller compensation, and there are searches that use cascode compensation to improve the performance of op amps. But at present, it can improve the performance of the operational amplifier, and the report of frequency compensation with strong robustness has not been verified yet.

Contents of the invention

In order to eliminate the inherent right-half plane zero point of the two-stage operational amplifier based on Miller compensation, the present invention provides a split-compensated two-stage operational amplifier. The operational amplifier adopts an inverter input structure, and improves the small-signal and large-signal performance of the operational amplifier on the basis of eliminating the inherent right-half-plane zero point of the two-stage operational amplifier, and has strong robustness.

Detailed technical scheme of the present invention is as follows:

The split compensation two-stage operational amplifier based on the inverter input structure, as shown in Figures 5 and 6, includes two-stage operational amplifiers, and the first-stage operational amplifier consists of NMOS transistors M _1N , M _2N , M ₃ , M ₄ and PMOS transistors Composed of M _1P , M _2P , and M ₀ , the second-stage operational amplifier is composed of PMOS transistor M _5P and NMOS transistor M _5N .

In the first-stage operational amplifier, the source of the PMOS transistor _M0 is connected to the power supply VDD, the gate of the PMOS transistor _M0 is connected to the gates _of the NMOS transistors M3 and _M4 , and the drains of the NMOS transistor _M1N and the PMOS transistor _M1P . The drain of the PMOS transistor M0 is the source of the PMOS transistors M _1P and M _{2P ;} the gates of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected and used as the inverting input terminal of the entire two-stage operational amplifier, and the PMOS transistors M _2P and The gates of the NMOS transistor M _2N are interconnected and used as the positive input of the entire two-stage operational amplifier; the drains of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected, and the drains of the PMOS transistor M _2P and the NMOS transistor M _2N are interconnected. Connected and used as the output terminal of the first-stage operational amplifier; the source of the NMOS transistor M _1N is connected to the drain of the NMOS transistor M ₃ , the source of the NMOS transistor M _2N is connected to the drain of the NMOS transistor M ₄ , and the NMOS transistors M ₃ and M ₄ 's source is grounded.

In the second-stage operational amplifier, the source of the PMOS transistor M _5P is connected to the power supply VDD, the gates of the PMOS transistor M _5P and the NMOS transistor M _5N are interconnected and connected to the output end of the first-stage operational amplifier, and the PMOS transistor M _5P and the NMOS transistor M 5P are connected to each other. The drains of the M _5N are interconnected and serve as the output terminals of the entire two-stage operational amplifier, and the source of the NMOS transistor M _5N is grounded.

A first frequency _compensation capacitor C _m1 is connected between the output terminal of the first-stage operational amplifier and the output terminal of the entire two _- stage operational amplifier; A second frequency compensation capacitor C _m2 is connected between the drain connection point and the output terminal of the entire two-stage operational amplifier.

The invention splits the traditional Miller capacitor C _m into two parts, C _m1 and C _m2 , so as to complete the frequency compensation of the operational amplifier. The differential pair of the first stage op amp consists of inverters M _1N and M _1P . The current source consists of M ₀ operating in the linear region and the critical saturation region. The gates of M0, M3, and M4 are connected to the drains of M _1N and M _1P to form a self-bias circuit. The second-stage operational amplifier consists of a PMOS transistor M _5P and an NMOS transistor M _5N to form an inverter input structure.

The present invention has the following characteristics:

1. The resistance of C _m2 and point A can form a left-half plane zero to compensate the negative phase shift produced by the non-dominant pole.

2. The operational amplifier of the present invention adopts self-bias technology, and does not require additional bias circuits. The self-bias circuit can suppress the influence of the PVT (process, voltage, temperature) of the circuit. For example, if VDD increases, then _VGS0 increases, and the bias current _I1 increases, then the voltage at point B increases, while _VGS0 decreases, so as to offset the impact of VDD increase on the circuit.

3. The sub-pole of the operational amplifier of the present invention has nothing to do with the parasitic capacitance and has strong robustness.

4. The current source M ₀ works in the linear region, and can provide a larger current during the large signal conversion process to increase the slew rate of the circuit.

5. The two-stage input of the operational amplifier of the present invention adopts an inverter input structure, which can increase the transconductance of the operational amplifier and improve the gain and unity gain bandwidth of the operational amplifier.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure of a Miller-compensated two-stage operational amplifier in the prior art.

FIG. 2 is a schematic diagram of a circuit structure of a two-stage operational amplifier with Miller compensation and series resistance in the prior art.

FIG. 3 is a schematic diagram of a circuit structure of a two-stage operational amplifier with Miller compensation plus a series voltage buffer in the prior art.

FIG. 4 is a schematic diagram of a circuit structure of a two-stage operational amplifier with folded cascode compensation in the prior art.

FIG. 5 is a schematic diagram of the circuit structure of the split compensation two-stage operational amplifier provided by the present invention.

FIG. 6 is a specific circuit diagram of a split-compensated two-stage operational amplifier based on an inverter input structure provided by the present invention.

FIG. 7 is a small-signal equivalent circuit of a split-compensated two-stage operational amplifier based on an inverter input structure provided by the present invention.

Detailed ways

The split compensation two-stage operational amplifier based on the inverter input structure, as shown in Figures 5 and 6, includes two-stage operational amplifiers, and the first-stage operational amplifier consists of NMOS transistors M _1N , M _2N , M ₃ , M ₄ and PMOS transistors Composed of M _1P , M _2P , and M ₀ , the second-stage operational amplifier is composed of PMOS transistor M _5P and NMOS transistor M _5N .

In the first-stage operational amplifier, the source of the PMOS transistor _M0 is connected to the power supply VDD, the gate of the PMOS transistor _M0 is connected to the gates _of the NMOS transistors M3 and _M4 , and the drains of the NMOS transistor _M1N and the PMOS transistor _M1P . The drain of the PMOS transistor M0 is the source of the PMOS transistors M _1P and M _{2P ;} the gates of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected and used as the inverting input terminal of the entire two-stage operational amplifier, and the PMOS transistors M _2P and The gates of the NMOS transistor M _2N are interconnected and used as the positive input of the entire two-stage operational amplifier; the drains of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected, and the drains of the PMOS transistor M _2P and the NMOS transistor M _2N are interconnected. Connected and used as the output terminal of the first-stage operational amplifier; the source of the NMOS transistor M _1N is connected to the drain of the NMOS transistor M ₃ , the source of the NMOS transistor M _2N is connected to the drain of the NMOS transistor M ₄ , and the NMOS transistors M ₃ and M ₄ 's source is grounded.

In the second-stage operational amplifier, the source of the PMOS transistor M _5P is connected to the power supply VDD, the gates of the PMOS transistor M _5P and the NMOS transistor M _5N are interconnected and connected to the output end of the first-stage operational amplifier, and the PMOS transistor M _5P and the NMOS transistor M 5P are connected to each other. The drains of the M _5N are interconnected and serve as the output terminals of the entire two-stage operational amplifier, and the source of the NMOS transistor M _5N is grounded.

A first frequency _compensation capacitor C _m1 is connected between the output terminal of the first-stage operational amplifier and the output terminal of the entire two _- stage operational amplifier; A second frequency compensation capacitor C _m2 is connected between the drain connection point and the output terminal of the entire two-stage operational amplifier.

The invention splits the traditional Miller capacitor C _m into two parts, C _m1 and C _m2 , so as to complete the frequency compensation of the operational amplifier. The differential pair of the first stage op amp consists of inverters M _1N and M _1P . The current source consists of M ₀ operating in the linear region and the critical saturation region. The gates of M0, M3, and M4 are connected to the drains of M _1N and M _1P to form a self-bias circuit. The second-stage operational amplifier consists of a PMOS transistor M _5P and an NMOS transistor M _5N to form an inverter input structure.

The small-signal equivalent circuit of the operational amplifier of the present invention is shown in FIG. 7 . Analyzing its equivalent circuit, the small signal transfer function is:

${\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; \&nu;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; p</span>}\mathrm{<span\; class="notranslate">\; e</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; the\; s</span>}}{{\mathrm{<span\; class="notranslate">\; p</span>}}_{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; B</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

in:

g _me =g _m1N +g _o4 +g _o1N (2)

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; P</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; P</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; N</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

A _dc = g _m1 R ₁ g _m2 R ₂ (5)

${\mathrm{<span\; class="notranslate">\; p</span>}}_{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

g _m2 =g _m5N +g _m5P , R ₁ ≈R _1N , R ₂ =R _5N //R _5P . g _m1 and g _m2 are the equivalent transconductance of the first and second op amps. g _me represents the equivalent admittance of point A, C _me represents the equivalent Miller capacitance, and C _L represents the equivalent load capacitance. A _dc and p _-3dB represent the DC gain and dominant pole of the operational amplifier, respectively.

Can draw the non-dominant pole of operational amplifier of the present invention from (1) to be:

${\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}^{<span\; class="notranslate">\; \&prime;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&PlusMinus;</span>\mathrm{<span\; class="notranslate">\; j</span>}\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 4</span>}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}^{<span\; class="notranslate">\; \&prime;</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

in

${{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

It can be seen from formula (10) that the non-dominant poles of the operational amplifier of the present invention have nothing to do with parasitic parameters, so it has strong robustness.

It can be seen from (4) that the equivalent Miller capacitance of the operational amplifier of the present invention is not the sum of two Miller capacitances, and is smaller than the sum of two Miller capacitances.

The unity gain bandwidth (GBW) and the slew rate (SR) of the operational amplifier of the present invention are:

$\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; B</span>}\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

$\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; e</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

It can be seen from equations (12) and (13) that the GBW and SR of the operational amplifier of the present invention are both improved due to the smaller equivalent Miller capacitance.

Claims (1)

1. A split-compensated two-stage operational amplifier based on an inverter input structure, including two-stage operational amplifiers. The first-stage operational amplifier consists of NMOS transistors M _1N , M _2N , M ₃ , M ₄ and PMOS transistors M _1P , M _2P , Composed of M ₀ , the second-stage operational amplifier is composed of PMOS transistor M _5P and NMOS transistor M _5N ; In the first-stage operational amplifier, the source of the PMOS transistor _M0 is connected to the power supply VDD, the gate of the PMOS transistor _M0 is connected to the gates _of the NMOS transistors M3 and _M4 , and the drains of the NMOS transistor _M1N and the PMOS transistor _M1P . The drain of the PMOS transistor M0 is the source of the PMOS transistors M _1P and M _{2P ;} the gates of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected and used as the inverting input terminal of the entire two-stage operational amplifier, and the PMOS transistors M _2P and The gates of the NMOS transistor M _2N are interconnected and used as the positive input of the entire two-stage operational amplifier; the drains of the PMOS transistor M _1P and the NMOS transistor M _1N are interconnected, and the drains of the PMOS transistor M _2P and the NMOS transistor M _2N are interconnected. Connected and used as the output terminal of the first-stage operational amplifier; the source of the NMOS transistor M _1N is connected to the drain of the NMOS transistor M ₃ , the source of the NMOS transistor M _2N is connected to the drain of the NMOS transistor M ₄ , and the NMOS transistors M ₃ and M The source of ₄ is grounded; In the second-stage operational amplifier, the source of the PMOS transistor M _5P is connected to the power supply VDD, the gates of the PMOS transistor M _5P and the NMOS transistor M _5N are interconnected and connected to the output end of the first-stage operational amplifier, and the PMOS transistor M _5P and the NMOS transistor M 5P are connected to each other. The drains of M _5N are interconnected and used as the output end of the entire two-stage operational amplifier, and the source of NMOS transistor M _5N is grounded; A first frequency _compensation capacitor C _m1 is connected between the output terminal of the first-stage operational amplifier and the output terminal of the entire two _- stage operational amplifier; A second frequency compensation capacitor C _m2 is connected between the drain connection point and the output terminal of the entire two-stage operational amplifier.