CN104051614A - Embedded resistor - Google Patents

Abstract

The present invention discloses an embedded resistor, which includes a first interlayer dielectric layer, a cap layer, a resistor layer and a cover film. The first interlayer dielectric layer is located on a substrate. The cap layer is located on the first interlayer dielectric layer, wherein the cap layer has a groove. The resistor layer conforms to the groove and has a U-shaped cross-sectional structure. The cover film is located in the groove and on the resistor layer; or, an embedded resistor, which includes a first interlayer dielectric layer, a cap layer and a block resistor layer. The first interlayer dielectric layer is located on a substrate. The cap layer is located on the first interlayer dielectric layer, wherein the cap layer has a groove. The block resistor layer is located in the groove.

Description

Embedded resistor

technical field

The present invention relates to a resistor, and in particular to an embedded resistor.

Background technique

In the manufacturing process of semiconductor chips, polysilicon materials are often used to form high-impedance resistors, which can replace transistors (transistors) as loads. For example, the transistors in static random access memory (SRAM) can be replaced by load resistors formed by polysilicon, so that the number of transistors in the SRAM is reduced, and the purpose of saving costs and improving integration is achieved.

Common load resistors can be roughly divided into two types: polysilicon resistor and diffusion resistor. The polysilicon resistor includes a doped polysilicon layer, and its resistance can be adjusted and controlled by the dopant concentration in the polysilicon layer. As for the diffusion resistance, ion implantation is used to form a doped layer in a semiconductor substrate, and then thermal diffusion is used to activate the ions in the doped layer to adjust its resistance. Generally speaking, whether it is a polysilicon resistor or a diffused resistor, most of them have a sandwich structure, and the two sides of the structure are defined as a low-impedance area, which is used to make contact plugs for internal connections, so that the resistors are electrically connected to other wires. , as for the high-impedance area sandwiched between the low-impedance areas on both sides, it is the main structure of the resistor, which is used to provide the high impedance required in electronic components or circuit design. With the diversification and miniaturization of electronic products, the circuit design of load resistors is becoming more and more complex, and the conditions for the volume occupied by the load resistor, the position formed, and the high impedance it can provide are becoming more and more stringent. .

Contents of the invention

The purpose of the present invention is to provide an embedded resistor, which firstly forms a trench in the material layer, and then fills the resistor material therein to form a U-shaped cross-sectional structure or a block-shaped embedded resistor.

To achieve the above purpose, the present invention provides an embedded resistor comprising a first interlayer dielectric layer, a capping layer, a resistor layer and a capping film. The first interlayer dielectric layer is located on a substrate. The capping layer is located on the first interlayer dielectric layer, wherein the capping layer has a groove. The resistive layer conforms to cover the groove, so it has a U-shaped cross-sectional structure. A capping film is in the trench and on the resistive layer.

The invention provides an embedded resistor, which includes a first interlayer dielectric layer, a cover layer and a block resistance layer. The first interlayer dielectric layer is located on a substrate. The capping layer is located on the first interlayer dielectric layer, wherein the capping layer has a groove. The bulk resistive layer is located in the trench.

Based on the above, the present invention proposes a buried resistor, which first forms a trench in a material layer such as a cover layer, and then forms a resistance layer or a block resistance layer with a U-shaped cross-sectional structure in the trench to form a buried resistor. built-in resistors. In this way, the present invention can solve the problem of under-etching or over-etching of trenches formed in different regions (such as transistor regions and resistance regions) where contact plugs are to be formed due to excessive differences in depth; The contact plugs of the trenches have the problem of insufficient hole filling or overfilling due to the large difference in length; The layer is completely removed by grinding. Furthermore, since the present invention is a buried resistor, it can avoid the problem of over-etching the bottom layer of the resistor layer (undercut) when etching the resistor layer for patterning.

Description of drawings

1-4 are schematic cross-sectional views of a fabrication process for embedded resistors according to a first embodiment of the present invention;

5 is a schematic cross-sectional view of a fabrication process of an embedded resistor according to another embodiment of the present invention;

6-9 are cross-sectional schematic diagrams of the fabrication process of embedded resistors according to a second embodiment of the present invention;

10 is a schematic cross-sectional view of a fabrication process of an embedded resistor according to another embodiment of the present invention;

11 is a schematic cross-sectional view of a buried resistor with a sacrificial gate according to the first embodiment of the present invention;

12 is a schematic cross-sectional view of a buried resistor with a sacrificial gate according to a second embodiment of the present invention.

Symbol Description

10: Insulation structure

20, 20a: buffer layer

110, 110a: base

120: first interlayer dielectric layer

130: Overlay

140, 140a: resistance layer

140', 140a': bulk resistance layer

142, 142a: vertical part

150, 150a: cover film

160: second interlayer dielectric layer

A: District 1

B: Second District

C1: socket contact plug

C2: contact plug

D: source/drain region

DG: sacrificial gate

E1, E2: Etching process

G: grid

K: epitaxial structure

M: MOS transistor

P1, P2: patterned photoresist

R1, R2, R3: Groove

T1, T2, T4, T5, T7: top surface

T3, T6: top

Detailed ways

1-4 are cross-sectional schematic diagrams illustrating a fabrication process of a buried resistor according to a first embodiment of the present invention. As shown in FIG. 1 , a substrate 110 includes a first region A and a second region B, wherein the first region A in this embodiment is a transistor region, and the second region B is a resistor region. A first interlayer dielectric layer 120 is formed on the substrate 110 in the first region A and the second region B. The first interlayer dielectric layer 120 can be, for example, an oxide layer, but the invention is not limited thereto. A MOS transistor M is disposed in the first interlayer dielectric layer 120 of the first region A. As shown in FIG. The plurality of insulating structures 10 are located in the second region B and the first region A next to the MOS transistor M, respectively. In this embodiment, the second region B is to form a resistor above the first interlayer dielectric layer 120, so the insulating structure 10 is specially provided as a block insulating structure in most of the substrate 10 of the second region B, so as to To prevent electric leakage when subsequently formed resistors or contact plugs connecting resistors penetrate through the first interlayer dielectric layer 120 to the substrate 110 , but the invention is not limited thereto. In other embodiments, the insulating structure 10 in the base 110 of the second region B may also consist of a plurality of insulating structures, or there may be no insulating structure in the base 110 of the second region B. In addition, the insulating structure 10 disposed in the base 110 of the first region A is to electrically insulate the MOS transistor M from other unillustrated semiconductor elements such as transistors.

Next, a capping layer 130 is formed on the first interlayer dielectric layer 120 . The capping layer 130 is, for example, a silicon nitride layer, or a carbon-doped silicon nitride layer, etc., but the invention is not limited thereto. The cover layer 130 can isolate a gate G of the MOS transistor M (especially when the gate G is a metal gate), so as to prevent it from being damaged in the subsequent manufacturing process, or electrically connected to the metal wires formed on the top subsequently. connected due to leakage or short circuit. Then, for example, a photolithography and etching process is performed to pattern the capping layer 130 and the first interlayer dielectric layer 120 to form a plurality of trenches (not shown) to expose a source/drain region D of the MOS transistor M , and then filling metal (not shown) and planarizing it to form a plurality of slot contact plugs C1 (Slot Contacts) or a plurality of columnar contact plugs (not shown) in the first interlayer dielectric layer 120 and the capping layer 130 , and is electrically connected to the MOS transistor M. The MOS transistor M can also include an epitaxial structure K in the substrate 110 on the side of the gate G and can partially overlap the source/drain region D; and a metal silicide (not shown) is formed between the source/drain region D and the Between the socket contact plugs C1 , the metal silicide can be formed before or after the formation of the trenches to form the socket contact plugs C1 . The socket contact plug C1 may be made of metal such as tungsten or copper, but the invention is not limited thereto. Afterwards, a patterned photoresist P1 is formed to cover the first region A, but expose the region where the resistance is to be formed in the second region B. The method of forming the patterned photoresist P1 can be, for example, firstly cover a photoresist (not shown) in its entirety, and then pattern it.

Then an etching process E1 is performed, and the exposed cap layer 130 is etched together with the patterned photoresist P1 to form a trench R1 in the cap layer 130 . In this embodiment, the capping layer 130 and the first interlayer dielectric layer 120 are made of different materials, so when performing the etching process E1, the first interlayer dielectric layer 120 can be used as an etching stop layer to stop the etching at the first but in other embodiments, the etching process E1 may also etch part of the first interlayer dielectric layer 120, so that the trench R1 is located between the cap layer 130 and part of the first layer in the dielectric layer 120 . As shown in FIG. 2 , after the etching process E1 is completed, the patterned photoresist P1 is removed and the residue after etching is removed.

As shown in FIG. 3 , a buffer layer 20 is selectively formed to conformably cover the capping layer 130 and the trench R1 . The buffer layer 20 can be, for example, an oxide layer, but the invention is not limited thereto. The buffer layer 20 can further insulate the socket contact plug C1 to prevent the socket contact plug C1 from being damaged during subsequent manufacturing processes such as metal layers such as resistors formed thereon. Next, a resistive layer (not shown) and a capping film (not shown) are sequentially formed to completely cover the capping layer 130 (or buffer layer 20 ), and the buffer layer 20 (or capping layer 130 ) is used as a stop layer A planarization process such as chemical mechanical polishing is performed to remove the resistive layer (not shown) and the capping film (not shown) directly above the capping layer 130 to form a resistive layer 140 conforming to cover the trench R1 and a cover film 150 are located on the resistive layer 140 in the trench R1 and fill up the trench R1 , so that the resistive layer 140 has a U-shaped cross-sectional structure. The resistance layer 140 is, for example, a titanium nitride layer or a tantalum nitride layer, but the invention is not limited thereto. The cover film 150 can be, for example, a dielectric material such as a silicon nitride layer.

In this way, the buffer layer 20 is disposed on the cover layer 130 , but the resistance layer 140 and the cover film 150 are exposed. In this embodiment, the buffer layer 20 extends into the trench R1 and covers the trench R1 but is located under the resistance layer 140 . Moreover, a top surface T1 of the buffer layer 20 on the cover layer 130 is flush with a top surface T2 of the cover film 150; the U-shaped resistance layer 140 has at least one vertical portion 142 parallel to the side of the trench R1, and The top surface T2 of the cover film 150 is flush with the top T3 of the vertical portion 142 .

In another embodiment, as shown in FIG. 5 , a block resistance layer 140' is used to replace the resistance layer 140 and the cover film 150 of the first embodiment described above. In other words, after the buffer layer 20 is formed, a resistive layer (not shown) is formed to completely cover the cover layer 130 (or buffer layer 20 ), and the trench R1 is filled, and then the buffer layer 20 (or cover layer 130 ) is used as a stop layer to perform a planarization process such as chemical mechanical polishing to remove the resistance layer outside the trench R1, so that the block resistance layer 140' can be formed. In this embodiment, no additional cap film 150 is formed, and a top surface T7 of the bulk resistance layer 140' is flush with the top surface T1 of the buffer layer 20.

The steps in FIG. 3 of the first embodiment are continued below, but the following manufacturing process steps are also applicable to the aforementioned embodiment in FIG. 5 .

As shown in FIG. 4, a second interlayer dielectric layer 160 is formed on the cover layer 130 (or buffer layer 20), the resistance layer 140 and the cover film 150, and then a plurality of contact plugs C2 (Contact Plugs) are formed, Wherein at least two contact plugs are located in the second interlayer dielectric layer 160 and are respectively electrically connected to the two ends of the resistance layer 140, while the remaining contact plugs are located in the second interlayer dielectric layer 160, the capping layer 130 and the buffer layer. 20 and are respectively electrically connected to the gate G of the MOS transistor M and the corresponding slot contact plug C1. The second interlayer dielectric layer 160 may be, for example, an oxide layer, and it may, for example, be obtained by stacking and covering multiple manufacturing processes; the contact plug C2 may, for example, be composed of metals such as tungsten or copper, but the present invention does not limit.

In detail, the second interlayer dielectric layer (not shown) can be fully covered on the flat capping layer 130 (or buffer layer 20 ), the resistance layer 140 and the capping film 150; and then the second interlayer dielectric layer is patterned. The electrical layer 160, the buffer layer 20 and the capping layer 130 are used to form a plurality of trenches R2 in the second interlayer dielectric layer 160, the buffer layer 20 and the capping layer 130; Each contact plug C2 is formed in each trench R2 and planarized. At this time, the contact plug C2 in the second area B is electrically connected to the resistive layer 140 , and the contact plug C2 in the first area A is electrically connected to the socket contact plug C1 and the MOS transistor M.

Based on the above, generally speaking, the MOS transistor M is located in the first interlayer dielectric layer 120, and if the resistance layer 140 is located in the material layer above the capping layer 130, it will have a protruding stepped cross-sectional structure, so that The trench R2 formed by the same manufacturing process has too large a difference in depth between the first region A and the second region B, so that the problem of insufficient etching of the first region A or overetching of the second region B easily occurs; or, by Filling metal in the same manufacturing process to electrically connect the MOS transistor M and the contact plug C2 of the resistance layer 140 respectively will cause the trench R2 in the first region A to be insufficiently filled or the second trench R2 will be insufficiently filled due to the large difference in the depth of the trench R2. The metal overfill problem of the trench R2 in the second region B; even, when the second interlayer dielectric layer 160 is polished after the contact plug C2 is formed, the contact plug with a shorter height may be damaged by the second interlayer dielectric layer 160 grind and completely removed. According to the present embodiment, the resistive layer 140 is located in the cap layer 130 by embedding, so that the height difference between the contact plug C2 in the first region A and the contact plug C2 in the second region B can be shortened, without the aforementioned problems.

Furthermore, the present invention uses the embedded resistor method to form the trench R1 in the cover layer 130 first, and then fills the resistor layer 140 in the cover layer 130, which can replace the aforementioned manufacturing process and directly form a resistor layer in the cover layer 130. On a flat material layer, it is patterned by etching to form a resistor. In this way, the problem of over-etching the bottom layer of the resistive layer caused when the resistive layer is etched for patterning can be avoided.

A second embodiment is proposed below. In addition to having the advantages of the first embodiment, the problem of forming a photoresist in the first embodiment can be further improved. 6-9 are schematic cross-sectional views illustrating a fabrication process of a buried resistor according to a second embodiment of the present invention.

As shown in FIG. 6 , a substrate 110 includes a first region A and a second region B, wherein the second region B in this embodiment is a resistor region, and the first region A is a transistor region. A first interlayer dielectric layer 120 is formed on the substrate 110 in the first region A and the second region B. The first interlayer dielectric layer 120 can be, for example, an oxide layer, but the invention is not limited thereto. A MOS transistor M is disposed in the first interlayer dielectric layer 120 of the first region A. As shown in FIG. The plurality of insulating structures 10 are respectively located in the second region B and the first region A beside the MOS transistors. In this embodiment, the second region B is to form a resistor above the first interlayer dielectric layer 120, so a block insulating structure 10 is specially provided in most of the substrate 10 of the second region B to prevent subsequent formation The resistor or the contact plug connecting the resistor penetrates through the first interlayer dielectric layer 120 to the substrate 110 and leaks electricity, but the invention is not limited thereto. In other embodiments, the insulating structure 10 in the base 110 of the second region B may also consist of a plurality of insulating structures, or there may be no insulating structure in the base 110 of the second region B. In addition, the insulating structure 10 disposed in the base 110 of the first region A is to electrically insulate the transistor M from other unillustrated semiconductor elements such as transistors.

Next, a capping layer 130 is formed on the first interlayer dielectric layer 120 . The capping layer 130 is, for example, a silicon nitride layer, or a carbon-doped silicon nitride layer, etc., but the invention is not limited thereto. The capping layer 130 can isolate a gate G of the MOS transistor M (especially when the gate G is a metal gate), so as to prevent it from being damaged in the subsequent manufacturing process, or from being electrically connected to the metal subsequently formed above and causing leakage or short circuit. Then, for example, a photolithography and etching process is performed to pattern the capping layer 130 and the first interlayer dielectric layer 120 to form a trench (not shown) to expose a source/drain region D of the MOS transistor M, and then filling metal (not shown) and planarizing it to form a plurality of slot contact plugs C1 (SlotContacts) or a plurality of columnar contact plugs (not shown) in the first interlayer dielectric layer 120 and the capping layer 130 and is electrically connected to the MOS transistor M. The socket contact plug C1 can be made of metal such as tungsten or copper, but the invention is not limited thereto. The MOS transistor M can also include an epitaxial structure K in the substrate 110 on the side of the gate G and can partially overlap the source/drain region D; and a metal silicide (not shown) is formed between the source/drain region D and the Between the socket contact plugs C1 , the metal silicide can be formed before or after the formation of the trenches to form the socket contact plugs C1 .

After that, a buffer layer 20 a is formed on the flat cap layer 130 . The buffer layer 20 can be, for example, an oxide layer, but the invention is not limited thereto. The buffer layer 20 a can further insulate the socket contact plug C1 , preventing the socket contact plug C1 from being damaged during subsequent manufacturing processes such as metal layers such as resistors formed thereon. Then, a patterned photoresist P2 is formed on the buffer layer 20a. Generally speaking, in this embodiment, the buffer layer 20a is formed first and then the patterned photoresist P2 is formed, so the patterned photoresist P2 formed only on the buffer layer 20a can have better adhesion. Furthermore, the material of the buffer layer 20a is generally an oxide layer, and the material of the capping layer 130 is generally a nitride layer, and the patterned photoresist P2 also reacts with the nitride layer so that it remains and cannot be completely removed. Embodiments Forming the patterned photoresist P2 on the buffer layer 20a can solve this problem.

Then, an etching process E2 is performed to etch the exposed buffer layer 20a and part of the cover layer 130 to form a trench R3 in the buffer layer 20a and the cover layer 130, and then remove the patterned photoresist P2, As shown in Figure 7. In other embodiments, the etching process E2 may stop at the capping layer 130 and only form the trench R3 at the buffer layer 20a, the present invention is not limited thereto. Next, as shown in FIG. 8 , a resistive layer (not shown) and a capping film (not shown) are sequentially formed to completely cover the buffer layer 20 a and the capping layer 130 in the groove R3 , and the buffer layer 20 is reused as As a stop layer, a planarization process such as chemical mechanical polishing is performed to remove the resistance layer (not shown) and the cap film (not shown) directly above the buffer layer 20a, so as to form a resistance layer 140a conforming to Covering the surface of the trench R3 and a cover film 150a is located in the trench R3 and on the resistive layer 140a, so that the resistive layer 140a has a U-shaped cross-sectional structure. The resistance layer 140a is, for example, a titanium nitride layer or a tantalum nitride layer, and the capping film 150a can be, for example, a silicon nitride layer or other dielectric material, but the invention is not limited thereto. In this way, the buffer layer 20a is disposed on the cover layer 130, but the resistance layer 140a and the cover film 150a are exposed. Moreover, a top surface T4 of the buffer layer 20a on the cover layer 130 is flush with a top surface T5 of the cover film 150a; the U-shaped resistance layer 140a has at least one vertical portion 142a parallel to the side of the trench R3, and The top surface T5 of the cover film 150a is flush with the top end T6 of the vertical portion 142a.

In another embodiment, as shown in FIG. 10 , a block resistance layer 140a' is used to replace the resistance layer 140a and the cover film 150a. In other words, after the aforementioned formation of the buffer layer 20a, when forming a resistive layer (not shown) to fully cover the cap layer buffer layer 20a, that is, to fill the trench R3, and then planarize and remove the resistive layer other than the trench R3, so that A bulk resistance layer 140a' is formed. In this embodiment, the cap film 150a is not additionally formed.

Please continue the steps in FIG. 8 (or FIG. 10 ), as shown in FIG. 9 , form a second interlayer dielectric layer 160 on the buffer layer 20a, the resistance layer 140a and the cap film 150a, and form a plurality of contact plugs. C2 (Contact Plugs). Wherein at least two contact plugs are located in the second interlayer dielectric layer 160 and are respectively electrically connected to two ends of the resistance layer 140a, while the remaining contact plugs are located in the second interlayer dielectric layer 160, the cap layer 130 and the buffer layer. 20a and are respectively electrically connected to the gate G of the MOS transistor M and the corresponding slot contact plug C1. The second interlayer dielectric layer 160 may be, for example, an oxide layer, and it may, for example, be obtained by stacking and covering multiple manufacturing processes; the contact plug C2 may, for example, be composed of metals such as tungsten or copper, but the present invention does not limit.

In detail, the second interlayer dielectric layer (not shown) can be fully covered on the flat buffer layer 20a, the resistance layer 140a and the capping film 150a; and then the second interlayer dielectric layer 160 is patterned to A plurality of trenches R2 are formed in the second interlayer dielectric layer 160 ; subsequently, metal (not shown) is filled in each trench R2 and planarized to form contact plugs C2 . At this time, the contact plug C2 in the second area B is electrically connected to the resistive layer 140 , and the contact plug C2 in the first area A is electrically connected to the socket contact plug C1 and the MOS transistor M.

In this way, this embodiment can also have the advantages of the first embodiment, for example, the trench R3 formed in the first region A and the second region B has the problem of under-etching or over-etching due to different depths; The contact plugs C2 in the first region A and the second region B are too large in length to cause the problem of insufficient hole filling or overfilling; even, when the second interlayer dielectric layer 160 is polished after the contact plugs C2 are formed, The shorter contact plugs C2 are completely removed due to the grinding of the second ILD layer 160 . Furthermore, since this embodiment is also a method of embedding the resistive layer, it can avoid the problem of over-etching the bottom layer of the resistive layer when etching the resistive layer for patterning. Furthermore, this embodiment has the advantage of improving photoresist adhesion and removal.

Moreover, the present invention can further selectively form at least one sacrificial gate in the first interlayer dielectric layer 120 under the resistance layer 140 or 140a; or, replace the bulk insulating structure 10 in the second region B with multiple The smaller insulating structure is used to prevent the first interlayer dielectric layer 120 or the insulating structure 10 from being recessed.

As shown in FIG. 11 , it shows a schematic cross-sectional view of a buried resistor with a sacrificial gate according to the first embodiment of the present invention, wherein the sacrificial gate DG in FIG. 11 is located in the first interlayer dielectric layer 120 and the electrical Directly below the contact plug C2 connected to the resistance layer 140 , and the sacrificial gates DG are all floating electrodes. Furthermore, a plurality of smaller insulating structures replace the bulk insulating structure 10 in the second region B, and each of the smaller insulating structures corresponds to the position of each sacrificial gate DG or contact plug C2.

However, in yet another embodiment, as shown in FIG. 12 , which shows a schematic cross-sectional view of a buried resistor with a sacrificial gate according to the second embodiment of the present invention, wherein the first interlayer dielectric layer 120 The sacrificial gate DG is located directly under the resistance layer 140a, but is misaligned with each contact plug C2. In this way, when the contact plug C2 extends to the first interlayer dielectric layer 120 due to over-etching, the problem of parasitic capacitance effect can be improved.

Of course, FIG. 11-FIG. 12 are only two embodiments of using the sacrificial gate DG, whether it is the sacrificial gate DG located directly below the contact plug C2 or misaligned with the contact plug C2, or extending through the base of the insulating structure 10 110a can be selectively applied to the first or second embodiment, as well as the resistive layer 140, 140a or block resistive layer 140', 140a' having a U-shaped cross-sectional structure.

In summary, the present invention proposes an embedded resistor, which first forms a groove in a material layer such as a cover layer or a buffer layer, and then forms a resistance layer or a block resistance layer with a U-shaped cross-sectional structure in the groove In order to form a buried resistor. In this way, the present invention can solve the problem of under-etching or over-etching caused by different depths of trenches formed in different regions (such as transistor regions and resistance regions) to form contact plugs; Due to the large difference in length of the contact plugs, the problem of insufficient hole filling or overfilling is caused; even, when the interlayer dielectric layer is polished after the formation of the contact plugs, the contact plugs with a shorter height may be damaged by the interlayer dielectric layer. Grinding is completely removed. Furthermore, since the present invention is a buried resistor, it can avoid the problem of over-etching the bottom layer of the resistor layer caused by etching the resistor layer for patterning.

Furthermore, if the buried resistor is formed in the buffer layer; in other words, the manufacturing process is to directly form a photoresist on the buffer layer to form a trench, and then form a resistor layer in the trench The method can make the photoresist have better adhesion because it is only formed on the buffer layer, and because the material of the buffer layer is generally an oxide layer, there will be no photoresist formed on the nitride layer (such as In layers of other materials, such as capping layers, reactions occur that make removal difficult.

In addition, the present invention can be further matched with forming a sacrificial gate in the first interlayer dielectric layer or making the base extend and penetrate in the bulk insulating structure, so as to prevent the first interlayer dielectric layer or the insulating structure from being recessed. Furthermore, the sacrificial gate formed in the first interlayer dielectric layer can be selectively dislocated from the contact plug to prevent the contact plug from being extended to the first interlayer dielectric layer due to over-etching to reduce the parasitic capacitance effect The problem.

Claims (22)

1. an embedded resistor, includes:

The first interlayer dielectric layer, is positioned in a substrate;

Cap rock, is positioned on this first interlayer dielectric layer, and wherein this cap rock has a groove;

Resistive layer, complies with and covers this groove, thereby have a U-shaped cross-section structure; And

Epiphragma, is arranged on this groove and this resistive layer.

2. embedded resistor as claimed in claim 1, also comprises:

MOS transistor is arranged in this first interlayer dielectric layer on this resistive layer side.

3. embedded resistor as claimed in claim 2, also comprises:

A plurality of slot contact plungers (Slot Contacts) are arranged in this first interlayer dielectric layer and are electrically connected to this MOS transistor.

4. embedded resistor as claimed in claim 1, wherein this resistive layer comprises titanium nitride layer.

5. embedded resistor as claimed in claim 1, wherein this epiphragma comprises a dielectric material.

6. embedded resistor as claimed in claim 1, also comprises:

Resilient coating, is arranged on this cap rock, but exposes this resistive layer and this epiphragma.

7. embedded resistor as claimed in claim 6, wherein this resilient coating extends in this groove and covers this groove but be positioned at this resistive layer below.

8. embedded resistor as claimed in claim 6, wherein an end face of this epiphragma flushes with an end face of this resilient coating on this cap rock.

9. embedded resistor as claimed in claim 1, wherein this U-shaped resistive layer has the side that at least one vertical component effect is parallel to this groove, and an end face of this epiphragma flushes with the top of this vertical component effect.

10. embedded resistor as claimed in claim 2, also comprises:

The second interlayer dielectric layer, is positioned on this cap rock, this resistive layer and this epiphragma.

11. embedded resistors as claimed in claim 10, also comprise:

A plurality of contact plungers (Contact Plugs), and those contact plungers of a part are arranged in this second interlayer dielectric layer and are electrically connected to respectively this resistive layer, and those contact plungers of another part are arranged in this second interlayer dielectric layer, this cap rock and this resilient coating and be electrically connected to respectively this MOS transistor.

12. embedded resistors as claimed in claim 11, also comprise:

At least one sacrifice grid, be arranged in this first interlayer dielectric layer and be electrically connected to this resistive layer those contact plungers under.

13. embedded resistors as claimed in claim 11, also comprise:

At least one sacrifice grid, be arranged in this first interlayer dielectric layer and this resistive layer under, but with those contact plungers dislocation (misalignment).

14. 1 kinds of embedded resistors, include:

The first interlayer dielectric layer, is positioned in a substrate;

Cap rock, is positioned on this first interlayer dielectric layer, and wherein this cap rock has a groove; And

Block resistive layer, is arranged in this groove.

15. embedded resistors as claimed in claim 14, also comprise:

MOS transistor is arranged in this first interlayer dielectric layer on this bulk resistive layer side.

16. embedded resistors as claimed in claim 14, also comprise:

Resilient coating, is arranged on this cap rock, but exposes this bulk resistive layer.

17. embedded resistors as claimed in claim 16, wherein this resilient coating extends in this groove and covers this groove but be positioned at this bulk resistive layer below.

18. embedded resistors as claimed in claim 16, wherein an end face of this bulk resistive layer flushes with an end face of this resilient coating on this cap rock.

19. embedded resistors as claimed in claim 14, also comprise:

The second interlayer dielectric layer, is positioned on this cap rock and this bulk resistive layer.

20. embedded resistors as claimed in claim 19, also comprise:

A plurality of contact plungers (Contact Plugs), and those contact plungers of a part are arranged in this second interlayer dielectric layer and are electrically connected to respectively this bulk resistive layer, and those contact plungers of another part are arranged in this second interlayer dielectric layer, this cap rock and this resilient coating and be electrically connected to respectively this MOS transistor.

21. embedded resistors as claimed in claim 20, also comprise:

At least one sacrifice grid, be arranged in this first interlayer dielectric layer and be electrically connected to this bulk resistive layer those contact plungers under.

22. embedded resistors as claimed in claim 20, also comprise:

At least one sacrifice grid, be arranged in this first interlayer dielectric layer and this bulk resistive layer under, but with those contact plungers dislocation (misalignment).