CN104051414B - Interconnection structure and method - Google Patents
Interconnection structure and method Download PDFInfo
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- CN104051414B CN104051414B CN201310241836.6A CN201310241836A CN104051414B CN 104051414 B CN104051414 B CN 104051414B CN 201310241836 A CN201310241836 A CN 201310241836A CN 104051414 B CN104051414 B CN 104051414B
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Abstract
The present invention relates to interconnection structure and method, there is provided and a kind of semiconductor devices includes the first semiconductor chip and the second semiconductor chip, wherein, the first semiconductor chip includes the first substrate and forms multiple first metal wires square on the first substrate；Second semiconductor chip is bonded on the first semiconductor chip, wherein, the second semiconductor chip includes the second substrate and multiple second metal wires formed above the second substrate.Semiconductor devices further comprises the conductive plug being connected between the first metal wire and the second metal wire, wherein, conductive plug includes the Part I formed above the first side of hard mask layer and the Part II formed above the second side of hard mask layer, wherein, Part I has the first width；Part II has the second width, and the second width is more than or equal to the first width.
Description
It is interim to quote
It is entitled this application claims the U.S. Provisional Patent Application the 61/777th, 870 submitted on March 12nd, 2013
" Interconnect Structure Method " rights and interests, entire contents are hereby expressly incorporated by reference.
Technical field
The application is related to semiconductor applications, more particularly, to interconnection structure and method.
Background technology
Due to various electronic devices (for example, transistor, diode, resistor, capacitor etc.) integration density it is continuous
Improve, semi-conductor industry experienced quick development.Largely, (e.g., will by constantly reducing the size of minimal parts
Semiconductor technology node is reduced into 20nm child nodes) more parts is integrated into given area, this integration density obtains
Improve.Requirement for miniaturization, nearest development have reached higher speed, bigger bandwidth and lower power consumption
And delay, but it is also required to develop the encapsulation technology of smaller and more creative semiconductor element.
Due to the further development of semiconductor technology, Stacket semiconductor device is generated, it turns into further reduction and partly led
Effective selection of the physical size of body device.In a Stacket semiconductor device, produced on different semiconductor crystal wafers
Active circuit (such as logic circuit), storage circuit and processor circuit.Two or more semiconductor crystal wafers can be installed
In top of each other, further to reduce the form factor of semiconductor devices (form factor).
Two semiconductor crystal wafers can be bonded together by suitable joining technique.Conventional joining technique includes direct
Engagement, chemism engagement, the active engagement of gas ions, anodic bonding, eutectic bonding, glass dust engage (glass frit), glued
Knot engagement, hot compression engagement, reaction engagement etc..As long as two semiconductor crystal wafers are bonded together, the two semiconductor crystal wafers it
Between interface can provide conductive path between Stacket semiconductor wafer.
The advantages of Stacket semiconductor device, is, more high density can be realized by using Stacket semiconductor device.In addition,
Stacket semiconductor device can realize smaller form factor, lower cost, the performance of enhancing and lower power consumption.
The content of the invention
To solve the above problems, the invention provides a kind of equipment, including：First semiconductor chip, including the first substrate
With a plurality of first metal wire for forming side on the first substrate；Second semiconductor chip, it is bonded on the first semiconductor chip, the
Two semiconductor chips include the second substrate and a plurality of second metal wire formed above the second substrate；And conductive plug, connection
Between the first metal wire and the second metal wire, conductive plug includes：Part I, formed hard mask layer first side it is upper
Side, Part I have the first width；And Part II, formed in the top of the second side of hard mask layer, Part II
The second width with more than or equal to the first width.
Wherein, hard mask layer is formed by the first metal wire.
Wherein, hard mask layer is formed by the redistribution lines of the first semiconductor chip.
Wherein, hard mask layer is formed by the contact of the first semiconductor chip.
Wherein, Part I is between the first metal wire and the second metal wire；And Part II is located at the first metal
Between the dorsal part of line and the first substrate.
Wherein, Part I is located between the contact and the second metal wire of the first semiconductor chip；And Part II
Between the contact of the first semiconductor chip and the dorsal part of the first substrate.
Wherein, Part I is located between the redistribution lines and the second metal wire of the first semiconductor chip；And second
Divide between the redistribution lines of the first semiconductor chip and the dorsal part of the first substrate.
In addition, a kind of device is additionally provided, including：First chip, including：First substrate；With multiple first interconnecting assemblies,
Form the top with the first substrate in the first metal intermetallic dielectric layer；Second chip, it is bonded on the first chip, the second chip bag
Include：Second substrate；With multiple second interconnecting assemblies, the top with the second substrate in the second metal intermetallic dielectric layer is formed；And
Conductive plug, the first substrate and the first metal intermetallic dielectric layer are formed through, and are formed as being situated between partially across between the second metal
Electric layer, wherein, conductive plug is connected between the first interconnecting assembly and the second interconnecting assembly.
The device further comprises：Hard mask layer, formed in the first chip, conductive plug is divided into first by hard mask layer
Point and Part II, wherein, Part I is adjacent to the first substrate；And the width of Part I is more than or equal to Part II
Width.
Wherein, hard mask layer is formed by two the first interconnecting assemblies.
Wherein, hard mask layer is formed by two contacts of the first chip.
Wherein, hard mask layer is formed by two redistribution lines of the first chip.
Wherein, conductive plug is made of copper.
In addition, a kind of method is additionally provided, including：First semiconductor crystal wafer is bonded on the second semiconductor crystal wafer, its
In, the first semiconductor crystal wafer includes the first substrate, the first metal intermetallic dielectric layer and the first interconnection structure, and the first interconnection structure is formed
In the first metal intermetallic dielectric layer and the first substrate top；And second semiconductor crystal wafer include the second substrate, the second metal
Between dielectric layer and the second interconnection structure, the second interconnection structure formed in the second metal intermetallic dielectric layer and the second substrate top；
The first substrate is patterned, to form the first opening in the first substrate；It is used as using etch process and by the first interconnection structure hard
Mask layer forms the second opening, wherein, the second opening be formed through first metal intermetallic dielectric layer and partially across
Second metal intermetallic dielectric layer；And plate conductive material in the first opening and the second opening.
This method further comprises：The depositing BARC layer on the dorsal part of the first semiconductor crystal wafer；And remove
A part for first substrate is to form the first opening.
This method further comprises：More metal lines of first semiconductor crystal wafer are opened as hard mask layer to form second
Mouthful.
This method further comprises：Multiple contacts of first semiconductor crystal wafer are opened as hard mask layer to form second
Mouthful.
This method further comprises：The a plurality of redistribution lines of first semiconductor crystal wafer are used as hard mask layer to form second
Opening.
Wherein, conductive material is copper.
This method further comprises：After the step of plating conductive material in the first opening and the second opening, by chemical machine
Tool glossing is applied to the dorsal part of the first semiconductor crystal wafer；And by chemical vapor deposition process by dielectric layer deposition
Above the dorsal part of semiconductor wafer.
Brief description of the drawings
In order to which embodiment and its advantage is more fully understood, now with reference to the description that accompanying drawing is carried out as reference, wherein：
Fig. 1 shows the section of the Stacket semiconductor device before joint technology of different embodiment according to the subject invention
Figure；
Fig. 2 shows semiconductor devices shown in Fig. 1 of different embodiment according to the subject invention in the first semiconductor die
Round top form bottom antireflective coating (BARC) and will be patterned into technique applied to the first semiconductor crystal wafer substrate it
Sectional view afterwards；
Fig. 3 shows semiconductor devices shown in Fig. 2 of different embodiment according to the subject invention in semiconductor devices
Sectional view after disposed thereon dielectric layer；
Fig. 4 shows semiconductor devices shown in Fig. 3 of different embodiment according to the subject invention in semiconductor devices
The sectional view that top is formed after mask layer；
Fig. 5 shows semiconductor devices shown in Fig. 4 of different embodiment according to the subject invention in etch process application
Sectional view after semiconductor devices；
Fig. 6 shows that the semiconductor devices shown in Fig. 5 of different embodiment according to the subject invention is removing remaining photoetching
Sectional view after glue-line；
Fig. 7 shows that the semiconductor devices shown in Fig. 6 of different embodiment according to the subject invention is inserted in the opening and led
Sectional view after electric material；
Fig. 8 shows that the semiconductor devices shown in Fig. 7 of different embodiment according to the subject invention is thrown by chemical machinery
Light (CMP) technique is applied to the sectional view after the top surface of semiconductor devices；
Fig. 9 shows semiconductor devices shown in Fig. 8 of different embodiment according to the subject invention on the semiconductor device
The sectional view formed after dielectric layer；
Figure 10 shows the sectional view of another Stacket semiconductor device of different embodiment according to the subject invention；
Figure 11 shows the sectional view of another Stacket semiconductor device of different embodiment according to the subject invention；
Figure 12 shows that the backside illumination type image for including stacking crystal circle structure of different embodiment according to the subject invention passes
The sectional view of sensor；
Figure 13 shows the top view of the hard mask of different embodiment according to the subject invention；And
Figure 14 shows another top view of the hard mask of different embodiment according to the subject invention.
Unless otherwise stated, the respective digital and symbol in different figures usually represent corresponding part.The figure of drafting
It is served only for clearly demonstrating the related fields of embodiment, is not necessarily to scale.
Embodiment
Below, the manufacture and use of the preferred embodiments of the present invention is discussed in detail.It should be appreciated, however, that the present invention provides
Many applicable concepts that can be realized in various specific environments.The specific embodiment discussed illustrate only manufacture
With the concrete mode using the present invention, rather than limitation the scope of the present invention.
Preferred embodiment in specific environment describes the present invention, forms the mutual link for Stacket semiconductor device
The method of structure.However, it is can also be applied to different semiconductor devices.Hereinafter, will be described in more detail referring to the accompanying drawings
Different embodiments.
Fig. 1 shows the section of the Stacket semiconductor device before joint technology of different embodiment according to the subject invention
Figure.First semiconductor crystal wafer 110 and the second semiconductor crystal wafer 210 include Semiconductor substrate (e.g., the first substrate 102 and second
Substrate 202) and form square on a semiconductor substrate multiple interconnection structures (e.g., metal wire 106, metal wire 108, metal wire 206
With metal wire 208).Here, the semiconductor crystal circle structure before joint technology that the first semiconductor crystal wafer 110 use is elaborated
Example.
As shown in figure 1, the first semiconductor crystal wafer 110 may include the first substrate 102 and be formed above the first substrate 102
Multiple metal intermetallic dielectric layers 104.In addition, more metal lines are formed in metal intermetallic dielectric layer 104, such as metal wire 106 and metal
Line 108.
First substrate 102 can be formed by silicon, but also can be by other III main groups, IV main group, and/or V main group
Element is formed, such as silicon, germanium, gallium, arsenic and combinations thereof.First substrate 102 can also be silicon-on-insulator (SOI) shape
Formula.SOI substrate may include the semiconductor material layer to be formed above insulator layer (e.g., oxygen buried layer and/or other layers) (e.g., silicon,
Germanium and/or other materials), it is formed in a silicon substrate.In addition, other workable substrates include MULTILAYER SUBSTRATE, gradient substrate,
Hybrid orientation substrate, its any combination etc..
First substrate 102 can further comprise different circuit (not shown).Forming circuit on the first substrate 102 can be with
Apply to any kind of circuit of special applications.According to some embodiments, circuit may include different n-type metal oxides
Semiconductor (NMOS) and/or p-type metal oxide semiconductor (PMOS) device, as transistor, capacitor, resistor, diode,
Photodiode, fuse etc..
Circuit can be interconnected to perform one or more functions.Function may include storage organization, processing structure, sensing
Device, amplifier, power distribution, input/output circuitry etc..One of ordinary skill in the art should be understood that the reality of above-mentioned offer
Purpose of the example only to show, it is no intended to which different embodiments are limited in any application-specific.
Metal intermetallic dielectric layer 104 is formed in the top of the first substrate 102.As shown in figure 1, metal intermetallic dielectric layer 104 can wrap
More metal lines are included, such as metal wire 106 and metal wire 108.
E.g., metal wire 106 and metal wire 108 (can have by any suitable formation process and etch, inlay, dual
The photoetching process inlayed etc.) make, and suitable conductive material (such as copper, aluminium, aluminium alloy, copper alloy) shape can be used
Into.
As shown in figure 1, the first semiconductor crystal wafer 110 will be stacked on the top of the second semiconductor crystal wafer 210.In some implementations
In example, multiple bond pads are respectively formed in the first semiconductor crystal wafer 110 and the second semiconductor crystal wafer 210.In addition, positioned at the
The bond pad of two semiconductor crystal wafers 210 and the corresponding bond pad at the first semiconductor crystal wafer 110 are right Face to face
It is accurate.The first semiconductor crystal wafer 110 and the second semiconductor crystal wafer 210 are bonded on by suitable joint technology (such as directly engagement)
Together.
According to some embodiments, in direct joint technology, by the engagement (engagement of such as copper and copper) of metal and metal,
Dielectric with it is dielectric engage the engagement of oxide (such as oxide with), metal engages (such as oxide and copper with dielectric
Engagement), its any combinations etc., the connection between the first semiconductor crystal wafer 110 and the second semiconductor crystal wafer 210 can be achieved.
Fig. 2 shows semiconductor devices shown in Fig. 1 of different embodiments of the invention in the first semiconductor crystal wafer
After top forms bottom antireflective coating (BARC) and will be patterned into technique applied to the substrate of the first semiconductor crystal wafer
Sectional view.BARC layer 112 forms the dorsal part in the first substrate 102.In entire description, the first lining of neighbouring BARC layer 112
The side at bottom 102 is referred to as the dorsal part of the first substrate 102.
BARC layer 112 can be formed by nitride material, organic material, oxide material etc..Suitable technology can be used (such as
Chemical vapor deposition (CVD) etc.) form BARC layer 112.
Using suitable deposition and photoetching process, patterned mask can be formed in the top of BARC layer 112, as photoresist is covered
Film etc..Suitable etch process, such as reactive ion etching (RIE) or other dry-etchings, anisotropic wet etching or any
Other suitable anisotropic etchings or Patternized technique can be applied to the first substrate 102 of the first semiconductor crystal wafer 110.Cause
This, forms multiple openings 114 and opening 116 in the first substrate 102.
Fig. 3 shows semiconductor devices shown in Fig. 2 of different embodiment according to the subject invention in semiconductor devices
Sectional view after disposed thereon dielectric layer.As shown in figure 3, dielectric layer 302 formed in the bottom of opening 114 and opening 116 and
The top of side wall.In addition, dielectric layer 302 is formed in the top of BARC layer 112.
The different dielectric material commonly used in IC manufacturing can be used to form dielectric layer 302.For example, can by silica,
Silicon nitride or the glassy layer of doping (such as Pyrex) form dielectric layer 302.Alternatively, dielectric layer can be silicon nitride layer,
Silicon oxynitride layer, aramid layer, low dielectric constant insulator or other.In addition, the combination of above-mentioned dielectric material can also be used for shape
Into dielectric layer 302.According to some embodiments, dielectric layer 302 can be formed using suitable technology (such as sputter, aoxidize, CVD).
Fig. 4 shows semiconductor devices shown in Fig. 3 of different embodiment according to the subject invention in semiconductor devices
The sectional view that top is formed after mask layer.Patterned mask 402 forms the side in opening 114 and opening 116 (as shown in Figure 3)
The top of wall.As shown in figure 4, after patterned mask 402 is formed along the side wall of opening 114 and opening 116, two are formed
New opening 404 and opening 406.
Patterned mask 402 can be photoresist layer.Using suitable deposition and photoetching technique, on the top of semiconductor devices
Patterned mask 402 is formed on face.
Fig. 5 shows semiconductor devices shown in Fig. 4 of different embodiment according to the subject invention in etch process application
Sectional view after semiconductor devices.Suitable etch process can be carried out, as dry-etching, anisotropic wet etching or
Other suitable anisotropic etchings or Patternized technique, to form opening 504 and opening 506.Opening 504 and opening 506 are divided
Not Wei opening 404 and opening 406 extension.Specifically, opening 504 and opening 506 extend through metal intermetallic dielectric layer 104 and gold
The joint interface of dielectric layer 204 and two stacking wafers between category.As shown in figure 5, after opening 504 and opening 506 are formed, expose
Metal wire 106, metal wire 108, metal wire 206 and metal wire 208.
It should be understood that metal wire 106 and metal wire 108 are formed by suitable metal material (such as copper), its etch-rate (selection
Than selectivity) it is different from the first substrate 102 and the etch-rate of metal intermetallic dielectric layer.Similarly, metal wire 106 and gold
Category line 108 can be used as the hard mask layer of the etch process of metal intermetallic dielectric layer 104 and metal intermetallic dielectric layer 204.When only etch gold
During a part for category line 106 and metal wire 108, selection etch process can be used rapidly to etch metal intermetallic dielectric layer 104 and gold
Dielectric layer 204 between category.As shown in figure 5, partly etch away the exposed division of hard mask layer (e.g., metal wire 106 and metal wire 108)
Point, and then groove is formed, such as groove 502.According to different applications and design requirement, the depth of groove 502 is variable.
Fig. 6 shows that the semiconductor devices shown in Fig. 5 of different embodiment according to the subject invention is removing remaining photoetching
Sectional view after glue-line.By using suitable photoresist lift off technology, such as chemical solvent cleaning, plasma ashing, do
Formula stripping etc., removes the remaining photoresist layer shown in Fig. 5.Photoresist lift off technology is known, therefore, in order to prevent going to live in the household of one's in-laws on getting married
State, no longer provide and be discussed in detail herein.
Fig. 7 shows that the semiconductor devices shown in Fig. 6 of different embodiment according to the subject invention is inserted in the opening and led
Sectional view after electric material.In certain embodiments, before electroplating technology, barrier layer and crystal seed layer can be deposited, passes through gesture
Barrier layer and crystal seed layer, conductive material can be filled into opening.
Barrier layer 710 can be deposited in bottom and the side wall of opening (opening 404 in such as Fig. 6).Barrier layer 710 can be by
Titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof etc. formed.In certain embodiments, barrier layer 710 can have uniform thickness.
In an alternate embodiment of the invention, barrier layer 710 can have uneven thickness.Use suitable manufacturing process, such as ald
(ALD), plasma enhanced CVD (PECVD), plasma enhancing PVD (PEPVD) etc., can form barrier layer
710。
In addition, crystal seed layer (not shown) can be deposited on the top of barrier layer 710.Crystal seed layer can by copper, nickel, gold, its is any
Combination etc. is formed.By suitable deposition technique, such as PVD, CVD, crystal seed layer can be formed.
In addition, the material alloying crystal seed layer for the adhesion characteristic for improving crystal seed layer can be used so that crystal seed layer may be used as gluing
Close layer.For example, material (such as manganese or aluminium) alloying crystal seed layer can be used, so it is movable between crystal seed layer and barrier layer 710
Interface and the bonding force between this two layers can be strengthened.During crystal seed layer is formed, alloy material can be introduced.Alloy material can
About 10% including no more than crystal seed layer.
Once barrier layer 710 and seed layer deposition are in the opening, just conductive material is filled into opening, and then is formed and led
Electricity plug 702 and conductive plug 704, wherein, conductive material includes tungsten, titanium, aluminium, copper, its any combinations etc..In certain embodiments,
Conductive material can be filled into opening by electroplating technology.
Fig. 8 shows that the semiconductor devices shown in Fig. 7 of different embodiment according to the subject invention is ground by chemical machinery
Grind the sectional view that (CMP) technique is applied to after the top surface of semiconductor devices.Flatening process can be carried out, such as CMP, deep etching step
Suddenly (etch back step) etc., to planarize the top surface of semiconductor devices.As shown in figure 8, so as to remove the one of conductive material
Part.As shown in figure 8, after carrying out CMP on the semiconductor device, two conductive plugs can be formed in the semiconductor device
802 and conductive plug 804.
As shown in figure 8, each conductive plug (e.g., conductive plug 802 and conductive plug 804) may include three parts.Part I
It is from metal wire 206 to the hard mask layer formed by metal wire 106 and 108.As shown in figure 8, Part I has width W1.
Part II is the front side from hard mask layer to the first substrate 102.As shown in figure 8, Part II has width W2.Part III
It is the dorsal part from the front side of the first substrate 102 to the first substrate 102.As shown in figure 8, Part III has width W3.At some
In embodiment, W2 is more than or equal to W1.W3 is more than W2.
Fig. 9 shows that the semiconductor devices shown in Fig. 8 of different embodiments of the invention is formed on the semiconductor device
Sectional view after dielectric layer.Dielectric layer 902 may include conventional dielectric material, as silicon nitride, silicon oxynitride, silicon oxide carbide,
Carborundum, combinations thereof and their multilayer., can be in semiconductor devices by suitable deposition technique, such as sputtering, CVD
Disposed thereon dielectric layer 902.
Conductive plug (such as conductive plug 802) includes three parts as shown in Figure 8 described above.In entire description,
Moieties option from hard mask layer (e.g., metal wire 106) to metal wire 206 can be referred to as three-dimensional structure 904.
One advantage of the stacking wafer with the conductive plug 802 shown in Fig. 9 and conductive plug 804 is, by single
Conductive plug (e.g., conductive plug 802), the active circuit of two semiconductor crystal wafers is connected with each other.Such single conductive plug
Help further to reduce form factor.In addition, compared with the Stacket semiconductor device connected by multiple conductive plugs, it is connected to
The single conductive plug between two semiconductor crystal wafers shown in Fig. 9 helps to reduce power consumption and prevents parasitic disturbances.
It should be noted that when Fig. 9 shows two semiconductor die bowlders being stacked, those skilled in the art should
Know, the Stacket semiconductor device shown in Fig. 9 is only an example.There may be many replacements, change and modifications.For example, heap
Folded semiconductor devices can accommodate more than two semiconductor crystal wafers.
Figure 10 shows the sectional view of another Stacket semiconductor device of different embodiment according to the subject invention.Except logical
Cross beyond the hard mask layer of the neighbouring interface setting between first substrate 102 and metal intermetallic dielectric layer 104 of contact formation, heap
Stacket semiconductor device 100 shown in folded semiconductor devices 1000 and Fig. 9 is similar.
Contact may be formed in interlayer dielectric layer (not shown).Interlayer dielectric layer may include such as boron-phosphorosilicate glass (BPSG)
Material, but any suitable dielectric is used equally for this layer.Using such as PECVD technique, interlayer dielectric layer can be formed, but
It is that can also alternatively use other techniques.
Contact 1006 and contact 1008 can be formed by interlayer dielectric layer using suitable photoetching and etching technique.It is logical
Often, these photoetching techniques include deposition Other substrate materials, its by mask, expose and develop, so as to expose interlayer to be removed
The part of dielectric layer.Remaining Other substrate materials protect subsurface material from the influence of ensuing processing step (as etched).
Contact 1006 and contact 1008 may include potential barrier/adhesive layer (not shown), to prevent from spreading and for contact
1006 and contact 1008 more preferable bonding force is provided.In certain embodiments, contact 1006 and contact 1008 can be by appointing
What suitable conductive material (e.g., high conductivity and low resistance metal, metal element, transition metal etc.) is formed.According to one embodiment, by tungsten
Contact 1006 and contact 1008 are formed, but can alternatively use other materials, such as copper, aluminium.In one embodiment
In, contact 1006 and contact 1008 are formed by tungsten, Deposit contact part 1006 and can be connect by CVD technology well known in the art
Contact element 1008, but can alternatively use any forming method.
As shown in figure 11, conductive plug (e.g., conductive plug 1002 and conductive plug 1004) includes three parts.From hard mask layer
(e.g., contact 1006) is alternatively properly termed as three-dimensional structure 1003 to the part of metal wire 206 in entire description.
Figure 11 shows the sectional view of another Stacket semiconductor device of different embodiment according to the subject invention.Except logical
Cross beyond the hard mask of etching being disposed adjacent with the interface of two semiconductor crystal wafers of redistributing layer formation, Stacket semiconductor device
1100 is similar to the Stacket semiconductor device 100 shown in Fig. 9.
Redistribution metal wire 1106 and redistribution metal wire 1108 can be single material layer or sandwich construction, and can be by
Metal is made, such as titanium, titanium nitride, aluminium, tantalum, copper and combinations thereof.By any appropriate method well known in the art (such as
Physical vapour deposition (PVD) (PVD), sputtering, CVD, plating etc.) redistribution metal wire 1106 and redistribution metal wire 1108 can be manufactured.
Conductive plug (such as conductive plug 1102 and conductive plug 1104) includes three parts.(metal e.g., is redistributed from hard mask layer
Line 1106 and redistribution metal wire 1108) to the part of metal wire 206 three-dimensional knot is alternatively properly termed as in entire description
Structure 1103.
It should be noted that by suitable metal-dielectric joining technique, (such as copper-silicon oxynitride (Cu-SiON) engages work
Skill) the first semiconductor crystal wafer 110 can be bonded on the second semiconductor crystal wafer 210.
It should be further noted that when Fig. 9, Figure 10, Figure 11 are shown respectively by the hard of metal wire, contact and redistribution lines formation
During mask layer, it will be appreciated by those skilled in the art that the hard mask layer shown in Fig. 9-Figure 11 is only example.There may be perhaps
Replace more, change and modifications.For example, the hard mask of the formation such as multiple isolated areas, multi-crystal silicon area, any combination of them can be passed through
Layer.
Figure 12 shows that the backside illumination type image for including stacking crystal circle structure of different embodiment according to the subject invention passes
The sectional view of sensor.Backside illumination type imaging sensor 1200 includes two semiconductor crystal wafers, i.e. sensor wafer 1201 and specially
With integrated circuit (ASIC) wafer 1203.As shown in figure 12, sensor wafer 1201 is stacked on ASIC1203 top.At some
In embodiment, sensor wafer 1201 and ASIC wafer 1203 are connected to each other by suitable three-dimensional structure, and three-dimensional structure includes
Three-dimensional structure 1003 shown in three-dimensional structure 904 as shown in Figure 9, Figure 10, the three-dimensional structure 1103 shown in Figure 11 and they
Combination.
ASIC wafer 1203 may include multiple logic circuits, such as logic circuit 1206 and logic circuit 1208.In some realities
Apply in example, logic circuit can be analog-digital converter.But logic circuit can be other functional circuitries, these features
Circuit can be used in backside illumination type imaging sensor.For example, logic circuit 1206 and logic circuit 1208 can be at data
Manage circuit, storage circuit, biasing circuit, reference circuit, any combination of them etc..
ASIC wafer 1203 can further comprise multiple interconnection layers and multiple metal wires 1220, metal in embedded interconnection layer
Line 1222, metal wire 1224 and metal wire 1226.Metal wire 1220, metal wire 1222, metal wire 1224 and metal wire 1226 can
As interconnection structure.As indicated by the arrows in fig, metal wire 1220, metal wire 1222, metal wire 1224 and metal wire 1226
Provide the signal path between logic circuit 1206 and logic circuit 1208 and sensor wafer 1201.
By any suitable formation process (e.g., have etch, inlay, the photoetching process of dual-inlaid etc.) and it can make
Metal wire 1220, metal wire 1222, metal wire 1224 are formed with suitable conductive material (such as copper, aluminium, aluminium alloy, copper alloy)
With metal wire 1226.
Sensor wafer 1201 is manufactured by CMOS technology technology well known in the art.Specifically, sensor wafer 1201
The epitaxial layer being included in above silicon substrate.According to the manufacturing process of backside illumination type imaging sensor, in dorsal part reduction process
Silicon substrate is removed, until exposing epitaxial layer.A part for epitaxial layer can be retained.P-type light active area and n-type light active area (do not divide
Do not show) formed in remaining epitaxial layer.
Light active area (such as p-type light active area and n-type light active area) can form PN junction, and the PN junction is used as photodiode.
As shown in figure 12, imaging sensor 1110 may include multiple photodiodes.
Sensor wafer 1201 may include transistor (not shown).Specifically, transistor can produce and influence optoelectronic active
The intensity of the light in area or the relevant signal of brightness.According to one embodiment, transistor can be transfering transistor.But crystal
Pipe can be an example of the feature transistor for the polymorphic type that can be used in backside illumination type imaging sensor.It is for example, brilliant
Body pipe may include other transistors being located in backside illumination type imaging sensor, such as reset transistor, source follower crystal
Pipe or selection transistor.The scope of the present embodiment is included in available for all appropriate transistors in imaging sensor and configuration
It is interior.
Sensor wafer 1201 may include multiple interconnection layers and the metal wire being embedded in interconnection layer.Metal wire 1120, gold
The signal that category line 1122, metal wire 1124 and metal wire 1126 can be provided between sensor wafer 1201 and ASIC wafer 1203 leads to
Road.Specifically, as shown by the arrows in figure 12, external signal can enter backside illumination type imaging sensor by aluminum bronze pad 1112
In 1200, metal line (such as metal wire 1120) is then reached by interconnection structure (such as by through hole (not shown)).Outside letter
Number it can further pass through three-dimensional structure 1210.Three-dimensional structure 1210 can be three-dimensional structure 904 shown in Fig. 9, shown in Figure 10
Three-dimensional structure 1103 and/or any combination of them shown in three-dimensional structure 1003, Figure 11.
After external signal passes through three-dimensional structure 1210, external signal can pass through the metal line of ASIC wafer 1203
(such as metal wire 1220) reaches logic circuit 1206.
When signal leaves logic circuit 1206, metal line (e.g., metal wire that the signal passes through ASIC wafer 1203
1222), the conductive path that the metal line of three-dimensional structure 1210 and sensor wafer 1201 is formed (such as metal wire 1122) arrives
Up to imaging sensor 1110.
After imaging sensor 1110 produces signal, the signal is (e.g., golden by the metal line of sensor wafer 1201
Category line 1124), the path quilt that is formed of the metal line (e.g., metal wire 1224) of three-dimensional structure 1210 and ASIC wafer 1203
It is sent to logic circuit 1208.In addition, the signal passes through the metal line (e.g., metal wire 1226) of ASIC wafer 1203, three-dimensional
The path that structure 1210, the metal line (e.g., metal wire 1126) of sensor wafer 1201 and aluminum bronze pad 1114 are formed from
Logic circuit 1208 is sent to the outside of backside illumination type imaging sensor 1200.
Logic circuit 1206 and logic circuit 1208 may be coupled to aluminum bronze pad 1112 and aluminum bronze weldering 1114.Such as Figure 12 institutes
Show, aluminum bronze pad 1112 and aluminum bronze pad 1114 may be formed at the dorsal part of sensor wafer 1201.
It should be noted that the position of the aluminum bronze pad 1112 and aluminum bronze pad 1114 shown in Figure 12 is only an example.Ability
The technical staff in domain should be understood that many can replace, modifications and variations.For example, aluminum bronze pad 1112 and aluminum bronze pad 1114
It may be formed on the disengaged side of ASIC wafer 1203.By forming aluminum bronze pad on the disengaged side of ASIC wafer 1203
1112 and aluminum bronze pad 1114, the form factor of backside illumination type imaging sensor can be reduced.
The advantage that input/output terminal is formed on the disengaged side of ASIC wafer 1203 is that it is possible to improve the back of the body
The density and quantum efficiency of side illumination type imaging sensor 1200.
Figure 13 shows the top view of the hard mask of different embodiment according to the subject invention.Referring to Fig. 9, Figure 10, Figure 11, lead to
Hard mask layer can be formed respectively by crossing metal wire, contact and redistribution lines.When sectional view 1301 shows that hard mask layer includes two
Partly when (such as metal wire 106 and metal wire 108), the two parts may be from the continuous circular shape area shown in top view 1302.
The top view 1302 of hard mask layer shows hard mask layer in a ring.The interior diameter of annular hard mask layer is denoted as W1.
It should be noted that other suitable shapes can replace the inner ring of annular hard mask layer, as shown in top view 1304 just
It is square.In the case of the scope and spirit without departing substantially from different embodiments of the invention, the top view of hard mask layer may include it
His shape, but be not limited only to these shapes, e.g., ellipse, triangle, polygon and/or other.
Figure 14 shows another top view of the hard mask of different embodiment according to the subject invention.Except with opening
Square replace annular outside, Figure 14 top view is similar with the top view shown in Figure 13.Top view 1402 shows have
The square of square openings.Top view 1404 shows the square with circular open.
According to one embodiment, a kind of equipment includes the first semiconductor chip and the second semiconductor chip, wherein, the first half
Conductor chip includes the first substrate and forms multiple first metal wires square on the first substrate；Second semiconductor chip is bonded on
On first semiconductor chip, wherein, the second semiconductor chip includes the second substrate and formed above the second substrate multiple the
Two metal wires.
Semiconductor devices further comprises the conductive plug being connected between the first metal wire and the second metal wire, wherein, lead
Electricity plug includes the Part I formed above the first side of hard mask layer and formed above the second side of hard mask layer
Part II, wherein, Part I has the first width；Part II has the second width, and the second width is more than or waited
In the first width.
According to one embodiment, a kind of device includes the first chip, the second chip and conductive plug.First chip includes first
Multiple first interconnecting assemblies of substrate and formation in the first metal intermetallic dielectric layer and above the first substrate.Second chip is bonded on
On first chip.Second chip includes the second substrate and formed multiple in the second metal intermetallic dielectric layer and above the second substrate
Second interconnecting assembly.The conductive plug of formation is through the first substrate and the first metal intermetallic dielectric layer and partially across the second metal
Between dielectric layer.Conductive plug is connected between the first interconnecting assembly and the second interconnecting assembly.
According to one embodiment, a kind of method includes the first semiconductor crystal wafer being bonded on the second semiconductor crystal wafer, its
In, the first semiconductor crystal wafer includes the first substrate, the first metal intermetallic dielectric layer and the first interconnection structure, and the first interconnection structure is formed
In the first metal intermetallic dielectric layer and the first substrate top；Second semiconductor crystal wafer includes being situated between the second substrate, the second metal
Electric layer and the second interconnection structure, the second interconnection structure form the top with the second substrate in the second metal intermetallic dielectric layer.
This method further comprises：The first substrate is patterned to form the first opening through the first substrate；Use etching
Technique and using the first interconnection structure as hard mask layer to form the second opening, wherein, the second opening of formation is through the
One metal intermetallic dielectric layer and partially across the second metal intermetallic dielectric layer；And the plated conductive in the first opening and the second opening
Material.
Although the invention has been described in detail and its advantage, it is to be understood that can be will without departing substantially from appended right
In the case of the spirit and scope of the present invention for asking restriction, a variety of changes are made, replaces and changes.
Moreover, scope of the present application is not limited in technique described in this specification, machine, manufacture, material component, dress
Put, the specific embodiment of method and steps.It is existing or modern as it will be recognized by one of ordinary skill in the art that by the present invention
Develop afterwards be used to perform with according to the essentially identical function of the corresponding embodiment of the present invention or the basic phase of acquisition
Isostructural technique, machine, manufacture, material component, device, method or the step present invention can be used.Therefore, appended right
It is required that it should be included in the range of such technique, machine, manufacture, material component, device, method or step.
Claims (19)
1. a kind of semiconductor equipment, including：
First semiconductor chip, including the first substrate and form hard mask layer above first substrate；
Second semiconductor chip, it is bonded on first semiconductor chip, second semiconductor chip includes the second substrate
With a plurality of second metal wire of the formation below second substrate；And
Conductive plug, it is connected between the hard mask layer and second metal wire, the conductive plug includes：
Part I, formed has the first width in the lower section of the first side of the hard mask layer, the Part I；
Part II, formed in the top of the second side of the hard mask layer, the Part II has wide more than described first
Second width of degree, the second side of the hard mask layer are relative with the first side of the hard mask layer；And
Part III, formed in the substrate, between the dorsal part of the front side of the substrate and the substrate, the described 3rd
Part has the 3rd width more than second width.
2. semiconductor equipment according to claim 1, wherein,
The hard mask layer is formed by the first metal wire.
3. semiconductor equipment according to claim 1, wherein,
The hard mask layer is formed by the redistribution lines of first semiconductor chip.
4. semiconductor equipment according to claim 1, wherein,
The hard mask layer is formed by the contact of first semiconductor chip.
5. semiconductor equipment according to claim 2, wherein,
The Part I is between first metal wire and second metal wire；And
The Part II is between first metal wire and the dorsal part of first substrate.
6. semiconductor equipment according to claim 4, wherein,
The Part I is located between contact and second metal wire of first semiconductor chip；And
The Part II is between the contact of first semiconductor chip and the dorsal part of first substrate.
7. semiconductor equipment according to claim 3, wherein,
The Part I is located between redistribution lines and second metal wire of first semiconductor chip；And
The Part II is between the redistribution lines of first semiconductor chip and the dorsal part of first substrate.
8. a kind of semiconductor device, including：
First chip, including：
First substrate；With
Hard mask layer, form the top with first substrate in the first metal intermetallic dielectric layer；
Second chip, it is bonded on first chip, second chip includes：
Second substrate；With
Multiple second interconnecting assemblies, form the lower section with second substrate in the second metal intermetallic dielectric layer；And
Conductive plug, be formed through first substrate and first metal intermetallic dielectric layer, and be formed as partially across
Second metal intermetallic dielectric layer, wherein, the conductive plug is connected between the hard mask layer and second interconnecting assembly；
Wherein, the hard mask layer is formed in first chip, and the conductive plug is divided into first by the hard mask layer
Point, Part II and Part III, wherein,
The Part I is adjacent to first substrate and is formed in the top of the first side of the hard mask layer；And
The Part II is formed in the lower section of the second side of the hard mask layer, the second side of the hard mask layer with it is described hard
First side of mask layer is relative, and the width of the Part I is more than the width of the Part II；And
The Part III is formed in the substrate, described between the dorsal part of the front side of the substrate and the substrate
The width of Part III is more than the width of the Part I.
9. semiconductor device according to claim 8, wherein,
The hard mask layer is formed by two the first interconnecting assemblies.
10. semiconductor device according to claim 8, wherein,
The hard mask layer is formed by two contacts of first chip.
11. semiconductor device according to claim 8, wherein,
The hard mask layer is formed by two redistribution lines of first chip.
12. semiconductor device according to claim 8, wherein,
The conductive plug is made of copper.
13. a kind of method for manufacturing semiconductor structure, including：
First semiconductor crystal wafer is bonded on the second semiconductor crystal wafer, wherein,
First semiconductor crystal wafer includes the first substrate, the first metal intermetallic dielectric layer and the first interconnection structure, and described first is mutual
Link the top being configured in first metal intermetallic dielectric layer with first substrate；And
Second semiconductor crystal wafer includes the second substrate, the second metal intermetallic dielectric layer and the second interconnection structure, and described second is mutual
Link the lower section being configured in second metal intermetallic dielectric layer with second substrate；
First substrate is patterned, to form the first opening in first substrate；
It is used as hard mask layer using etch process and by first interconnection structure to form the second opening, wherein, described second
Opening is formed through first metal intermetallic dielectric layer and partially across second metal intermetallic dielectric layer；And
Conductive material is plated to form conductive plug in the described first opening and the described second opening, wherein, the conductive plug includes：
Part I, formed has the first width in the lower section of the first side of hard mask layer, the Part I；
Part II, formed in the top of the second side of the hard mask layer, the Part II has wide more than described first
Second width of degree, the second side of the hard mask layer are relative with the first side of the hard mask layer；And
Part III, formed in the substrate, between the dorsal part of the front side of the substrate and the substrate, the described 3rd
Part has the 3rd width more than second width.
14. according to the method for claim 13, further comprise：
The depositing BARC layer on the dorsal part of first semiconductor crystal wafer；And
The part for removing first substrate is open with forming described first.
15. according to the method for claim 13, further comprise：
More metal lines of first semiconductor crystal wafer are used as the hard mask layer to form second opening.
16. according to the method for claim 13, further comprise：
Multiple contacts of first semiconductor crystal wafer are used as the hard mask layer to form second opening.
17. according to the method for claim 13, further comprise：
The a plurality of redistribution lines of first semiconductor crystal wafer are used as the hard mask layer to form second opening.
18. the method according to claim 11, wherein,
The conductive material is copper.
19. according to the method for claim 13, further comprise：
After the step of plating the conductive material in the described first opening and the described second opening, by CMP process
Dorsal part applied to first semiconductor crystal wafer；And
By chemical vapor deposition process by dielectric layer deposition above the dorsal part of first semiconductor crystal wafer.
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| US13/839,860 US9041206B2 (en) | 2013-03-12 | 2013-03-15 | Interconnect structure and method |
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| US20150187701A1 (en) * | 2013-03-12 | 2015-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Devices and Methods of Manufacture Thereof |
| US10056353B2 (en) | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
| US9412719B2 (en) | 2013-12-19 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
| US9455158B2 (en) | 2014-05-30 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect devices and methods of forming same |
| US9449914B2 (en) | 2014-07-17 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuits with redistribution lines |
| CN104377164A (en) * | 2014-09-28 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Through silicon var wafer interconnection process |
| CN104733437B (en) * | 2015-03-31 | 2019-02-19 | 武汉新芯集成电路制造有限公司 | The method of wafer three-dimensional integration |
| CN104766828B (en) * | 2015-03-31 | 2017-08-04 | 武汉新芯集成电路制造有限公司 | The method of wafer three-dimensional integration |
| TWI604565B (en) * | 2015-08-04 | 2017-11-01 | 精材科技股份有限公司 | Sensing chip package and manufacturing method thereof |
| CN105826214B (en) * | 2016-05-30 | 2019-04-30 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of bonded wafer structure |
| CN108063121A (en) * | 2016-11-08 | 2018-05-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic device |
| CN108010930A (en) * | 2017-12-08 | 2018-05-08 | 德淮半导体有限公司 | Imaging sensor and the method for forming imaging sensor |
| CN109037197B (en) * | 2018-08-03 | 2020-07-10 | 德淮半导体有限公司 | Semiconductor device and method of manufacturing the same |
| CN109148361B (en) * | 2018-08-28 | 2019-08-23 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| US20200211968A1 (en) * | 2018-12-27 | 2020-07-02 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| US11217547B2 (en) * | 2019-09-03 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure with reduced step height and increased electrical isolation |
| KR20210088810A (en) * | 2020-01-06 | 2021-07-15 | 에스케이하이닉스 주식회사 | Three dimensional semiconductor memory device |
| KR102747696B1 (en) * | 2020-05-28 | 2024-12-30 | 삼성전자주식회사 | Semiconductor device and method of manufacturing thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US8421193B2 (en) * | 2010-11-18 | 2013-04-16 | Nanya Technology Corporation | Integrated circuit device having through via and method for preparing the same |
-
2013
- 2013-06-18 CN CN201310241836.6A patent/CN104051414B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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