CN104766828B - The method of wafer three-dimensional integration - Google Patents
The method of wafer three-dimensional integration Download PDFInfo
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- CN104766828B CN104766828B CN201510148917.0A CN201510148917A CN104766828B CN 104766828 B CN104766828 B CN 104766828B CN 201510148917 A CN201510148917 A CN 201510148917A CN 104766828 B CN104766828 B CN 104766828B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000010354 integration Effects 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 103
- 239000002184 metal Substances 0.000 claims abstract description 103
- 238000005530 etching Methods 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011135 tin Substances 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 69
- 235000012431 wafers Nutrition 0.000 description 59
- 238000005516 engineering process Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to field of semiconductor manufacture, more particularly to a kind of method of wafer three-dimensional integration.The wafer comprising different process, the chip of difference in functionality can be integrated in a heterogeneous three-dimensional structure of wafer scale by the method for the present invention, while chip volume is maintained, the extensive function of improving chip, the metal interconnection between each functional chip has been greatly shortened, heating, power consumption has been reduced, with postponing.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of method of wafer three-dimensional integration.
Background technology
The continuous diminution of IC-components improves constantly integrated level, can on chip area every square centimeter at present
Integrated more than 1,000,000,000 transistors, and the total length of metal interconnecting wires is even more to have reached tens kilometers.This not only causes wiring to become
Obtain complex, it is often more important that delay, power consumption, noise of metal interconnection etc. all constantly increase with the reduction of characteristic size
Plus, particularly globally interconnected RC (resistance capacitance) delays have had a strong impact on the performance of integrated circuit.In addition, dynamic power consumption with
The load capacitance value of circuit is directly proportional, in the dynamic power consumption of current mainstream high performance microprocessor, has more than half all by interconnecting
Caused by line.The method for solving interconnection delay at present is to increase a series of buffers on globally interconnected line, and due to a large amount of
The addition of buffer, the power consumption of circuit is increased considerably, i.e., exchange speed for using power consumption.The use of copper-connection and bottom K media makes
Series resistance and parasitic capacitance decrease, and make that technique develops into 90nm by 130nm and overall performance increases, and introduce
Super low-K dielectric can only also maintain technological development to 65nm nodes.Therefore, metal interconnection be substituted transistor turn into determine it is integrated
The principal element of circuit performance.
Chip system (SoC, System on a Chip) technology wishes to realize the repertoire of system on a single chip, such as
Array, simulation, radio frequency, photoelectricity and MEMS (Microelectromechanical Systems, MEMS), SoC hair
Maximum difficulty is different process compatible problems in exhibition, for example realize SoC may need standard COMS, RF, Bipolar and
The techniques such as MEMS, the backing material of these manufacturing process is all different, as a consequence it is hardly possible to leading to its Integrated manufacture on one chip.
Even if backing material identical module, the manufacture feasibility of each circuit module is also considered in the mill.This aspect can not be right
The manufacture feasibility of each circuit module.This aspect can not sufficiently be optimized to each circuit module, on the other hand be
Multiple modules are in one plane realized, it is necessary to increase mask plate quantity, arrange mutually to limit during process sequence, certainly will increase
The cost of circuit manufacture, the raising of limiting performance.Therefore, the chip of current multifunction module remains discrete, and SoC's is each
Advantage is planted because the limitation of manufacture still rests on the stage of imagination.
Three-dimensional interconnection is the collection for realizing multilayer device in one single chip using the third dimension on the basis of planar circuit
Into, i.e., a big planar circuit is divided into some logically related functional modules and is distributed in multiple adjacent chip layers,
Then the three-dimensional perpendicular interconnection by penetrating substrate is integrated by multilayer chiop.Three-dimensional interconnection can realize different functions, difference
The Vertical collection of the multi-chip of technique, is greatly lowered globally interconnected length, so that interconnection delay is greatly lowered, collection is improved
Into the power consumption of circuit speed, reduction chip.Three-dimensional interconnection can be with integrated multi-layer different process or the integrated electricity of various substrates material
Road, good solution is provided for the SoC of heterogeneous chip.Three-dimensional interconnection is all physical interconnections, can solve the problem that multi-chip is different
Matter is integrated, high-bandwidth communication and the problems such as interconnection delay.
But it is existing three-dimensionally integrated to be sealed by TSV (Though Silicon Via, silicon perforation) structures 13 and the grade of tin ball 16
Dress mode is connected inside and out three-dimensionally integrated, is mainly carried out in package level (package level).Such as Fig. 1 and Fig. 2 institutes
Show, it is difficult to be realized in wafer scale (wafer level), hinder the development of the further integrated levels of SoC, this is people in the art
Member is unwilling what is seen.
The content of the invention
In view of the above problems, the present invention provides a kind of method of wafer three-dimensional integration.
The technical proposal for solving the technical problem of the invention is：
A kind of method of wafer three-dimensional integration, wherein, including：
There is provided in a bonding wafer for being provided with interconnection area and lead areas, above-mentioned bonding wafer and be provided with metal connecting line
Structure and metal level, above-mentioned metal connection structure are electrically connected the metal level of mutually insulated, and above-mentioned metal connection structure
Part surface be exposed to above-mentioned bonding wafer upper surface；
In preparing a metallic film on above-mentioned bonding wafer, above-mentioned metallic film covers above-mentioned metal connection structure exposure
Surface；
The part metallic film is removed, it is mutual with the metal that formation is electrically connected with metal connection structure in above-mentioned interconnection region
Connect layer and the metal wiring layer for being electrically connected adjacent metal connecting line construction in above-mentioned lead areas.
The method of above-mentioned wafer three-dimensional integration, wherein, above-mentioned bonding wafer includes the first wafer and the second wafer, above-mentioned
First wafer includes the first silicon substrate layer and the first BEOL dielectric layers；Second wafer includes the second silicon substrate layer and the 2nd BEOL is situated between
Matter layer, above-mentioned second integrated circuit layer covers the upper surface of above-mentioned first integrated circuit layer.
The method of above-mentioned wafer three-dimensional integration, wherein, any of the above-described metal connection structure electrically connects two above-mentioned gold
Belong to layer.
The method of above-mentioned wafer three-dimensional integration, wherein, any of the above-described metal connection structure electrically connects two above-mentioned gold
Belong to layer, respectively in above-mentioned first BEOL dielectric layers and in the 2nd BEOL dielectric layers.
The method of above-mentioned wafer three-dimensional integration, wherein, the preparation technology of above-mentioned metal connection structure is：Ditch after first through hole
The etching technics of through hole after the etching technics of groove or first groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the etching technics of groove includes after above-mentioned first through hole：
Etch above-mentioned second silicon substrate layer, above-mentioned 2nd BEOL dielectric layers and above-mentioned first BEOL dielectric layers, with formed by
Above-mentioned layer on surface of metal gives exposed through hole；
On the basis of above-mentioned through hole, etching, which is located at any two, needs what is electrically connected by above-mentioned metal connection structure
Second silicon substrate layer of metal layer, to form above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the etching technics of through hole includes after above-mentioned first groove：
Second silicon substrate of the metal layer that etching needs to electrically connect by above-mentioned metal connection structure positioned at any two
Bottom, to form groove；
On the basis of above-mentioned groove, twoth BEOL dielectric layer and first of the etching positioned at any of the above-described metal layer
BEOL dielectric layers, to form above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, after above-mentioned first through hole after the etching technics of groove or first groove
The etching technics of through hole also includes：
Formed after above-mentioned groove, in filling metal material in above-mentioned groove.
The method of above-mentioned wafer three-dimensional integration, wherein, the material of above-mentioned metal material is copper, aluminium, tin or tungsten.
The method of above-mentioned wafer three-dimensional integration, wherein, the material of above-mentioned metal lead wire is metal or metal and metal nitrogen
The mixing material of compound.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
Wafer comprising different process, the chip of difference in functionality can be integrated in by the method for the present invention by a wafer
In the heterogeneous three-dimensional structure of level, while chip volume is maintained, the extensive function of improving chip has been greatly shortened each
Metal interconnection between functional chip, reduces heating, power consumption, with postponing, improves the bandwidth between each functional module.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is the structural representation of three-dimensional TSV integrated morphologies in background of invention；
Fig. 2 is the structural representation of tin ball packaged type in background of invention；
Fig. 3-9 is the corresponding structural representation of each step in the inventive method.
Embodiment
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is the structural representation of three-dimensional TSV integrated morphologies in background of invention；
Fig. 2 is the structural representation of tin ball packaged type in background of invention；
Fig. 3-9 is the corresponding structural representation of each step in the inventive method.
Embodiment
The present invention provides a kind of method of wafer three-dimensional integration.LOC region and three-dimensional suitable for being bonded wafer
Interconnection area needs separated situation.
The core concept of the present invention is to face each other placement by the way that two panels to have been completed to the wafer of integrated circuit preparation, then will
Above-mentioned two panels wafer bonding, then by setting the TSV between wafer, realize difference in functionality between different wafers chip it
Between interconnection, and the protective layer that thickness is higher than metal interconnecting layer is formed by using the deposition of multiple protective layer, so as to protect
Protect the metal interconnecting layer structure of chip.
The inventive method is described in detail below in conjunction with the accompanying drawings, but it is not as a limitation of the invention.
First there is provided the bonding wafer that one is provided with interconnection area 1 and lead areas 2, metal is provided with bonding wafer
Connecting line construction 28 and metal level, metal connection structure are electrically connected the metal level of mutually insulated, and metal connection structure
Part surface is exposed to the upper surface of bonding wafer.
Interconnection area comprises at least a metal connection structure, and lead areas comprises at least two metal connection structures；
In preparing a metallic film 29 on bonding wafer, metallic film 29 covers the surface of metal connection structure exposure.
Part metals film 29 is removed, to form the metal interconnecting layer electrically connected with metal connection structure in interconnection region
210 and the metal wiring layer 211 that is electrically connected adjacent metal connecting line construction in lead areas.
Metal lead wire 210 is prepared to give the adjacent ＇ of the metal connection structure 28 in the lead areas and 28 ＇ ＇
To electrically connect.
Below, a specific embodiment is lifted to be described in further detail the present invention.
First there is provided the first wafer and the second wafer for having completed integrated circuit preparation, above-mentioned first wafer includes the
One silicon substrate layer 21 and the structure of the first BEOL dielectric layers 22, above-mentioned second wafer include the second silicon substrate layer 24 and the 2nd BEOL
The structure of dielectric layer 25.
Wherein, the first BEOL dielectric layers 22 and the 2nd BEOL dielectric layers 25 include some metal levels, and hair is done for ease of illustrating
Bright purpose, only shows metal level at six.
The first i.e. above-mentioned BEOL dielectric layers also include the first metal layer 23, the ＇ of the 3rd metal level 23 and fifth metal layer
23 ＇ ＇, the 2nd BEOL dielectric layers 25 also include second metal layer 26, the ＇ of the 4th metal level 26 and the ＇ ＇ of the 6th metal level 26.
Wherein, the first metal layer is the metal interconnection layer of integrated circuit on the first wafer, with integrated circuit in the first wafer
Interior each function element electrical connection.Second metal layer is the part-structure of the metal interconnection layer of integrated circuit on the second wafer,
Electrically connected with each function element in the second wafer in integrated circuit.
Then, the second integrated circuit layer covers the upper surface of first integrated circuit layer, and its structure is tied as shown in Figure 3
Structure.The first wafer and the second wafer stacked again to completion carries out bonding technology, it is connected as entirety, then to completing bonding work
The wafer of skill carries out reduction process, so that the first silicon substrate layer 21 and the second silicon substrate layer 24 is thinned, follow-up to the first silicon to facilitate
The etching technics of the silicon substrate layer 24 of basalis 21 and second, completes the chip interconnection between wafer.
Wherein, above-mentioned bonding technology can use any one process program of prior art with reduction process.
Then, the first lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to the first metal layer and the second gold medal
The part of the second silicon substrate layer 24 above category layer performs etching technique, etching technics to the above-mentioned upper surface of 2nd BEOL dielectric layers 25
Stop, structure as shown in Figure 4.Then at the second silicon substrate layer 24 and the 2nd BEOL dielectric layers 25 disposed thereon, one layer of separation layer 27,
To protect the second silicon substrate layer 24 and the 2nd BEOL dielectric layers 25 not to be destroyed in subsequent technique.
Wherein, the material of separation layer 27 is preferably oxide or nitride.
Afterwards, the second lithographic etching technics is carried out to the first wafer and the second wafer, i.e., to the above the first metal layer
The part of two BEOL dielectric layers 25 performs etching technique, and etching technics to the first metal layer upper surface stops, structure as shown in Figure 5.
Then, the 3rd lithographic etching technics is carried out to above-mentioned first wafer and the second wafer, i.e., to above second metal layer
The part of the 2nd BEOL dielectric layers 25 perform etching technique, etching technics to above-mentioned second metal layer upper surface stops, such as Fig. 6 institutes
Show structure.
Then, walked to each in first, second, and third lithographic etching technics in the groove that etching technics is formed, filling gold
Belong to material, form the first metal connection structure 28, the ＇ of the second metal connection structure 28 and the ＇ ＇ of the 3rd metal connection structure 28, and go
Except separation layer 27, structure as shown in Figure 7.
Wherein, metal material is preferably copper, aluminium, tin or tungsten etc..
Then, in the second silicon base 24, the first metal connection structure 28, the ＇ of the second metal connection structure 28 and the 3rd metal
The ＇ ＇ upper surfaces of connecting line construction 28 deposition layer of metal film 29, structure as shown in Figure 8.
Wherein, the material of metallic film 29 is preferably the mixing material of metal or metal and metal nitride.
Finally, the 4th lithographic etching technics is carried out to the first wafer and the second wafer, i.e., part metals film 29 carried out
Etching, is formed with first metal connection structure 28 is electrically connected in interconnection region 1 metal interconnecting layer 210 and by lead areas 2
The metal wiring layer 211 that the adjacent ＇ of second metal connection structure 28 and the 3rd metal connection structure 28 ＇ ＇ are electrically connected.
Above-mentioned first to the 3rd lithographic etching technics is only the present embodiment narration and sets numbering, does not constitute to this implementation
Example limitation, the need for its processing step can be according to actual product, is adjusted correspondingly.
In summary, the method for wafer three-dimensional integration of the invention can will include different works by the method for the present invention
Skill, the wafer of the chip of difference in functionality are integrated in a heterogeneous three-dimensional structure of wafer scale, for needing lead areas and three
Tieing up interconnection region needs separated process conditions, while chip volume is maintained, the extensive function of improving chip, significantly
Degree shortens the metal interconnection between each functional chip, reduces heating, power consumption, with postponing, improves each functional module
Between bandwidth.
For a person skilled in the art, read after described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.In power
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (10)
1. a kind of method of wafer three-dimensional integration, it is characterised in that including：
There is provided in a bonding wafer for being provided with interconnection area and lead areas, the bonding wafer and be provided with metal connection structure
And metal level, the metal connection structure is electrically connected the metal level of mutually insulated, and the portion of the metal connection structure
Divide surface exposed to the upper surface of the bonding wafer；
In preparing a metallic film on the bonding wafer, the metallic film covers the table of the metal connection structure exposure
Face；
The part metallic film is removed, to form the metal interconnecting layer electrically connected with metal connection structure in the interconnection area
With the metal wiring layer for being electrically connected adjacent metal connecting line construction in the lead areas.
2. the method for wafer three-dimensional integration as claimed in claim 1, it is characterised in that the bonding wafer includes the first wafer
With the second wafer, first wafer includes the first silicon substrate layer and the first BEOL dielectric layers；Second wafer includes the second silicon substrate
Bottom and the 2nd BEOL dielectric layers, the second integrated circuit layer cover the upper surface of the first integrated circuit layer.
3. the method for wafer three-dimensional integration as claimed in claim 1, it is characterised in that any metal connection structure is electric
Connect two metal levels.
4. the method for wafer three-dimensional integration as claimed in claim 3, it is characterised in that any metal connection structure institute electricity
Two metal levels are connected, respectively in the first BEOL dielectric layers and in the 2nd BEOL dielectric layers.
5. the method for wafer three-dimensional integration as claimed in claim 2, it is characterised in that the preparation work of the metal connection structure
Skill is：After first through hole after the etching technics of groove or first groove through hole etching technics.
6. the method for wafer three-dimensional integration as claimed in claim 5, it is characterised in that the etching work of groove after the first through hole
Skill includes：
Second silicon substrate layer, the 2nd BEOL dielectric layers and the first BEOL dielectric layers are etched, so that formed will be described
Layer on surface of metal gives exposed through hole；
On the basis of the through hole, etching is located at the metal that any two needs to electrically connect by the metal connection structure
The second silicon substrate layer above layer, to form the groove.
7. the method for wafer three-dimensional integration as claimed in claim 5, it is characterised in that the etching work of through hole after the first groove
Skill includes：
Second silicon substrate layer of the metal layer that etching needs to electrically connect by the metal connection structure positioned at any two,
To form groove；
On the basis of the groove, etching is located at the 2nd BEOL dielectric layers and the first BEOL of any metal layer
Dielectric layer, to form the groove.
8. the method for wafer three-dimensional integration as claimed in claims 6 or 7, it is characterised in that the quarter of groove after the first through hole
The etching technics of through hole also includes after etching technique or first groove：
Formed after the groove, in filling metal material in the groove.
9. the method for wafer three-dimensional integration as claimed in claim 8, it is characterised in that the material of the metal material be copper,
Aluminium, tin or tungsten.
10. the method for wafer three-dimensional integration as claimed in claim 1, it is characterised in that the material of the metal lead wire is gold
The mixing material of category or metal and metal nitride.
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| CN105914202B (en) * | 2016-06-13 | 2018-11-13 | 上海珏芯光电科技有限公司 | Display driving backboard, display and manufacturing method |
| CN109148361B (en) * | 2018-08-28 | 2019-08-23 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
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| CN103137636A (en) * | 2011-11-30 | 2013-06-05 | 索尼公司 | Semiconductor apparatus, semiconductor apparatus manufacturing method and electronic equipment |
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
| CN104051329A (en) * | 2013-03-15 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect structure and method for stacked devices |
| CN104051414A (en) * | 2013-03-12 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect Structure and Method |
| CN104051423A (en) * | 2013-03-13 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect apparatus and method |
| CN104377164A (en) * | 2014-09-28 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Through silicon var wafer interconnection process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5729100B2 (en) * | 2011-04-11 | 2015-06-03 | ソニー株式会社 | Semiconductor device manufacturing method, semiconductor device, and electronic apparatus |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137636A (en) * | 2011-11-30 | 2013-06-05 | 索尼公司 | Semiconductor apparatus, semiconductor apparatus manufacturing method and electronic equipment |
| CN103579114A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Integrated semiconductor device and wafer level method of fabricating the same |
| CN104051414A (en) * | 2013-03-12 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect Structure and Method |
| CN104051423A (en) * | 2013-03-13 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect apparatus and method |
| CN104051329A (en) * | 2013-03-15 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Interconnect structure and method for stacked devices |
| CN104377164A (en) * | 2014-09-28 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Through silicon var wafer interconnection process |
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