CN104022034B - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN104022034B CN104022034B CN201310063976.9A CN201310063976A CN104022034B CN 104022034 B CN104022034 B CN 104022034B CN 201310063976 A CN201310063976 A CN 201310063976A CN 104022034 B CN104022034 B CN 104022034B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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Abstract
A forming method of a semiconductor structure comprises the following steps: providing a semiconductor substrate, a surface of the semiconductor substrate is provided with a stop layer, a surface of the stop layer is provided with a grid electrode film, partial surface of the grid electrode film is provided with a first mask layer, a surface of the first mask layer is provided with a second mask layer, wherein the second mask layer and the stop layer are made of the same material, and the first mask layer and the second mask layer are made of different material; forming a protection layer on a side wall surface of the first mask layer, and the protection, the second mask layer and the stop layer are made of the same material; etching the grid electrode film by using the second mask layer as a mask after the protection layer is formed until the surface of the stop layer is exposed, thereby forming the grid electrode layer; the size of the formed semiconductor structure is easily and accurately controlled, so the formed semiconductor device is stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the fast development of ic manufacturing technology, promote the semiconductor device in integrated circuit, especially MOS
（Metal Oxide Semiconductor, Metal-oxide-semicondutor）The size of device constantly reduces, and with this collection is met
Miniaturization and integrated requirement into circuit development.During the size of MOS transistor device persistently reduces, existing work
Skill is challenged as the technique of gate dielectric layer using silicon oxide or silicon oxynitride.Using silicon oxide or silicon oxynitride as gate medium
The transistor that layer is formed occurs in that some problems, including leakage current increase and the diffusion of impurity, so as to affect transistor
Threshold voltage, and then affect the performance of semiconductor device.
To solve problem above, the transistor containing high-K gate dielectric layer and metal gate is suggested.Described containing high K grid
In the transistor of dielectric layer and metal gate, using high K（Dielectric constant）Material replaces the silicon oxide commonly used or nitrogen oxidation Si-gate to be situated between
Material, can reduce transistor size, it is to avoid the generation of leakage current, and improve the performance of transistor.
The planar structure schematic diagram with high-K gate dielectric layer and the transistor of metal gate of prior art is as shown in figure 1, bag
Include：Positioned at the first medium layer 105 on the surface of Semiconductor substrate 100, have in the first medium layer 105 and expose quasiconductor lining
The opening on the surface of bottom 100（It is not shown）；Positioned at the high-K gate dielectric layer 101 of the lower surface of the opening；Positioned at the high K grid
The metal gate layers 103 on the surface of dielectric layer 101；Quasiconductor positioned at high-K gate dielectric layer 101 and the both sides of metal gate layers 103 is served as a contrast
The side wall 104 on the surface of bottom 100；Positioned at the Semiconductor substrate of high-K gate dielectric layer 101, metal gate layers 103 and the both sides of side wall 104
Source region 106a and drain region 106b in 100.
However, as the size of transistor persistently reduces, the size of transistor is difficult to precise control, causes semiconductor device
Performance it is unstable.
More related datas with regard to the transistor with high-K gate dielectric layer and metal gate or its formation process refer to public affairs
The number of opening is the U.S. patent documents of US2011/0195549.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of semiconductor structure, can be in precise control transistor
The characteristic size of grid layer, it is ensured that the stable performance of transistor and semiconductor device.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Quasiconductor lining is provided
Bottom, the semiconductor substrate surface has stop-layer, and the stopping layer surface having grid thin film, the part of the grid thin film
Surface has the first mask layer, and the first mask layer surface has the second mask layer, the material of second mask layer and stops
Only the material of layer is identical, and the material of first mask layer and the second mask layer is different；In the side wall table of first mask layer
Face forms protective layer, and the material of the protective layer is identical with the material of the second mask layer and stop-layer；Forming the protective layer
Afterwards, with the second mask layer as mask etching described in grid thin film, to expose stop layer surface, formed grid layer.
Optionally, the material of first mask layer be silicon nitride, the material of second mask layer, protective layer and stop-layer
Expect for silicon oxide, the material of the grid thin film is polysilicon.
Optionally, the formation process of the protective layer is plasma treatment, and the plasma treatment process includes：Pressure 2
Millitorr~100 millitorr, plasma dissociation power is 100 watts~1500 watts, and 0~50V of bias voltage, gas includes O2, gas
1 standard milliliters of total flow/minute~1000 standard milliliters/minute, 5 seconds~200 seconds response time.
Optionally, the thickness of the protective layer is 1 angstrom~100 angstroms.
Optionally, also include：After the grid layer is formed, second mask layer is removed, and in the grid layer
Side wall is formed with the semiconductor substrate surface of the first mask layer both sides.
Optionally, ion implanting is carried out to Semiconductor substrate as mask with the side wall and the first mask layer, in grid layer
Source region and drain region are formed in the Semiconductor substrate of both sides.
Optionally, also include：Gate dielectric membrane is formed in the stopping layer surface；Formed on the gate dielectric membrane surface
Grid thin film；When the grid thin film formation grid layer is etched, the gate dielectric membrane is etched, form gate dielectric layer.
Optionally, the material of the gate dielectric membrane is high K dielectric material.
Optionally, also include：Cover film is formed on the gate dielectric membrane surface, the material of the cover film is nitrogen
Change tantalum or titanium nitride；Grid thin film is formed on the cover film surface；When the grid thin film formation grid layer is etched, carve
The cover film is lost, coating is formed.
Optionally, also include：After the grid layer is formed, in the semiconductor substrate surface dielectric layer, institute are formed
The surface for stating dielectric layer flushes with the surface of the first mask layer；After dielectric layer is formed, first mask layer and grid are removed
Pole layer, forms opening；Metal gate is formed in the opening.
Optionally, the formation process of first mask layer and the second mask layer includes：In the grid layer film surface
Form the first mask thin film；The second mask thin film is formed in the first mask film surface；In the second mask thin film table
Face forms the first photoresist layer；With first photoresist layer as mask, etch the second mask thin film and the first mask is thin
Film, till grid thin film is exposed.
Optionally, also include：Before the grid thin film is etched, in the second mask layer surface the second photoetching is formed
Glue-line；With second photoresist layer and the second mask layer as mask, the grid thin film is etched, form grid layer.
Compared with prior art, technical scheme has advantages below：
The grid film surface has the first mask layer, and the first mask layer surface has the second mask layer；Wherein,
First mask layer is used as mask when being subsequently formed side wall, mask of second mask layer as etching grid thin film；
Protective layer is formed in the sidewall surfaces of first mask layer, and the material of the protective layer is identical with the second mask layer；Due to
, used as the mask of etching grid thin film, the technique of the etching grid thin film is for second mask layer for second mask layer
It is relatively low to the etch rate of the protective layer with relatively low etch rate, therefore the etching technics；The protective layer energy
First mask layer is enough protected not to be thinned in the technique of etching grid thin film, so as to ensure that the grid that subsequent etching is formed
During the layer of pole, the grid layer for being formed will not can make formed grid layer because of the thinning and size reduction of the first mask layer
Size meet design standard；Therefore, the characteristic size of the grid layer is accurately easily-controllable, makes the feature chi of formed transistor
Very little standard is accurate, and the stable performance of the semiconductor device for being formed is good.
Further, the formation process of the protective layer be plasma treatment process, the gas of the plasma treatment process
Body is oxygen；In the plasma treatment process, oxygen is dissociated into as plasma, and the regulation for passing through technological parameter,
Oxygen gas plasma is set to carry sufficiently high energy；Because the material of the first mask layer is silicon nitride, the oxygen plasma is made
The energy that body is carried can destroy the chemical bond of silicon nitride, in the plasma-treating technology, first mask layer
Sidewall surfaces can produce silicon ion and Nitrogen ion；Then, oxonium ion substitutes Nitrogen ion and constitutes silicon oxide with the silicon ion
Material, and the Nitrogen ion for being substituted is pulled away with the air-flow in technical process.And, the plasma treatment process can make
The oxygen gas plasma for being injected accumulates in the sidewall surfaces of first mask layer, it is easier in making oxonium ion and silicon nitride
Silicon ion generates silicon oxide, meanwhile, make formed silicon oxide thickness thin, i.e. the thickness of thin of protective layer, follow-up institute will not be increased
The size of the grid layer of formation, makes the accurate size of formed grid layer.
Description of the drawings
Fig. 1 is the cross-sectional view with high-K gate dielectric layer and the transistor of metal gate of prior art；
Fig. 2 to Fig. 3 is a kind of cross-sectional view of the partial routine for forming transistor as shown in Figure 1；
Fig. 4 to Fig. 9 is the section knot of the forming process of the forming method of the semiconductor structure described in embodiments of the invention
Structure schematic diagram.
Specific embodiment
As stated in the Background Art, as the size of transistor persistently reduces, the size of transistor is difficult to precise control, causes
Performance of semiconductor device it is unstable.
Fig. 2 to Fig. 3 is a kind of cross-sectional view of the partial routine for forming transistor as shown in Figure 1, including：
Fig. 2 is refer to, in the surface of Semiconductor substrate 200 formation silicon oxide film 201, positioned at the surface of silicon oxide film 201
High K dielectric thin film 202 and the polysilicon membrane 203 positioned at the surface of high K dielectric thin film 202；In the table of the polysilicon membrane 203
Face forms silicon nitride layer 204 and the silicon oxide layer 205 positioned at the surface of silicon nitride layer 204.
Wherein, the polysilicon membrane 203 is used to form dummy gate layer, and the dummy gate layer is the metal gate being subsequently formed
Take up space position；The silicon nitride layer 204 is used for when side wall is subsequently formed as mask, protects the pattern of dummy gate layer not
It is destroyed；The silicon oxide layer 205 is used to form the mask of dummy gate layer and gate dielectric layer as etching；The silicon oxide film
201 are used to define the stop position of etches polycrystalline silicon thin film 203 and the technique of high K dielectric thin film 202, it is to avoid Semiconductor substrate 200
Surface sustains damage.
Fig. 3 is refer to, polysilicon membrane 203 described in the silicon oxide layer 205 as mask etching（As shown in Figure 2）And height
K dielectric films 202（As shown in Figure 2）, formation dummy gate layer 203a of the polysilicon membrane 203, the high K dielectric thin film 202
Form gate dielectric layer 202a.
After dummy gate layer 203a is formed, the silicon oxide layer 205 is removed, and be with the silicon nitride layer 204
Mask, on the surface of silicon oxide film 201 of the dummy gate layer 203a both sides side wall is formed（It is not shown）, and in side wall both sides
Source region and drain region are formed in Semiconductor substrate 200；It is follow-up again dummy gate layer 203a to be substituted with metal material, form metal
Grid, to complete the manufacture of transistor.
Find through the present inventor's research, in order that the etching technics stops at silicon oxide film 201, it is described
Etching technics needs to ensure that the speed for etching silicon oxide is slower such that it is able to protect for silicon oxide has higher selectivity
The pattern of card silicon oxide layer 205 will not change in etches polycrystalline silicon thin film 203, and the etching technics can stop at oxygen
SiClx thin film 201.However, when ensure that the etching technics is slower for the speed of etching oxidation silicon, it is difficult to while taking into account
For the Etch selectivity of silicon nitride layer 204, the speed that frequently can lead to etch the silicon nitride layer 204 is very fast, and then causes
The side wall of the silicon nitride layer 204 is thinned；Once and the silicon nitride layer 204 is thinned, it is easily caused the puppet that etching is formed
The size of grid layer 203a diminishes relative to design size（As is shown in phantom in fig. 3, be dummy gate layer 203a be design size when
Pattern profile graphics）, therefore make the characteristic size of dummy gate layer 203a be difficult to precise control, and then cause what is subsequently formed
The size of metal gate and whole transistor is inaccurate, especially when the characteristic size of the transistor further reduces, institute
The lax pair for stating size is more notable in the performance impact of semiconductor device.
Further study through the present inventor, in the grid film surface for being used to be formed dummy gate layer first is formed
Mask layer and after the second mask layer of the first mask layer surface, forms in the sidewall surfaces of first mask layer and protects
Sheath；Wherein, first mask layer is used as mask when being subsequently formed side wall, and second mask layer is thin as etching grid
The mask of film, therefore, the technique of subsequent etching grid thin film is relatively low for the etch rate of second mask layer；Make the guarantor
The material of sheath is identical with the second mask layer, therefore the protective layer is in the technique of subsequent etching grid thin film, with higher
Etch selectivity, i.e., the speed of follow-up etching technics etch-protecting layer is slower；Therefore, the protective layer can be protected described
First mask layer is not thinned in the etching technics, and then ensure that the size of the grid layer after etching meets design mark
Standard, makes the characteristic size of the grid layer accurate, the stable performance of the semiconductor device and good.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Fig. 9 is the section knot of the forming process of the forming method of the semiconductor structure described in embodiments of the invention
Structure schematic diagram.
Refer to Fig. 4, there is provided Semiconductor substrate 300, the surface of the Semiconductor substrate 300 has stop-layer 301, described to stop
Only the surface of layer 301 has gate dielectric membrane 302, and the surface of the gate dielectric membrane 302 has grid thin film 303, the grid layer
The surface of thin film 303 has the first mask thin film 304, and the surface of the first mask thin film 304 has the second mask thin film 305, the
The material of two mask thin film 305 is identical with the material of stop-layer 301, the first mask thin film 304 and the second mask thin film 305
Material it is different.
The Semiconductor substrate 300 is used to provide work platformses for subsequent technique；The Semiconductor substrate 300 is silicon lining
Bottom, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator（SOI）Substrate, germanium on insulator（GOI）Substrate, glass substrate or III-
V compounds of group substrates（Such as GaAs etc.）.
In the present embodiment, the semiconductor structure for being formed is used to be formed with high-K gate dielectric layer and metal gate layers
Transistor, the size with high-K gate dielectric layer and the transistor of metal gate layers is little, is conducive to the miniature of semiconductor device
Change and integrated, however, because size is little, characteristic size is more difficult to precise control when making to be formed the transistor；It is described to stop
Only the material of layer 301 is silicon oxide, and the material of the gate dielectric membrane 302 is high K dielectric material, the grid layer film 303
Material be polysilicon；The stop-layer 301 is used to define the stop position of subsequent etching grid thin film 303, it is to avoid quasiconductor
Substrate 300 sustains damage in etching technics；Secondly, the stop-layer 301 can also be used to strengthen the gate dielectric membrane 302
And the adhesion between Semiconductor substrate 300, reduce the generation of leakage current；Again, the stop-layer 301 can also adopted subsequently
When source region and the drain region of transistor is formed with ion implanting, protection Semiconductor substrate 300 surface is injury-free.
The gate dielectric membrane 302 is used to form the gate dielectric layer of transistor, and the grid layer film 303 is used to form crystalline substance
The dummy gate layer of body pipe, the dummy gate layer is that the metal gate being subsequently formed takes up space and position, is ultimately formed with high K grid
The transistor of dielectric layer and metal gate layers.
The first mask thin film 304 is used to form the first mask layer, and the second mask thin film 305 is used to form second
Mask layer；First mask layer is used to protect formed grid layer surface injury-free when side wall is subsequently formed and shape
Looks are good；Second mask layer is used in subsequent etching grid thin film 303 as mask；In the present embodiment, described first
The material of mask thin film 304 is silicon nitride, and the material of the second mask thin film 305 is silicon oxide；Wherein, due to silicon nitride
Hardness is bigger, it is higher to the protective capability of grid layer when side wall is formed；Because second mask layer is subsequent etching grid
The mask of thin film 303, and the stop-layer 301 is used to define the stop position of the technique of etching grid thin film 303, therefore institute
Stating the mask thin film 305 of stop-layer 301 and second needs have higher Etch selectivity in follow-up etching technics, to ensure
The grid layer dimensional standard that etching is formed is accurate, and is not damaged.In the present embodiment, the stop-layer 301 and second
The material of mask thin film 305 is silicon oxide, it is therefore desirable to make follow-up etching technics have higher etching for silicon oxide
Selectivity.
Additionally, being subsequently formed after grid layer, need to remove the second mask layer, and retain the first mask layer as formation side
The mask of wall, therefore the material of the first mask thin film 304 is different from the material of the second mask thin film 305, in the present embodiment
In, the material of the first mask thin film 304 is silicon nitride.
The stop-layer 301, gate dielectric membrane 302, grid thin film 303, the first mask thin film 304 and the second mask thin film
305 formation process is depositing operation, it is preferred that chemical vapor deposition method；The stop-layer 301, gate dielectric membrane 302,
Depending on the thickness of grid thin film 303, the first mask thin film 304 and the second mask thin film 305 is according to specific process requirements, should not
Excessively limit.
In one embodiment, the surface of the gate dielectric membrane 302 is also formed with cover film（It is not shown）, in the covering
Film surface forms grid thin film 303, and the material of the cover film is tantalum nitride or titanium nitride；The cover film is used for shape
Into coating, the coating is used to improve the isolation effect between the gate dielectric layer that is subsequently formed and metal gate, and after preventing
In continuous technical process, impurity pollution is diffused in metal gate by gate dielectric layer.
In another embodiment, the gate dielectric membrane be silicon oxide, then in subsequent technique etching grid thin film with shape
Into grid layer, and formed after side wall, source region and drain region, that is, form transistor.
Fig. 5 is refer to, in the second mask thin film 305（As shown in Figure 4）Surface forms the first photoresist layer 306；With
First photoresist layer 306 is mask, etches the second mask thin film 305 and the first mask thin film 304（Such as Fig. 4 institutes
Show）, till grid thin film 303 is exposed, form the second mask layer 305a and the first mask layer 304a.
First photoresist layer 306 is used to define to need the position to form grid layer；Additionally, the second mask thin film
305 and first also have bottom anti-reflection layer between photoresist layer 306（It is not shown）, first photoresist layer 306 is formed at
The bottom anti-reflective layer surface, the formation process of the bottom anti-reflection layer is depositing operation；First photoresist layer 306
Formation process be：First photoresist film is formed using spin coating proceeding；Using graphical first photoresist of exposure technology
Thin film, first photoresist layer 306 is only covered needs to be subsequently formed the correspondence position of grid layer.
The technique of the second mask thin film 305 of the etching and the first mask thin film 304 is anisotropic dry etching work
Skill；The anisotropic dry etch process can by control technological parameter, make the first formed mask layer 304a and
The side wall of the second mask layer 305a is perpendicular to the surface of grid thin film 303, or makes the first mask layer 304a and the second mask
The side wall of layer 305a is inclined relative to the surface of grid thin film 303；The first mask layer 304a and the second mask layer 305a sides wall
Pattern according to concrete technology demand depending on, in the present embodiment, the first mask layer 304a's and the second mask layer 305a
Side wall is inclined relative to the surface of grid thin film 303.
After the etching technics is completed, first photoresist layer 306 and bottom are removed using wet clean process
Portion's anti-reflecting layer；Due to the transistor size for needing to be formed in the present embodiment it is minimum, therefore, complete etch the second mask thin film
305 and the technique of the first mask thin film 304 after, first photoresist layer 306 can not meet the follow-up etching that continues and form grid
The technique of pole layer, it is difficult to ensure that the second mask layer 305a surfaces are not damaged in the technical process for be subsequently formed grid layer
Wound, once and the pattern or size of the second mask layer 305a are difficult to ensure that, formed grid layer and transistor can be affected
Characteristic size degree of accuracy, then affect semiconductor device performance.Therefore, the first mask layer 304a and the second mask are being formed
After layer 305a, need to remove first photoresist layer 306, and form photoresist layer covering as subsequent etching processes again
Film, and the accurate size and pattern of the photoresist layer for being formed again are good, ensure that the feature chi of the grid layer that etching is formed
It is very little accurate easily-controllable.
Fig. 6 is refer to, in the sidewall surfaces of the first mask layer 304a protective layer 307 is formed, the protective layer 307
Material is identical with the material of the second mask layer 305a and stop-layer 301.
The protective layer 307 is used for the first mask layer 304a of protection in the technique that subsequent etching forms grid layer, side wall
Will not be etched thinning, ensure that the characteristic size of the grid layer that etching is formed is accurately easily-controllable with this.
In the present embodiment, the material of the second mask layer 305a and stop-layer 301 is silicon oxide, therefore the protection
The material of layer 307 is silicon oxide, and the thickness of the protective layer 307 is 1 angstrom~100 angstroms, and formation process is：Using plasma treatment
The sidewall surfaces of the first mask layer 304a described in PROCESS FOR TREATMENT, make in the oxygen gas plasma and the first mask layer 304a in technique
Silicon ion form silicon oxide, the silicon oxide is formed at the protective layer 307 of the first mask layer 304a sidewall surfaces；It is described etc.
Ion processing technique is：Millitorr~100 millitorr of pressure 2, plasma dissociation power is 100 watts~1500 watts, bias voltage 0~
50V, gas includes O2, 1 standard milliliters of total gas flow rate/minute~1000 standard milliliters/minute, -200 seconds 5 seconds response time.
In the plasma treatment process, oxygen dissociation is become into plasma, carry the oxygen gas plasma
Higher-energy；The material of the first mask layer 304a is silicon nitride, because the oxygen gas plasma carries high-energy, can
The chemical bond of destruction silicon nitride, produces silicon ion and Nitrogen ion；Oxonium ion in plasma treatment process can with the silicon from
Son constitutes silica material, and the Nitrogen ion for being substituted is pulled away with the air-flow in technical process.And, by technological parameter
Regulation, the energy that can make oxygen gas plasma institute band interrupts enough the chemical bond of silicon nitride；Also, by technological parameter
Adjust, injected oxygen gas plasma can be made to accumulate in the sidewall surfaces of the first mask layer 304a, it is easier to make oxygen
Ion generates silicon oxide with the silicon ion in silicon nitride；Additionally, the regulation for passing through technological parameter, makes injected oxygen plasma
Body accumulates in the sidewall surfaces of the first mask layer 304a, makes formed silicon oxide thickness thin, therefore the protection for being formed
The thickness of thin of layer 307, will not increase the size of the grid layer for subsequently being formed.
The plasma treatment process is similar to anisotropic dry etch process, and can enter in identical within the chamber
OK, thus the protective layer 307 can etching the first mask layer 304a and the second mask layer 305a within the chamber carry out, can
Simplified flowsheet step；And, the thickness of thin of protective layer 307 that the plasma treatment process is formed, in first mask layer
The sidewall surfaces of 304a form protective layer 307 will not make mask pattern size that significant change occurs, and make the protective layer 307 and the
The size of one mask layer 304a does not interfere with the technique of subsequent etching grid thin film 303, ensure that formed grid layer chi
It is very little accurate.
In prior art, because the technique of subsequent etching grid thin film 303 needs to ensure first for the second mask layer
305a and stop-layer 301 have higher Etch selectivity, therefore, it is difficult to while taking into account the etching for the first mask layer 304a
Selectivity, the etch rate for being easily caused the etching technics to the first mask layer 304a is higher, causes first mask layer
The side wall of 304a is etched thinning, and then causes the size of grid layer that the etching technics formed inclined compared to design size
It is little, therefore the characteristic size of the grid layer is difficult to precise control, the performance of transistor is bad.Therefore in the present embodiment, need
Protective layer 307 is formed in the sidewall surfaces of the first mask layer 304a.
In the present embodiment, follow-up etching technics is to the second mask layer 305a and the etching selection of stop-layer 301
Property is higher, therefore when the protective layer 307 is identical with the material of the second mask layer 305a, follow-up etching technics is to institute
The etching speed for stating protective layer 307 is also relatively slow, and the protective layer 307 can play protection the first mask layer 304a sides wall not
It is thinned, so as to ensure that the accurate size standard of the grid layer that etching is formed and being easily controlled, and then makes formed crystal
The stable performance of pipe and semiconductor device.
Fig. 7 is refer to, after the protective layer 307 is formed, on the second mask layer 305a surfaces the second light is formed
Photoresist layer 308；With the mask layer 305a of second photoresist layer 308 and second as mask, the grid thin film 303 is etched（Such as
Shown in Fig. 6）, to the surface of stop-layer 301 is exposed, form grid layer 303a.
Second photoresist layer 308 is used for during etching grid thin film 303, protects second mask layer
The surface of 305a is injury-free, and maintains the pattern of the second mask layer 305a and do not change, and, second light
The figure Precision criterion of photoresist layer 308, further ensures the degree of accuracy of the characteristic size of the grid layer 303a that etching is formed.Institute
The formation process for stating the second photoresist layer 308 is identical with the technique for forming the first photoresist layer 306, and therefore not to repeat here.
The technique of the etching grid thin film 303 is anisotropic dry etch process；In the present embodiment, due to institute
State the surface of stop-layer 301 and there is gate dielectric membrane 302（As shown in Figure 6）, the surface of gate dielectric membrane 302 has cover film（Not
Illustrate）, the gate surface 303 is formed at the cover film surface, therefore, the anisotropic dry etch process exists
After etching the grid thin film 303, continue to etch the cover film and gate dielectric membrane 302, until exposing stop-layer
Till 301；Coating is formed after the cover film etching（It is not shown）, formation grid are situated between after the gate dielectric membrane 302 is etched
Matter layer 302a.
The material of the grid layer 303a is polysilicon, in the present embodiment, because the transistor of required formation has high K
Gate dielectric layer and metal gate layers, therefore the grid layer 303a is for used as dummy gate layer, the metal gate to be subsequently formed to be accounted for
According to space and position.
Fig. 8 is refer to, after the grid layer 303a is formed, the second mask layer 305a is removed（As shown in Figure 7）,
And form side wall 309 on the surface of stop-layer 301 of the grid layer 303a and the first mask layer 304a both sides；With the side wall
309 and first mask layer 304a ion implanting is carried out to Semiconductor substrate 200 for mask, in the quasiconductor of grid layer 303a both sides
Source region 310a and drain region 310b are formed in substrate 300.
While the second mask layer 305a is removed, second photoresist layer 308 is removed；The removal second is covered
The technique of film layer 305a and the second photoresist layer 308 is wet clean process, can thoroughly remove the second mask layer 305a and the
Two photoresist layers 308, can't cause to damage to grid layer 303a；After the second mask layer 305a is removed, described the
One mask layer 304a is used for as mask during formation side wall 309, protects the surface of the grid layer 303a injury-free, it is ensured that
The pattern of the grid layer 303a is good, accurate size.
The side wall 309 is used to define the position of source region 310a and drain region 310b, and grid layer is protected in subsequent technique
The side wall of 303a or metal gate；The material of the side wall 309 is the combination of silicon oxide, silicon nitride or silicon oxide and silicon nitride；Institute
The formation process for stating side wall 309 is depositing operation, and is covered using being etched back to technique and expose first after the depositing operation
Film layer 304a surface；Therefore, depending on the thickness of the first mask layer 304a is needed according to etching technics, it is to avoid described time quarter
In etching technique, the first mask layer 304a is removed.
In the present embodiment, when grid layer 303a is formed, the stop-layer 301 is retained, therefore is forming the source region
During 310a and drain region 310b, the stop-layer 301 can also be used to protect Semiconductor substrate 300 from the damage of ion implantation technology
Wound, it is ensured that the stable performance of transistor.
Fig. 9 is refer to, after source region 310a and drain region 310b is formed, in the surface shape of the Semiconductor substrate 300
Into dielectric layer 311, the surface of the dielectric layer 311 and the first mask layer 304a（As shown in Figure 8）Surface flush；It is situated between being formed
After matter layer 311, the first mask layer 304a and grid layer 303a is removed（As shown in Figure 8）, to form opening（It is not shown）；
Metal gate 312 is formed in the opening.
Because the transistor formed needed for the present embodiment is the transistor with high-K gate dielectric layer and metal gate layers, because
This needs substitutes the grid layer 303a of the polycrystalline silicon material with metal gate 312.
The material of the dielectric layer 311 is silicon oxide, and the formation process of the dielectric layer 311 is：In the stop-layer
301st, the mask layer 304a surfaces silicon oxide film of side wall 309 and first；Using glossing, it is preferred that chemical machinery is thrown
Light technique removes the silicon oxide film higher than the first mask layer 304a surfaces, forms dielectric layer 311；First mask layer 304
Material be between silicon nitride, with silicon oxide have selectivity, can be in the glossing, as the stopping of glossing
Position.
The technique of the removal first mask layer 304a and grid layer 303a is etching technics, it is preferred that wet etching work
Skill；The material of the metal gate 312 is copper, tungsten, aluminum or silver, and the formation process of the metal gate is depositing operation, described heavy
Technique is polished after product technique, till dielectric layer 311 is exposed.
In the present embodiment, in the sidewall surfaces of first mask layer protective layer, the material of the protective layer and the are formed
Two mask layers are identical；Because second mask layer is used as the mask of etching grid thin film, therefore in the etching technics, institute
Stating protective layer can protect first mask layer not to be thinned in the technique of etching grid thin film；It is described can be conformal
One mask layer is in the grid layer that subsequent etching is formed, it is to avoid the grid layer size reduction for being formed, therefore makes formed grid
The size of pole layer meets design standard, makes the characteristic size of the grid layer accurate and size is easily controlled, the crystal for being formed
The characteristic size of pipe is accurate, it is ensured that semiconductor device has good stability.
In sum, the grid film surface has the first mask layer, and the first mask layer surface has second to cover
Film layer；Wherein, first mask layer is used as mask when being subsequently formed side wall, and second mask layer is thin as etching grid
The mask of film；Protective layer, and the material of the protective layer and the second mask layer are formed in the sidewall surfaces of first mask layer
It is identical；Because second mask layer is used as the mask of etching grid thin film, the technique of the etching grid thin film is for described
Second mask layer has relatively low etch rate, therefore the etching technics is relatively low to the etch rate of the protective layer；Institute
Stating protective layer can protect first mask layer not to be thinned in the technique of etching grid thin film, so as to ensure that etching after
It is continuous formed grid layer when, the grid layer for being formed will not because of the first mask layer thinning size reduction, institute's shape can be made
Into the size of grid layer meet design standard；Therefore, the characteristic size of the grid layer is accurately easily-controllable, makes formed crystal
The characteristic size standard of pipe is accurate, and the stable performance of the semiconductor device for being formed is good.
Further, the formation process of the protective layer be plasma treatment process, the gas of the plasma treatment process
Body is oxygen；In the plasma treatment process, oxygen is dissociated into as plasma, and the regulation for passing through technological parameter,
Oxygen gas plasma is set to carry sufficiently high energy；Because the material of the first mask layer is silicon nitride, the oxygen plasma is made
The energy that body is carried can destroy the chemical bond of silicon nitride, in the plasma-treating technology, first mask layer
Sidewall surfaces can produce silicon ion and Nitrogen ion；Then, oxonium ion substitutes Nitrogen ion and constitutes silicon oxide with the silicon ion
Material, and the Nitrogen ion for being substituted is pulled away with the air-flow in technical process.And, the plasma treatment process can make
The oxygen gas plasma for being injected accumulates in the sidewall surfaces of first mask layer, it is easier in making oxonium ion and silicon nitride
Silicon ion generates silicon oxide, meanwhile, make formed silicon oxide thickness thin, i.e. the thickness of thin of protective layer, follow-up institute will not be increased
The size of the grid layer of formation, makes the accurate size of formed grid layer.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variations and modification that above example is made, belong to technical solution of the present invention
Protection domain.
Claims (11)
1. a kind of forming method of semiconductor structure, it is characterised in that include：
Semiconductor substrate is provided, the semiconductor substrate surface has stop-layer, and the stopping layer surface having grid thin film, institute
State grid thin film part surface have the first mask layer, the first mask layer surface have the second mask layer, described first
The material of mask layer is silicon oxide for the material of silicon nitride, second mask layer and stop-layer；
Protective layer is formed in the sidewall surfaces of first mask layer, the material of the protective layer is silicon oxide, the protective layer
Formation process be plasma treatment；
After the protective layer is formed, grid thin film described in the second mask layer as mask etching, to exposing stop-layer table
Till face, grid layer is formed.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the plasma treatment process includes：
Millitorr~100 millitorr of pressure 2, plasma dissociation power is 100 watts~1500 watts, and 0~50V of bias voltage, gas includes O2,
1 standard milliliters of total gas flow rate/minute~1000 standard milliliters/minute, 5 seconds~200 seconds response time.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of the protective layer is 1 angstrom~
100 angstroms.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include：Forming the grid layer
Afterwards, second mask layer is removed, and the semiconductor substrate surface in the grid layer and the first mask layer both sides forms side
Wall.
5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that also include：With the side wall and first
Mask layer carries out ion implanting for mask to Semiconductor substrate, and source region and leakage are formed in the Semiconductor substrate of grid layer both sides
Area.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include：In the stopping layer surface
Form gate dielectric membrane；Grid thin film is formed on the gate dielectric membrane surface；Grid layer is formed the grid thin film is etched
When, the gate dielectric membrane is etched, form gate dielectric layer.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the material of the gate dielectric membrane is height
K dielectric materials.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that also include：In the gate dielectric membrane
Surface forms cover film, and the material of the cover film is tantalum nitride or titanium nitride；Grid are formed on the cover film surface
Very thin films；When the grid thin film formation grid layer is etched, the cover film is etched, form coating.
9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that also include：Forming the grid layer
Afterwards, dielectric layer is formed in the semiconductor substrate surface, the surface of the dielectric layer flushes with the surface of the first mask layer；
After forming dielectric layer, first mask layer and grid layer are removed, form opening；Metal gate is formed in the opening.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first mask layer and second is covered
The formation process of film layer includes：The first mask thin film is formed in the grid layer film surface；In the first mask thin film table
Face forms the second mask thin film；The first photoresist layer is formed in the second mask film surface；With first photoresist layer
For mask, the second mask thin film and the first mask thin film are etched, till grid thin film is exposed.
The forming method of 11. semiconductor structures as claimed in claim 1, it is characterised in that also include：Etching, the grid is thin
Before film, in the second mask layer surface the second photoresist layer is formed；It is with second photoresist layer and the second mask layer
Mask, etches the grid thin film, forms grid layer.
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| CN107731752B (en) * | 2016-08-12 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113327979B (en) * | 2020-02-28 | 2023-04-18 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
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