CN104022022A - Forming method of multigraph - Google Patents

Abstract

A method for forming multiple patterns, comprising: providing a material layer to be etched; forming a plurality of discrete first hard mask layers on the material layer to be etched; forming a first hard mask layer located around the first hard mask layer A side wall; forming a second side wall located around the first side wall, the second side wall is made of a different material from the first side wall; repeating the process of forming the first side wall and the second side wall Several times, forming a multi-layer spacer structure in which first sidewalls and second sidewalls are spaced apart around the first hard mask layer; removing the first hard mask layer and the second sidewall; The first sidewall is used as a mask to etch the material layer to be etched to form a target pattern. In the method for forming multiple patterns of the present invention, the line width of the target pattern is small, and a controllable number of target patterns can be realized without multiple hard mask transfers, and the process is simple.

Description

How to form multiple graphics

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming multiple patterns.

Background technique

With the continuous shrinking of the minimum line width and spacing of integrated circuit design, when the feature size of the exposure line is close to the theoretical resolution limit of the exposure system, the lithographic imaging will be severely distorted, resulting in a serious decline in the quality of the lithographic pattern. . In order to reduce the influence of the optical proximity effect, the industry has proposed a photolithographic resolution enhancement technology.

One of the technologies is the double exposure (Double Print) technology, which uses multiple exposure technology to obtain a smaller line width, but the process of the double exposure technology is complicated, the cost is high, and there is alignment between multiple exposures (Alignment )question.

Another technology is self-aligned double patterning (SADP: Self-aligned Double Patterning) technology, which is considered to be a powerful guarantee to fill the gap between immersion lithography and extreme ultraviolet lithography (EUV). Self-aligned double patterning technology forms an etching sacrificial layer on the material layer to be etched, forms sidewalls around the etching sacrificial layer, and after removing the etching sacrificial layer, uses the sidewalls as a mask to etch The material layer to be etched can obtain patterns with small feature sizes.

1 to 6 show a process flow of a self-aligned quadruple patterning (SAQP: Self-aligned Quadruple Patterning) technology based on the self-aligned double patterning technology in the prior art.

Please refer to FIG. 1 , a semiconductor substrate 100 is provided, the surface of the semiconductor substrate 100 has a material layer 101 to be etched; a sacrificial layer 102 is formed on the material layer 101 to be etched; A separate hard mask layer 103 ; forming a first spacer 104 around the hard mask layer 103 .

Referring to FIG. 2 , the hard mask layer 103 (refer to FIG. 1 ) is removed.

Please refer to FIG. 3 , using the first sidewall 104 as a mask to etch the sacrificial layer 102 (refer to FIG. 2 ) until the material layer 101 to be etched is exposed, forming a sacrificial pattern 105; One side wall 104 .

Referring to FIG. 4 , a second side wall 106 is formed around the sacrificial pattern 105 .

Referring to FIG. 5 , the sacrificial pattern 105 (refer to FIG. 4 ) is removed.

Referring to FIG. 6 , the material layer 101 to be etched (refer to FIG. 5 ) is etched using the second sidewall 106 as a mask to form a target pattern 107 , and the second sidewall 106 is removed.

In the above-mentioned self-aligned quadruple patterning technology, the hard mask layer 103 is first formed by photolithography, and then the material layer 101 to be etched is etched through two times of sidewall pattern transfer to form four times the number of hard mask layers 103 target graphics 107 . However, the number of target patterns formed by the above method is limited, and multiple hard mask transfers are required, resulting in complicated processes.

For other methods of forming multiple patterns, please refer to the US patent application publication number US2012/0085733A1.

Contents of the invention

The problem solved by the invention is that the process of forming small-sized multiple patterns in the prior art is complicated and costly.

In order to solve the above problems, the present invention provides a method for forming multiple patterns, including: providing a material layer to be etched; forming a plurality of discrete first hard mask layers on the material layer to be etched; A first sidewall around the first hard mask layer; forming a second sidewall around the first sidewall, the material of the second sidewall being different from that of the first sidewall; repeating the above to form the first sidewall The process of the sidewall and the second sidewall is performed several times, forming a multi-layer spacer structure in which the first sidewall and the second sidewall are spaced apart around the first hard mask layer; removing the first hard mask layer and the second sidewall; etching the material layer to be etched by using the first sidewall as a mask to form a target pattern.

Optionally, the material layer to be etched is a semiconductor layer, and the target pattern is used as a semiconductor fin.

Optionally, the outermost layer of the multilayer side wall structure is the first side wall.

Optionally, the number of times of repeating the process of forming the first sidewall and the second sidewall is 1-100.

Optionally, the method further includes forming a second hard mask layer on the material layer to be etched before forming the first hard mask layer on the material layer to be etched.

Optionally, the process of forming the first sidewall located around the first hard mask layer includes: forming a first sidewall material layer covering the first hard mask layer; etching back the first sidewall The wall material layer, the first side wall material layer located around the first hard mask layer constitutes the first side wall.

Optionally, the process of forming the first sidewall material layer is atomic layer deposition.

Optionally, the process of etching back the first sidewall material layer is dry etching.

Optionally, the width of the first sidewall ranges from 5 nm to 20 nm.

Optionally, the process of forming the second sidewall located around the first sidewall includes: forming a second sidewall material layer covering the first hard mask layer and the first sidewall; etching back The second side wall material layer, the second side wall material layer located around the first side wall constitutes the second side wall.

Optionally, the process of forming the second sidewall material layer is atomic layer deposition.

Optionally, the process of etching back the second sidewall material layer is dry etching.

Optionally, the width of the second sidewall ranges from 10 nm to 50 nm.

Optionally, further comprising: before removing the first hard mask layer and the second sidewall, grinding the first hard mask layer, the first sidewall and the second sidewall, removing part of the first hard mask layer, part of the first sidewall and part of the second sidewall.

Optionally, the etching selectivity ratio of the second sidewall to the first sidewall is greater than 100:1.

Optionally, the height of the first hard mask layer ranges from 20 nm to 100 nm.

Optionally, the material of the second sidewall is the same as that of the first hard mask layer.

Optionally, the processes of removing the first hard mask layer and removing the second spacer are completed in the same step.

Compared with the prior art, the present invention has the following advantages:

In the method for forming multiple patterns in the embodiment of the present invention, several discrete first hard mask layers are formed on the material layer to be etched, and first sidewalls are formed around the first hard mask layer, and forming a second sidewall around the first sidewall, and then repeating the above-mentioned process of forming the first sidewall and the second sidewall, so as to form spaced apart first sidewalls and second sidewalls around the first hard mask layer Multi-layer side wall structure. After removing the first hard mask layer and the second sidewall, the first sidewall forms a repeating pattern structure with intervals, and then uses the first sidewall as a mask to etch the to-be-etched Etch the material layer to form the target pattern. In the method for forming multiple patterns of the present invention, the width of the first sidewall and the second sidewall is determined by the thickness of the deposited sidewall material layer, so that a target pattern with a small line width can be obtained, which reduces the difficulty of photolithography; in addition, by controlling repetition The number of processes for forming the first sidewall and the second sidewall can control the number of subsequent first sidewalls used as a mask of the material layer to be etched, and a large number of controllable target patterns can be obtained; and compared with the prior art Compared with the traditional multi-pattern formation method, multiple hard mask transfers are not required, and multiple pattern transfers can be realized by one etching of the material layer to be etched, and the process is simple and the cost is low.

Further, in the method for forming multiple patterns in the embodiment of the present invention, the first sidewall material layer and the second sidewall material layer are formed by atomic layer deposition process, with good thickness controllability and good shape retention of the film . The sidewalls of the first sidewall and the second sidewall formed after etching are straight and evenly spaced, and the material layer to be etched is subsequently etched using the first sidewall as a mask, and the obtained target pattern The width and spacing are uniform and the shape is regular.

Further, in the method for forming multiple patterns in the embodiment of the present invention, the first mask layer, the first sidewall and the second sidewall are ground by a chemical mechanical polishing process to remove the first sidewall and the portion at the top of the second sidewall that is not steep enough, the sidewall of the target pattern formed by etching the material layer to be etched subsequently using the first sidewall as a mask is steep.

Description of drawings

1 to 6 are schematic cross-sectional structural diagrams of the formation process of self-aligned quadruple patterns in the prior art;

7 to 15 are schematic cross-sectional structure diagrams of the forming process of multiple patterns according to the embodiment of the present invention.

Detailed ways

It can be seen from the background art that the process of forming small-sized multiple patterns in the prior art is complicated and costly.

The inventors of the present invention have studied the formation methods of multiple patterns in the prior art, and found that the prior art mostly uses sidewall technology to obtain small-sized patterns, and multiple hard mask transfers are required to obtain multiple patterns. First form the first sidewall around the hard mask layer, transfer the first sidewall pattern to the sacrificial layer to form a sacrificial pattern, then form the second sidewall around the sacrificial pattern, and transfer the second sidewall to the material layer to be etched . Since the second sidewall is formed after the first sidewall is transferred to the sacrificial layer, multiple transfers of the hard mask are caused and the process is complicated.

Based on the above studies, the inventors of the present invention proposed a method for forming multiple patterns, by repeatedly forming the first sidewall and the second sidewall around the first hard mask layer, forming the first sidewall and the second sidewall In the spaced-apart multi-layer spacer structure, after the first hard mask layer and the second sidewall are removed, the material layer to be etched is etched using the first sidewall as a mask to form a target pattern. In the above-mentioned method for forming multiple patterns, the width of the first sidewall and the second sidewall is determined by the thickness of the deposited sidewall material layer, and a target pattern with a small line width can be obtained, which reduces the difficulty of photolithography; and the second sidewall is formed repeatedly by controlling The number of processes for one side wall and the second side wall can control the number of subsequent first side walls used as a mask of the material layer to be etched, and an unlimited number of multiple pattern transfers can be realized, and the process is simple.

Taking the formation process of semiconductor fins as an example, specific embodiments will be described in detail below with reference to the accompanying drawings, so that the above-mentioned purpose and advantages of the present invention will become clearer.

FIG. 7 to FIG. 15 are structural schematic diagrams of the process of forming multiple graphics in the embodiment of the present invention.

Referring to FIG. 7 , a material layer 200 to be etched is provided; a second hard mask layer 201 is formed on the material layer 200 to be etched.

In this embodiment, the material layer 200 to be etched is a semiconductor substrate. The semiconductor substrate may be a silicon substrate or a silicon-on-insulator substrate, and the semiconductor substrate may also be a germanium substrate, a silicon-germanium substrate, a gallium arsenide substrate, or a germanium-on-insulator substrate. In this embodiment, semiconductor fins with smaller dimensions are formed by etching the semiconductor substrate.

In other embodiments, the material layer to be etched can also be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, a low dielectric constant material layer, a high dielectric constant material layer, an amorphous carbon layer, and a metal layer. one or more of. After the material layer to be etched is formed on the semiconductor substrate, it is used to form multiple patterns with repeated structures.

A second hard mask layer 201 is formed on the material layer to be etched 200 , and the second hard mask layer 201 is used to protect the surface of the material layer to be etched 200 in subsequent processes and reduce damage. The material of the second hard mask layer 201 may be different from that of the subsequently formed first hard mask layer, first sidewall material layer and second sidewall material layer, so as to ensure During the process of layering, the first sidewall material layer and the second sidewall material layer, the etching rate of the second hard mask layer 201 is relatively small, which is beneficial to protect the material layer 200 to be etched. The process of forming the second hard mask layer 201 may be a chemical vapor deposition or physical vapor deposition process, or an oxide layer may be formed by oxidizing the surface of the material layer 200 to be etched to form the second hard mask layer 201 . The material of the second hard mask layer 201 may be silicon oxide, silicon nitride, silicon oxynitride, carbon, titanium nitride or tantalum nitride.

Referring to FIG. 8 , several discrete first hard mask layers 202 are formed on the second hard mask layer 201 .

Specifically, a first hard mask material layer (not shown) is formed on the second hard mask layer 201 by chemical vapor deposition, physical vapor deposition or atomic layer deposition; Form a patterned photoresist layer (not shown) by photolithography on the layer; use the patterned photoresist layer as a mask to etch the first hard mask material layer until the second hard mask is exposed A first hard mask layer 202 is formed on the surface of the film layer 201 . The process of forming the patterned photoresist layer by photolithography may adopt ultraviolet lithography, 193nm wavelength lithography or 193nm wavelength immersion lithography. The material of the first hard mask layer 202 may be silicon oxide, silicon nitride, silicon oxynitride, carbon, titanium nitride or tantalum nitride. In this embodiment, the material of the first hard mask layer 202 is silicon oxide, and the height of the first hard mask layer 202 ranges from 20 nm to 100 nm.

In this embodiment, conventional ultraviolet lithography is used in the formation process of the first hard mask layer 202 , and the formed first hard mask layer 202 has a relatively large size, for example, 5 μm˜10 μm. The subsequently formed semiconductor fins located on both sides of the first hard mask layer 202 can be used to form different circuit units.

Referring to FIG. 9 , a first spacer material layer 203 covering the first hard mask layer 202 is formed.

In this embodiment, the first sidewall material layer 203 is formed by atomic layer deposition process, and the first sidewall material layer 203 covers the sidewall and top surface of the first hard mask layer 202 . The atomic layer deposition process pulses gas-phase precursors into the reaction chamber alternately, chemically adsorbs on the deposition substrate and reacts to form a monolayer growth to form a deposited film with good thickness controllability and good shape retention. Therefore, a smaller thickness of the first sidewall material layer 203 can be obtained, and the shape of the first sidewall material layer 203 is consistent with that of the first hard mask layer 202 . In this embodiment, the material of the first sidewall material layer 203 is silicon nitride, and during the atomic layer deposition process, SiH ₂ Cl ₂ and NH ₃ are provided alternately, and the film is formed at a temperature of 450 degrees Celsius to 550 degrees Celsius For silicon nitride, the chamber pressure is 0.2-0.3 Torr. In other embodiments, the material of the first sidewall material layer 203 may also be silicon oxide, silicon oxynitride, carbon, titanium nitride or tantalum nitride.

In other embodiments, the first sidewall material layer may also be formed by chemical vapor deposition or physical vapor deposition.

Referring to FIG. 10 , the first spacer material layer 203 is etched back (refer to FIG. 9 ), and the first spacer material layer 203 located around the first hard mask layer 202 forms a first spacer 204 .

Specifically, the first sidewall material layer 203 is etched back by using a dry etching process. In this embodiment, the reactive ion etching process is used to etch back the first sidewall material layer 203. Since the reactive ion etching has better directionality, after the first sidewall material layer 203 is etched back, The first sidewall material layer 203 covering the top surface of the first hard mask layer 202 and the surface of the second hard mask layer 201 is removed, and the first sidewall material layer 203 located on the sidewall surface of the first hard mask layer 201 The sidewall material layer 203 remains to form the first sidewall 204 .

In this embodiment, the first sidewall material layer 203 is formed by an atomic layer deposition process, and its thickness can be precisely controlled by controlling deposition parameters. Therefore, the width of the first sidewall 204 formed by etching back the first sidewall material layer 203 can also be precisely controlled, which can ensure that the subsequent formation is located at the desired location while obtaining a line width smaller than that of traditional optical lithography. The plurality of first sidewalls 204 around the first hard mask layer 202 have the same width. Subsequently, using the first sidewall 204 as a mask, the semiconductor fins formed by etching the material layer 201 to be etched have a smaller size and the same width. In this embodiment, the width range of the first sidewall 204 is 5 nm˜20 nm.

Referring to FIG. 11 , a second spacer material layer 205 covering the first mask layer 202 and the first spacer 204 is formed.

In this embodiment, the second sidewall material layer 205 is formed by using an atomic layer deposition process, which is beneficial to control the thickness and shape of the second sidewall material layer 205 . The sidewall of the second sidewall formed by etching back the second sidewall material layer 205 subsequently has a steep sidewall and a controllable thickness, so that the finally formed multilayer sidewall structure located around the first hard mask layer 202 The distances between the first side walls 204 are the same, and the distances between the formed target patterns are the same. The material of the second sidewall material layer 205 can be silicon oxide, silicon nitride, silicon oxynitride, carbon, titanium nitride or tantalum nitride, and the second sidewall material layer 205 and the first sidewall material layer The materials of the material layer 203 (refer to FIG. 9 ) are different to ensure a higher etching selectivity ratio for the first sidewall 204 and the second sidewall formed subsequently. Materials of the second sidewall material layer 205 and the first hard mask layer 202 may be the same or different. In this embodiment, the material of the second sidewall material layer 205 is the same as that of the first hard mask layer 202 , both are silicon oxide, and can be removed in the same process step in subsequent processes, and the process is simple.

In other embodiments, the second sidewall material layer may also be formed by chemical vapor deposition or physical vapor deposition.

Referring to FIG. 12 , the second sidewall material layer 205 is etched back (refer to FIG. 11 ), and the second sidewall material layer 205 located around the first sidewall 204 forms a second sidewall 206 .

Specifically, the second sidewall material layer 205 is etched back by using a dry etching process. In this embodiment, the second sidewall material layer 205 is etched back by using a reactive ion etching process. Since the reactive ion etching has better directionality, after the second sidewall material layer 205 is etched back, The second spacer material layer 205 covering the top surface of the first hard mask layer 202, the top surface of the first spacer 204 and the surface of the second hard mask layer 201 is removed, and is located on the first side The second sidewall material layer 205 remains on the sidewall surface of the wall 204 to form the second sidewall 206 . In this embodiment, the width of the second side wall 206 ranges from 10 nm to 50 nm.

Since the second sidewall 206 is formed by etching back the second sidewall material layer 205, and the material of the second sidewall material layer 205 is different from that of the first sidewall 204, so the The material of the second sidewall 206 is different from that of the first sidewall 204 and has etching selectivity. In this embodiment, the etching selectivity ratio of the second sidewall 206 to the first sidewall 204 is greater than 100:1, so as to ensure that the second sidewall 206 is removed in the subsequent process, all The damage to the first side wall 204 is relatively small.

Please refer to FIG. 13 , repeat the process of forming the first sidewall 204 and the second sidewall 206 several times, and form the first sidewall 204 and the second sidewall 206 spaced apart around the first hard mask layer 202. Multi-layer side wall structure.

By controlling the times of repeatedly forming the first spacer 204 and the second spacer 206 , the number of patterns subsequently formed around the first hard mask layer 202 can be controlled. After removing the first hard mask layer 202 and the second hard mask layer 206, the material layer 200 to be etched is etched by using a plurality of the first hard mask layers 204 as a mask to achieve multiple Graphic transfer, simple process. It should be noted that the number of repeating processes for forming the first sidewall 204 and the second sidewall 206 is not limited and is determined according to the number of multiple patterns to be formed. For example, the number of repetitions may be 1-100.

In this embodiment, after repeating the process of forming the first sidewall 204 and the second sidewall 206 several times, the outermost layer of the multilayer sidewall structure is the first sidewall 204 . Since only the first sidewall 204 is used as an etching mask and the second sidewall 206 is removed, making the first sidewall 204 at the outermost layer of the multi-layer sidewall can avoid redundant process steps and save costs.

Please refer to FIG. 14 , remove the first hard mask layer 202 and the second spacer 206

In this embodiment, the first hard mask layer 202 and the second sidewall 206 are made of the same material, and the processes of removing the first hard mask layer 202 and the second sidewall 206 are performed in the same step. Finished, the process is simple. The process of removing the first hard mask layer 202 and the second sidewall 206 may be dry etching or wet etching. During the etching process, due to the surface of the material layer 200 to be etched With the second hard mask layer 201 , the damage to the material layer 200 to be etched is reduced.

It should be noted that, in this embodiment, before removing the first hard mask layer 202 and the second sidewall 206, the first hard mask layer 202, the first For the side wall 204 and the second side wall 206 , the part of the top of the first side wall 204 and the second side wall 206 that is not steep enough is removed. Subsequent etching of the to-be-etched material layer 200 by using the first sidewall 204 with a steep sidewall as a mask is beneficial to improving the morphology of the formed semiconductor fin and making the sidewall of the semiconductor fin steep.

In another embodiment, the first hard mask layer and the second spacer are made of different materials, and the processes of removing the first hard mask layer and removing the second spacer are performed separately.

Referring to FIG. 15 , the material layer 200 to be etched is etched using the first sidewall 204 (refer to FIG. 14 ) as a mask to form a target pattern 207 .

In this embodiment, the second hard mask layer 201 (refer to FIG. 14 ) is formed on the surface of the material layer 200 to be etched. Therefore, dry etching is used to etch the first sidewall 204 as a mask. The second hard mask layer 201 and the material layer 200 to be etched. After etching, the first sidewall 204 is removed, and the remaining second hard mask layer 201 forms a third hard mask layer 208, and part of the material layer 200 to be etched forms a target pattern 207. The third hard mask layer The film layer 208 is located on the top surface of the target pattern 207 . In this embodiment, the material layer 200 to be etched is a semiconductor substrate, and the target pattern 207 is used as a semiconductor fin, and the height of the formed semiconductor fin can be controlled by controlling the etching depth of the semiconductor substrate. Since there are multiple first hard mask layers 204, multiple target patterns 207 are formed, so multiple pattern transfers are realized and the process is simple.

It should be noted that, after etching the material layer 200 to be etched to form the target pattern 207 by using the first sidewall 204 as a mask, since the first sidewall 204 is formed on the first hard mask layer 202 (Refer to FIG. 10 ), the target graphic 207 is generally a ring structure. Therefore, part of the target pattern 207 can be removed by photolithography and etching process, and the target pattern 207 can be cut to obtain a discrete bar-shaped pattern structure.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can utilize the methods and techniques disclosed above to analyze the technical aspects of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the protection of the technical solution of the present invention. scope.

Claims (18)

1. A method for forming multiple graphics, comprising: providing a material layer to be etched; forming several discrete first hard mask layers on the material layer to be etched; forming a first spacer around the first hard mask layer; forming a second side wall around the first side wall, the second side wall being of a different material than the first side wall; Repeating the above-mentioned process of forming the first sidewall and the second sidewall several times, forming a multi-layer sidewall structure in which the first sidewall and the second sidewall are spaced apart around the first hard mask layer; removing the first hard mask layer and the second spacer; Etching the material layer to be etched by using the first sidewall as a mask to form a target pattern. 2. The method for forming multiple patterns according to claim 1, wherein the material layer to be etched is a semiconductor layer, and the target pattern is a semiconductor fin. 3. The method for forming multiple patterns according to claim 1, wherein the outermost layer of the multi-layer side wall structure is the first side wall. 4 . The method for forming multiple patterns according to claim 1 , wherein the number of times of repeating the process of forming the first sidewall and the second sidewall is 1-100. 5. The method for forming multiple patterns according to claim 1, further comprising forming a first hard mask layer on the material layer to be etched before forming a first hard mask layer on the material layer to be etched. Two hard mask layers. 6. The method for forming multiple patterns according to claim 1, wherein the process of forming a first spacer located around the first hard mask layer comprises: forming a spacer covering the first hard mask layer A first sidewall material layer; etching back the first sidewall material layer, and the first sidewall material layer located around the first hard mask layer constitutes a first sidewall. 7. The method for forming multiple patterns according to claim 6, wherein the process of forming the first sidewall material layer is atomic layer deposition. 8. The method for forming multiple patterns according to claim 6, wherein the process of etching back the first sidewall material layer is dry etching. 9 . The method for forming multiple patterns according to claim 6 , wherein the width of the first sidewall ranges from 5 nm to 20 nm. 10. The method for forming multiple patterns according to claim 1, wherein the process of forming the second sidewall located around the first sidewall comprises: forming a hard mask layer covering the first hard mask layer and the The second sidewall material layer of the first sidewall; etching back the second sidewall material layer, and the second sidewall material layer located around the first sidewall constitutes the second sidewall. 11. The method for forming multiple patterns according to claim 10, wherein the process of forming the second sidewall material layer is atomic layer deposition. 12 . The method for forming multiple patterns according to claim 10 , wherein the process of etching back the second sidewall material layer is dry etching. 13 . 13 . The method for forming multiple patterns according to claim 10 , wherein the width of the second sidewall ranges from 10 nm to 50 nm. 14 . 14. The method for forming multiple patterns according to claim 1, further comprising: before removing the first hard mask layer and the second sidewall, grinding the first hard mask layer , the first sidewall and the second sidewall, removing part of the first hard mask layer, part of the first sidewall and part of the second sidewall. 15 . The method for forming multiple patterns according to claim 1 , wherein the etching selection ratio of the second sidewall to the first sidewall is greater than 100:1. 16. The method for forming multiple patterns according to claim 1, wherein the height of the first hard mask layer ranges from 20 nm to 100 nm. 17. The method for forming multiple patterns according to claim 1, wherein the material of the second sidewall is the same as that of the first hard mask layer. 18. The method for forming multiple patterns according to claim 17, wherein the processes of removing the first hard mask layer and removing the second spacer are completed in the same step.