CN102446704B - Dual patterning method - Google Patents
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- CN102446704B CN102446704B CN 201010509399 CN201010509399A CN102446704B CN 102446704 B CN102446704 B CN 102446704B CN 201010509399 CN201010509399 CN 201010509399 CN 201010509399 A CN201010509399 A CN 201010509399A CN 102446704 B CN102446704 B CN 102446704B
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Abstract
The invention relates to a dual patterning method which comprises the following steps of: providing a substrate, and sequentially forming a first masking film layer and a second masking film layer on the substrate; carrying out anisotropic etching on the first masking film layer and the second masking film layer, and forming a first opening in the masking film layer and the second masking film layer, wherein the first opening exposes the surface of the substrate; carrying out partly side etching on the second masking film layer to form a second masking film pattern which exposes the first masking film layer positioned at the two sides of the second masking film layer; by using the second masking film pattern as a masking film, etching the thickness of the part of the first masking film layer till obtaining the first masking film layer with the first thickness; removing the second masking film pattern, and forming a third masking film layer on the surface of the substrate, wherein the part of the third masking film fills the opening; and by using the third masking film layer as the masking film, etching the first masking film till exposing the substrate. The dual patterning method provided by the invention has the advantages of avoiding the problem of non-uniform etching of the substrate and effectively improving the etching effect.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of double-patternization (double patterning) method.
Background technology
Semiconductor technology strides forward towards littler process node under the driving of Moore's Law constantly.Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, but the semiconductor manufacture difficulty also grows with each passing day.And photoetching technique is production technology the most key in the semiconductor fabrication process, along with the semiconductor technology node enters into 65 nanometers, 45 nanometers, even 32 lower nanometers, the ArF light source light lithography of existing 193nm can't satisfy the needs that semiconductor is made, and extreme ultraviolet light photoetching technique (EUV), multi-beam do not have the research focus that mask technique and nanometer embossing become photoetching candidate technologies of future generation.But above-mentioned photoetching candidate technologies of future generation still has inconvenience and defective, demands urgently further being improved.
When Moore's Law continues the step that extends forward irreversible the time, the double-pattern technology becomes the optimal selection of industry undoubtedly, the double-pattern technology only need be carried out very little change to existing photoetching infrastructure, just can fill up 45 nanometers effectively to 32 nanometers even the photoetching technique blank of minor node more.The principle of double-pattern technology resolves into the lower figure of discrete, the density of two covers with the highdensity circuitous pattern of a cover, then they is prepared on the wafer.Just disclosed a kind of double-pattern technology in the US Patent No. 7709396, the technological process of described double-pattern technology comprises as shown in Figures 1 to 4:
Please refer to Fig. 1, form first graph layer 101 that includes a plurality of flagpole patterns and equidistantly arrange at substrate 100, spacing and the wide sum of single flagpole pattern of described first graph layer, 101 each adjacent flagpole pattern are defined as pitch, and the zone between described flagpole pattern is first opening 107.
With reference to figure 2, afterwards, form side wall layer 103 at described substrate 100 and first graph layer 101, described side wall layer 103 evenly is formed at first graph layer, 101 both sides.
Then, the described side wall layer of anisotropic etching, form second graph layer 105 in the both sides of first graph layer, 101 each flagpole pattern (namely in first opening 107), described second graph layer 105 includes a plurality of sidewalls, and each oppose side wall is corresponding to a flagpole pattern of first graph layer 103.
Then, remove first graph layer; Like this, the position that former each flagpole pattern of first graph layer occupies has namely constituted second opening 109, and each second opening 109 all is positioned at 105 of pair of sidewalls.
Behind the above-mentioned process implementing, originally included two sidewalls and two openings (first opening and second opening) in the zone of each pitch correspondence, further, described sidewall can be used as the mask of etched substrate.Like this, can under the condition of not changing lithographic equipment, the pitch minimum value of first graph layer be broken through the restriction of photoetching resolution, thereby effectively improve the integrated level of chip.
Yet described double-pattern technology still has problems.The size and dimension influence of described first graph layer, 101 oppose side walls is very big.If described first graph layer, 101 thickness are too little, then the sidewall cross section of dry etching side wall layer 103 back formation is triangular in shape, and this can influence sidewall as the effect of substrate 100 etch mask; And if the thickness of described first graph layer 101 is excessive, be subject to the step covering power of side wall layer 103, and the sidewall cross-sectional width that dry etching side wall layer 103 backs form is difficult to accurate control, and this has just reduced the accuracy of sidewall as etch mask.
Summary of the invention
The problem that the present invention solves provides a kind of double-pattern method, improves patterned accuracy.
For addressing the above problem, the invention provides a kind of double-pattern method, comprising: substrate is provided, is formed with first mask layer and second mask layer on the described substrate successively; Described first mask layer of anisotropic etching and second mask layer form first opening in described first mask layer and second mask layer, described first opening exposes substrate surface; Described second mask layer of side direction partial etching forms second mask pattern, and described second mask pattern exposes first mask layer that is positioned at the second mask pattern both sides; Be mask with second mask pattern, etched portions first mask layer thickness is until first mask layer that keeps first thickness; Remove second mask pattern; Form the 3rd mask layer at substrate surface, the partially filled opening of described the 3rd mask layer, and first thickness＜described the 3rd mask layer thickness≤first mask layer thickness; Be mask with described the 3rd mask layer, etching first mask layer is until exposing substrate; Remove described the 3rd mask layer.
Compared with prior art, the present invention has the following advantages: first mask layer as the etched substrate mask has the square-section, and its thickness can accurately be controlled, this has improved the uniformity of first mask layer greatly, when etched substrate, first mask layer of described uniform thickness has been avoided the inhomogeneous problem of substrate etching, has effectively improved etching effect.
Description of drawings
Fig. 1 to Fig. 4 is the technological process of prior art double-pattern method.
Fig. 5 is the schematic flow sheet of double-pattern method of the present invention.
Fig. 6 to Figure 14 is the generalized section of substrate in each step of embodiment of double-pattern method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, in existing double-pattern metallization processes, the influence of the size and dimension of the first graph layer oppose side wall is very big.If the described first graph layer thickness is too little, then the sidewall cross section that forms after the dry etching side wall layer is triangular in shape, and this can influence sidewall as the effect of substrate etching mask; And if the thickness of described first graph layer is excessive, be subject to the step covering power of side wall layer, and the sidewall cross-sectional width that forms after the dry etching side wall layer is difficult to accurate control, and this has just reduced the accuracy of sidewall as etch mask.
At the problems referred to above, the present inventor provides a kind of double-pattern method, and as shown in Figure 5, described double-pattern method comprises:
Step S101 provides substrate, is formed with first mask layer and second mask layer on the described substrate successively.
Step S102, described first mask layer of anisotropic etching and second mask layer form first opening in described first mask layer and second mask layer, and described first opening exposes substrate surface.
Step S103, described second mask layer of side direction partial etching forms second mask pattern, and described second mask pattern exposes first mask layer that is positioned at the second mask pattern both sides.
Step S104 is mask with second mask pattern, and etched portions first mask layer thickness is until first mask layer that keeps first thickness.
Step S105 removes second mask pattern.
Step S106 forms the 3rd mask layer at substrate surface, the partially filled opening of described the 3rd mask layer, and first thickness＜described the 3rd mask layer thickness≤first mask layer thickness.
Step S107 is mask with described the 3rd mask layer, and etching first mask layer is until exposing substrate.
Step S108 removes described the 3rd mask layer.
Below in conjunction with accompanying drawing, describe the double-pattern method of the specific embodiment of the invention in detail.
As shown in Figure 6, provide substrate 601, described substrate 601 is silicon-based substrate, for example is n type silicon substrate, p-type silicon substrate or is the SOI substrate; Described substrate 601 also can be silicon, germanium, GaAs or silicon Germanium compound substrate; Described substrate 601 can also be the substrate that comprises the part of integrated circuit and other elements, or has the substrate of covering dielectric and metal film, specially illustrates at this, should too not limit protection scope of the present invention.
Adopt chemical vapor deposition, physical vapor deposition or other films to form technology and on described substrate 601, form first mask layer 603 and second mask layer 605 successively.In specific embodiment, described first mask layer 603 and second mask layer 605 comprise: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride, amorphous carbon or other are easy to film forming material.In actual applications, described first mask layer 603 and second mask layer 605 should have relatively large etching selection ratio.For example, when described substrate 601 was silicon, described first mask layer 603 adopted silica, and described second mask layer 605 adopts silicon nitride; Perhaps, when described substrate 601 was silica, described first mask layer 603 adopted silicon nitride, and described second mask layer 605 adopts polysilicon.
As shown in Figure 7, described first mask layer 603 of anisotropic etching and second mask layer 605, in described first mask layer 603 and second mask layer 605, form first figure, described first graphics package contains a plurality of first flagpole patterns 607,607 adjacent of first flagpole patterns are formed with first opening 609, and described first opening 609 exposes substrate 601 surfaces.
In specific embodiment, described anisotropic etching using plasma etching technics, described plasma etch process needs to form the photoresist layer (not shown) that has with the identical figure of first figure at described second mask layer 605 earlier, and described photoresist layer is namely as the mask of anisotropic etching first mask layer 603 and second mask layer 605.
As shown in Figure 8, described second mask layer 605 of side direction etching until removing described second mask layer 605 of part, makes the width of second mask layer, 605 first flagpole patterns reduce, form second mask pattern 604, thereby part first mask layer 603 under former second mask layer 605 is exposed.In specific embodiment, the width of second mask layer 605 after the side direction etching, namely the width of second mask pattern 604 can be identical with the width of first opening 609.The degree of depth of described second mask layer, 605 side direction etchings is 10 nanometer to 50 nanometers, and corresponding, the width of second mask layer, 605 first flagpole patterns reduces 10 nanometer to 50 nanometers.And first flagpole pattern of described second mask layer 605 reduces along its bilateral symmetry.
In specific embodiment, after second mask layer 605 and first mask layer 603 are by plasma etching, can select to keep the photoresist layer on described second mask layer 605 or remove described photoresist layer.If described photoresist layer is not removed before the side direction etching, be mask with described photoresist layer then, adopt isotropic dry etch technology or described second mask layer 605 of wet-etching technology partial etching, at this moment, the side direction etching only takes place in second mask layer 605, then remove described photoresist layer again, form second mask pattern 604; If described photoresist layer is removed before the side direction etching, then there is not etch mask on second mask layer 605, in the side direction etching processing, it also can be by vertical etching, described second mask layer, 605 first flagpole patterns should be less than the thickness of second mask layer 605, to guarantee that described second mask layer 605 can not removed fully after the side direction etching by the degree of depth of side direction etching.
Because first mask layer 603 and second mask layer 605 have bigger etching selection ratio, therefore, in described second mask layer, 605 side direction etchings, first mask layer 603 can't be etched, and namely still is first figure.
With reference to figure 9, be mask with second mask pattern 604, etched portions first mask layer 603 thickness are until first mask layer 603 that keeps first thickness.
By narration before as can be known, described first mask layer 603 and second mask layer 605 should have relatively large etching selection ratio, so described first mask layer 603 and second mask pattern 604 also should have relatively large etching selection ratio.The using plasma etching apparatus, select to the first mask layer etch rate is high that the second mask layer etch rate is low for use or the etch technological condition of etching second mask layer not substantially, etched portions first mask layer 603 thickness keep first mask layer 603 of first thickness.
Need to prove that described first thickness is less than first mask layer, 603 thickness, in actual applications, first thickness is decided on first mask layer, 603 thickness, and namely first mask layer, 603 thickness deduct the thickness that first thickness needs for the actual product etching.Preferred first mask layer, 603 thickness are 1/3～1/2 first mask layer 603 thickness.
With reference to Figure 10, remove second mask pattern 604, removing the process choice plasma etching of second mask pattern 604 removes or the wet etching removal, because second mask pattern 604 and first mask layer 603 have relatively large etching selection ratio, when removing second mask pattern 604, can not cause the damage of first mask layer 603.
And because the etching technics in step S104 before, make the top of design transfer to the first mask layer 603 of second mask pattern 604.Namely the section of first mask layer 603 is " type " type, and " 1 " of " type " type be positioned at the centre position of " " of " fall T " type, and the width of " 1 " is than little 10 nanometer to 100 nanometers of width of " ".The width and one of concrete " 1 " " width can decide with the figure that need form.
With reference to Figure 11, form the 3rd mask film 611 on substrate 601 surfaces, and described the 3rd mask film 611 covers described first mask layer 603.
Described the 3rd mask film 611 materials are that polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride, amorphous carbon or other are easy to film forming material.In actual applications, described first mask layer 603 should have relatively large etching selection ratio with described the 3rd mask film 611.Need to prove that the material of described the 3rd mask film 611 and second mask layer 605 can be the same or different.For example, described first mask layer 603 adopts silica, and when described second mask layer 605 adopted silicon nitride, described the 3rd mask layer 611 adopted amorphous carbon; Perhaps, described first mask layer 603 adopts silicon nitride, and when described second mask layer 605 adopted polysilicon, described the 3rd mask layer 611 adopted amorphous carbon.
The formation technology of described the 3rd mask film 611 is that chemical vapor deposition, physical vapor deposition or other films form technology.
With reference to Figure 12, described the 3rd mask film 611 of attenuate forms the 3rd mask layer 612, and first thickness＜described the 3rd mask layer 612 thickness≤first mask layer, 603 thickness.
The thickness of described the 3rd mask layer 612 is 20 nanometer to 300 nanometers.
Described reduction process can be for returning etching technics or CMP (Chemical Mechanical Polishing) process, because described first mask layer 603 should have relatively large etching selection ratio with described the 3rd mask film 611, select for use to the 3rd mask film 611 etching rates big and to first mask layer, 603 etching rates the low or etch technological condition of etching first mask layer 603 not substantially, described the 3rd mask film 611 of attenuate.
Also need to prove, be thinned to described the 3rd mask film 611 thickness greater than first thickness and less than first mask layer, 603 thickness, soon " 1 " of first mask layer 603 of " type " type is come out and is got final product.
With reference to Figure 13, adopt described the 3rd mask layer 612 to be mask, described first mask layer 603 is carried out etching until exposing substrate 601.
Described etching technics select for use to first mask layer, 603 etching rates big and to the 3rd mask layer 612 etching rates the low or etch technological condition of etching the 3rd mask layer 612 not substantially, etching exposes substrate 601.
In this step, each first flagpole pattern of first mask layer 603 is divided into two parts, and this makes that the width of first flagpole pattern is reduced.
With reference to Figure 14, remove described the 3rd mask layer 612, only keep first mask layer 603 on the substrate 601, like this, first mask layer 603 of original first figure is transformed to second graph, first mask layer 603 of described second graph is made up of a plurality of second flagpole patterns 615, and two adjacent 615 of second flagpole patterns are formed with first opening 609 or second opening 613.According to the difference of specific embodiment, described first opening 609 can have identical width or different width with second opening 613.In the preferred embodiment, described first opening 609 has identical width with second opening 613, and like this, a plurality of second flagpole patterns 615 that comprise in the described second graph can equidistantly be arranged on the substrate 601.Than first flagpole pattern, the width of described second flagpole pattern 615 reduces, and under the condition of not changing lithographic equipment, the pitch minimum value of first figure is broken through the restriction of photoetching resolution, thereby effectively improves the integrated level of chip.
Because described first mask layer 603 all has mask to cover when etching, therefore, the cross section of second flagpole pattern of described first mask layer 603 is rectangle, and thickness is comparatively even, and first mask layer 603 of described square-section can be used as the mask of subsequent etching substrate 601; In addition, described first mask layer 603 directly forms on substrate 601, need not to make side wall construction, and the thickness of described first mask layer 603 can accurately be controlled, and this has further improved the uniformity of first mask layer 603.When etched substrate 601, first mask layer 603 of described uniform thickness has been avoided the inhomogeneous problem of etching, has effectively improved etching effect.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (13)
1. a double-pattern method is characterized in that, comprising:
Substrate is provided, is formed with first mask layer and second mask layer on the described substrate successively;
Described first mask layer of anisotropic etching and second mask layer form first opening in described first mask layer and second mask layer, described first opening exposes substrate surface;
Described second mask layer of side direction partial etching forms second mask pattern, and described second mask pattern exposes first mask layer that is positioned at the second mask pattern both sides;
Be mask with second mask pattern, etched portions first mask layer thickness is until first mask layer that keeps first thickness, form first mask layer that section is " T " type, and the longitudinal section of " T " type " 1 " is rectangle, and " T " type " 1 " is positioned at the centre position of " T " type " ";
Remove second mask pattern;
Form the 3rd mask film at substrate surface, return described the 3rd mask film of etching, form the 3rd mask layer, the partially filled opening of described the 3rd mask layer, and first thickness＜described the 3rd mask layer thickness≤first mask layer thickness;
Be mask with described the 3rd mask layer, etching first mask layer is until exposing substrate;
Remove described the 3rd mask layer.
2. double-pattern method as claimed in claim 1, it is characterized in that, describedly form the 3rd mask layer at substrate surface, the partially filled opening of described the 3rd mask layer, and the processing step of first thickness＜described the 3rd mask layer thickness≤first mask layer thickness comprises: form the 3rd mask film at substrate surface, and described the 3rd mask film covers described first mask layer; Described the 3rd mask film of attenuate forms the 3rd mask layer, and first thickness＜described the 3rd mask layer thickness≤first mask layer thickness.
3. double-pattern method as claimed in claim 2 is characterized in that, described reduction process is plasma etching or chemico-mechanical polishing.
4. double-pattern method as claimed in claim 1 is characterized in that, adopts chemical vapor deposition or physical vapor deposition to form first mask layer and second mask layer successively on described substrate.
5. double-pattern method as claimed in claim 1 is characterized in that, described first mask material is polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
6. double-pattern method as claimed in claim 1 is characterized in that, described second mask material is polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
7. double-pattern method as claimed in claim 1 is characterized in that, the degree of depth of described second mask layer of described side direction partial etching is 10 nanometer to 50 nanometers.
8. double-pattern method as claimed in claim 1 is characterized in that, described second mask layer of described side direction partial etching comprises: adopt isotropic dry etch technology or described second mask layer of wet-etching technology partial etching.
9. double-pattern method as claimed in claim 1 is characterized in that, described the 3rd mask material is polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
10. double-pattern method as claimed in claim 1 is characterized in that, the thickness of described the 3rd mask layer is 20 nanometer to 300 nanometers.
11. double-pattern method as claimed in claim 1 is characterized in that, the width behind the described second mask layer side direction partial etching is identical with the width of first opening.
12. double-pattern method as claimed in claim 1 is characterized in that, described first mask layer adopts silica, and described second mask layer adopts silicon nitride, and described the 3rd mask layer adopts amorphous carbon.
13. double-pattern method as claimed in claim 1 is characterized in that, described first mask layer adopts silicon nitride, and described second mask layer adopts polysilicon, and described the 3rd mask layer adopts amorphous carbon.
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| CN103779228B (en) * | 2012-10-24 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | A kind of method improving the planarization of super junction deep groove epitaxial layer |
| CN103928325B (en) * | 2013-01-10 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Edge epitaxial planarization method of super junction devices |
| KR102163187B1 (en) * | 2013-10-21 | 2020-10-08 | 삼성전자 주식회사 | Method for for fabricating semiconductor device and computing system for implementing the same |
| CN107403719B (en) * | 2016-05-20 | 2021-07-02 | 中芯国际集成电路制造（天津）有限公司 | Method for forming pattern in semiconductor device |
| CN112563409A (en) * | 2019-09-10 | 2021-03-26 | 浙江驰拓科技有限公司 | Magnetic memory based on spin orbit torque and preparation method thereof |
| CN113809047B (en) * | 2020-06-12 | 2024-02-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN114300588B (en) * | 2021-12-30 | 2023-09-26 | 广东省科学院半导体研究所 | Method for preparing nano pattern substrate |
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