CN103715068A - Forming method of semiconductor fine pattern - Google Patents
Forming method of semiconductor fine pattern Download PDFInfo
- Publication number
- CN103715068A CN103715068A CN201210378702.4A CN201210378702A CN103715068A CN 103715068 A CN103715068 A CN 103715068A CN 201210378702 A CN201210378702 A CN 201210378702A CN 103715068 A CN103715068 A CN 103715068A
- Authority
- CN
- China
- Prior art keywords
- side wall
- layer
- fine pattern
- etching
- formation method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 49
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 238000005229 chemical vapour deposition Methods 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 238000001338 self-assembly Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 161
- 125000006850 spacer group Chemical group 0.000 description 24
- 238000000151 deposition Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to a forming method of a semiconductor fine pattern. The forming method comprises the following steps that: a semiconductor substrate is provided, wherein a to-be-etched material layer and a plurality of discrete sacrificial layers arranged at the surface of the to-be-etched material layer are arranged at the surface of the semiconductor substrate; first side walls are formed at the two sides of the sacrificial layers; the sacrificial layers are removed; second side walls are formed at the two sides of the first side walls and a graphical mask layer is formed by the first side walls and the second side walls; and the to-be-etched material layer is etched by using the graphical mask layer as the mask and a fine pattern is formed at the surface of the semiconductor substrate. With the forming method, the size and the space of the pattern can be adjusted conveniently.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor fine pattern.Background technology
Along with the minimum feature of integrated circuit (IC) design and constantly dwindling of spacing, when the characteristic size of exposure lines is during close to the theory resolution power of exposure system, will there is serious distortion in the imaging of silicon chip surface, thereby cause the degradation of litho pattern quality.In order to reduce the impact of optical proximity effect, industrial quarters has proposed photoetching resolution enhancing technology (RET), and the double-pattern technology (DPT) wherein receiving much concern is considered to fill up the powerful guarantee of wide gap between immersion lithography and EUV.The core concept of double-pattern technology is that the figure that needs are formed is divided into two kinds of figures, be respectively the first figure and second graph, the critical size of the first figure and second graph is respectively the twice of the figure that needs formation, then graphically form for the first time respectively the first figure, graphically form for the second time second graph, by the method for such Dual graphing, avoid occurring the too small optical proximity effect causing of adjacent pattern pitch-row.
At present, the fine pattern for being formed by line (line) alternately and interval (space) on substrate, generally adopts self-aligned double patterning case (SADP, Self-Aligned Double Patterning) technology.
The method that existing employing SADP technology forms fine pattern comprises the following steps, and below in conjunction with accompanying drawing, Fig. 1 to Fig. 5 describes.
Please refer to Fig. 1, deposition-etch material layer 20 in Semiconductor substrate 10.
Please refer to Fig. 2, on the surface of etching material layer 20, form successively sacrificial material layer (not shown) to be etched, sacrificial material layer to be etched described in etching, forms patterned sacrifice layer 30.
Please refer to Fig. 3, on patterned sacrifice layer 30 surfaces and the etching material layer 20 surface deposition side wall layers that manifest, and side wall layer described in anisotropic etching, in patterned sacrifice layer 30 both sides, form side walls 40, the live width that its width is fine pattern.Gap length between adjacent side wall 40 has defined the interval of fine pattern equally.
Please refer to Fig. 4, remove patterned sacrifice layer 30.
Please refer to Fig. 5, take side wall 40 as mask, etching material layer is carried out to etching, form fine pattern 21.
More self-aligned double patterning shape technology please refer to the american documentation literature that publication number is US20090146322A1.
In prior art because the gap between side wall has defined the interval between fine pattern, and this interval is by the width of graphical sacrifice layer 30 and the interval determination between adjacent side wall 40, and be subject to the impact of etching and depositing operation, in actual adjustment process, face very large difficulty.
Summary of the invention
The problem that the present invention solves is a kind of formation method that has proposed semiconductor fine pattern, and described method can be adjusted the critical size of fine pattern easily, comprises dimension of picture, the size of space.
For addressing the above problem, the present invention proposes a kind of formation method of semiconductor fine pattern, comprise: Semiconductor substrate is provided, described semiconductor substrate surface has the some discrete sacrifice layer of material layer to be etched and described material surface to be etched, and the spacing distance between described sacrifice layer equates; In sacrifice layer both sides, form the first side wall; Remove sacrifice layer; In the first side wall both sides, form the second side wall, described the first side wall and the second side wall form pattern mask layer; Take described pattern mask layer as mask etching material layer to be etched, at semiconductor substrate surface, form fine pattern.
Preferably, the material of described sacrifice layer is one or more in photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, chemical vapour deposition (CVD) thin dielectric film, metal level.
Preferably, the formation technique of described sacrifice layer is at least one in photoetching, plasma etching, wet etching, ashing, nano impression self assembly graphics art.
Preferably, the material of described the first side wall is photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, chemical vapour deposition (CVD) thin dielectric film, metal level.
Preferably, the material of described the first side wall is different from the material of sacrifice layer, has very high etching selection ratio between the two.
Preferably, the material of described the second side wall is photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, thin dielectric film, metal level.
Preferably, the formation technique of described the first side wall and the second side wall is coating, chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald.
Preferably, the technique of removing described sacrifice layer is wet etching, dry etching or ashing.
Preferably, the thickness of described the first side wall is 5nm ~ 20nm.
Preferably, the thickness of described the second side wall is 5nm ~ 50nm.
Preferably, by regulating the size of the fine pattern that the thickness adjustment of the second side wall forms.
Preferably, described in etching, the technique of material layer to be etched is plasma etching.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention, after the sacrifice layer both sides of material surface to be etched form the first side wall, removes described sacrifice layer; In the first side wall both sides that form, form the second side wall again, the second side wall of described the first side wall and sidewall forms pattern mask layer.Technical scheme of the present invention forms pattern mask layer in two steps, forms the first side wall and removes sacrifice layer afterwards, in material surface to be etched, forms uniform repetitive pattern; In described the first side wall both sides, form the second side wall again, form pattern mask layer, the spacing between described mask is identical.In the prior art, only utilize the first side wall as mask etching material layer to be etched, need the parameter of constantly adjusting etching technics and depositing operation just can reach the expectation width of etching or the thickness of deposition, in the process of repeatedly adjusting, need to adjust the thickness of the first side wall and the width of sacrifice layer simultaneously, and the width of adjusting sacrifice layer can make the groove depth-to-width ratio between each sacrifice layer change, thereby have influence on the deposition of the first side wall, so influence each other between the thickness of the width of sacrifice layer and the first side wall, so need to constantly circulate to adjust to the formation parameter of sacrifice layer and the first side wall and just can reach the requirement of design simultaneously, whole process is very complicated and loaded down with trivial details.In technical scheme of the present invention, because the formation of the second side wall and the forming process of sacrifice layer are irrelevant, so adjust between the size of sacrifice layer and the size of the second side wall, can not influence each other, in adjustment, determine under the formation technological parameter and size condition of sacrifice layer, can adjust separately the technological parameter that forms the second side wall, form the thickness of the second side wall that meets designing requirement, thereby adjust the spacing between pattern mask layer, be the spacing between adjacent patterns on material layer to be etched, saved processing step.
Further, owing to material layer to be etched being carried out in the process of etching, due to the inhomogeneities of plasma and the scattering process between plasma, can make in the process of etching, except the etching of vertical direction, also have in the horizontal direction certain damage, thereby the dimension of picture that makes finally to obtain is less than the size of mask, the pattern dimension finally obtaining is incurred loss, be less than the pattern dimension needing, can not meet the demand of design.And in prior art, the thickness that forms the first side wall is less, and described the first side wall of usining carries out in etching process material layer to be etched as mask layer, and described the first side wall can sustain damage, pattern changes, thereby affects the pattern of the material layer to be etched after etching.So in technical scheme of the present invention, in the first side wall both sides, form the second side wall, make the size of the pattern mask layer that described the second side wall and the first side wall form be greater than the size of the etching pattern of the material layer to be etched that final needs obtain, and then make up the loss of pattern dimension in etching process, make it finally can meet the requirement designing.In addition, also can regulate easily by described the second side wall the size of final graphics.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is that prior art utilizes autoregistration double-pattern as the generalized section of the etching process of mask;
Fig. 6 to Figure 13 is the generalized section that embodiments of the invention form semiconductor fine pattern.
Embodiment
As described in the background art, in prior art, utilize double-pattern technology to form semiconductor fine pattern, be difficult to adjust the interval between adjacent pattern, it is equated.
Research finds, in prior art, pattern spacing is directly controlled by side wall thicknesses, make pattern spacing equate, just need to make the width of interval between side wall and sacrifice layer identical.The width that needs simultaneously to adjust side wall thicknesses and sacrifice layer in adjusting pattern spacing process, the width change of sacrifice layer can make the depth-to-width ratio at interval between adjacent side wall change, thereby affect the deposition of side wall, cause the change of side wall thicknesses, these two factors are interrelated, interact, cause the process of adjusting to become very complicated, need to carry out circulation adjustment repeatedly.
For addressing the above problem, inventor proposes a kind of formation method of semiconductor fine pattern, after the both sides of sacrifice layer form the first side wall, remove sacrifice layer, in the first side wall both sides, form the second side wall again, described the first side wall and the second side wall form pattern mask layer, take this mask layer as mask, at semiconductor substrate surface, form fine pattern.By adjusting the thickness of the second side wall, adjust the interval in fine pattern, do not need to adjust the width of sacrifice layer and the thickness of side wall, process is simple.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Described embodiment is only a part for embodiment of the present invention, rather than they are whole.When the embodiment of the present invention is described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.According to described embodiment, those of ordinary skill in the art is obtainable all other execution modes under the prerequisite without creative work, all belong to protection scope of the present invention.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described semiconductor substrate surface has the sacrificial material layer 300 of material layer 200 to be etched and material surface to be etched.
Concrete, the material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can be that body material can be also that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device forming in Semiconductor substrate 100, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
The material of described material layer to be etched 200 is wherein one or more such as silicon oxide layer, silicon nitride layer, polysilicon layer, low-K dielectric material, amorphous carbon, metal level.Described material layer to be etched 200 can be the material layer of monolayer material layer or multiple-level stack.
The material of described sacrificial material layer 300 is one or more in photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, thin dielectric film, metal level.The formation technique of sacrificial material layer 300 is chemical vapour deposition (CVD), physical vapour deposition (PVD) or coating.In the present embodiment, the material of described sacrificial material layer 300 is photoresist, and formation technique is coating processes.
Please refer to Fig. 7, sacrificial material layer 300(please refer to Fig. 6 described in etching), form some discrete sacrifice layers 301.
Concrete, in the present embodiment, because the material of described sacrificial material layer 300 is photoresist, so form the technique of discrete sacrifice layer 301, be photoetching.In other embodiments of the invention, adopt other materials such as anti-reflecting layer, organic film, amorphous carbon, thin dielectric film, metal level etc., can also adopt one or more techniques in photoetching, plasma etching, wet etching, ashing, nano impression, self assembly etc. to form.Interval CD between described sacrifice layer
space1be greater than the width C D of described sacrifice layer
core.
Please refer to Fig. 8, on surface and sacrifice layer 301 surfaces of described material layer 200 to be etched, form the first spacer material layer 400.
Concrete, the material of described the first spacer material layer 400 can be the materials such as photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, thin dielectric film or metal level.The material of described the first spacer material layer 400 is different from the material of sacrifice layer 301, and both have high selection ratio.The formation technique of described the first spacer material layer 400 can be coating, chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald.In the present embodiment, the material of the first spacer material layer 400 of employing is dielectric silica, and formation technique is atom layer deposition process, and the thickness of the first spacer material layer 400 of formation is 10nm.In other embodiments of the invention, the thickness range of described the first spacer material layer 400 is 5nm ~ 20nm.
Please refer to Fig. 9, adopt and please refer to Fig. 8 without the first spacer material layer 400(described in mask etching technique etching), at the sidewall of sacrifice layer 301, form the first side wall 401.
Concrete, described in described etching, the technique of the first spacer material layer 400 is plasma etch process, utilize the first spacer material layer 400 described in the vertical etching of plasma etch process, until remove the part first spacer material layer of material layer to be etched 200 surfaces and sacrifice layer 301 end faces, form the first side wall 401 that covers described sacrifice layer sidewall, the thickness of described the first side wall 401 is all 5nm ~ 20nm mutually with the thickness of the first spacer material layer 400.Distance between the first side wall of adjacent sacrifice layer both sides is CD
space2, form repeat patterns, CD
space2=CD
space1-2CD
sp1=CD
core.
Please refer to Figure 10, remove described sacrifice layer 301(and please refer to Fig. 9).
Concrete, in the present embodiment, adopt photoresist as sacrificial layer material, the present embodiment adopts cineration technics to remove described sacrifice layer 301.The reacting gas of described cineration technics is O2, by described oxygen gas plasma, and utilize described oxygen gas plasma and sacrifice layer 301 to react, form the main product such as volatile carbon monoxide, carbon dioxide, water, thereby remove described sacrifice layer 301.In other embodiments, the reacting gas of described cineration technics can also comprise N
2or H
2deng, described N
2or H
2be conducive to improve the ability of sacrificing photoresist layer and residual polymer of removing.In other embodiments of the invention, can also adopt the techniques such as wet etching, dry etching to remove described sacrifice layer 301.After removing sacrifice layer, described the first side wall 401 has formed measure-alike in sacrificial layer surface, the mask pattern that interval is equal.In prior art, directly utilize described the first side wall 401 as mask, material layer to be etched described in etching, forms fine pattern in material surface to be etched.The interval of described fine pattern is by CD
coreand CD
space2determine, and CD
space2=CD
space1-2CD
sp1, described CD
sp1be the thickness of the first side wall, CD
space1(as described in Figure 7) be the spacing distance between adjacent sacrifice layer.So, form repetitive pattern, must make CD
core=CD
space2, i.e. CD
core=CD
space1-2CD
sp1.In the formation technique actual, the parameter of etching technics and depositing operation need to constantly be adjusted, and just can reach and estimate etching width or deposit thickness.In fact, in this process, need to regulate according to the result of each flow, just can make final CD
core=CD
space1-2CD
sp1, need to adjust the width C D of sacrifice layer simultaneously
coreand the thickness C D of the first side wall
sp1.And for the sacrifice layer dimension of picture Pitch of the fixing one-period of sacrifice layer figure
original=CD
core+ CD
space1so, the width C D of sacrifice layer
corechange, can make CD
space1also change, CD
space1change and just to make the depth-to-width ratio of the groove between adjacent sacrifice layer change, described depth-to-width ratio changes and can affect the deposition of the first spacer material layer, thereby affects the thickness of the first spacer material layer.Due to sacrifice layer width C D
corethickness C D with the first side wall
sp1between influence each other, need again to regulate both sizes, so need to constantly repeat the parameter of sacrifice layer and side wall to adjust, repeatedly circulation could obtain rational technological parameter after regulating simultaneously, thereby obtain the dimension of picture needing, whole process is very complicated and difficult.
Please refer to Figure 11, on surface and first side wall 401 surfaces of described material layer 200 to be etched, form the second spacer material layer 500.
Concrete, the material of described the second spacer material layer 500 can be the materials such as photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, chemical vapour deposition (CVD) thin dielectric film or metal level.The formation technique of described the second spacer material layer 500 can be coating, chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald.In the present embodiment, the material of the second spacer material layer 500 of employing is silicon nitride, and formation technique is chemical vapour deposition (CVD).The thickness of described the second spacer material layer 500 is 5nm ~ 50nm.
Please refer to Figure 12, adopt and please refer to Figure 11 without the second spacer material layer 500(described in mask etching technique etching), at the sidewall of the first side wall 401, form the second side wall 501.
Concrete, described in described etching, the technique of the second spacer material layer 500 is plasma etch process, utilize the second spacer material layer 500 described in the vertical etching of plasma etch process, until remove the part second spacer material layer of material layer to be etched 200 surfaces and the first side wall 401 end faces, form the second side wall 501 that covers described sacrifice layer sidewall, the thickness of described the second side wall 501 is identical with the thickness of the second spacer material layer 500, is 5 ~ 50nm.The second side wall 501 of described the first side wall 401 and both sides forms pattern mask layer.Interval between described mask layer equates.
Please refer to Figure 13, the second side wall 501 of the first side wall 401 and both sides of usining forms pattern mask layers as mask, and material layer 200(to be etched is as shown in figure 12 described in etching), in Semiconductor substrate, form fine pattern 201.
Concrete, in the present embodiment, described in etching, the technique of material layer to be etched is plasma etching, in other embodiments of the invention, also can adopt other dry etch process to carry out etching to described layer to be etched.As shown in Figure 13, the size Pitch of the one-period of the fine pattern of described formation
final=CD
space3+ 2CD
sp2+ CD
sp1, CD wherein
space3for the distance between adjacent mask layer, the interval between fine pattern 201 namely, CD
sp2be the thickness of the second side wall.Again due to CD
core=CD
space3+ 2CD
sp2so, Pitchfinal=CD
core+ CD
sp1, and the size Pitch of the one-period of initial sacrifice layer
original=CD
core+ CD
space1, for the figure repeating, due to CD
space1=cD
core+ 2CD
sp1,so Pitch
original=CD
core+ CD
core+ 2CD
sp1=2CD
core+ 2CD
sp1.So Pitch
final=1/2Pitch
original, the density of the final fine pattern forming is 1/2 of initial sacrifice layer pattern density, pattern integrated level is improved.Due to CD
core=cD
space3+ 2CD
sp2, because the formation of the second side wall and the forming process of sacrifice layer are irrelevant, so do not changing CD
coresituation under, we can adjust separately the technological parameter that forms the second side wall, form the thickness C D of the second side wall that meets designing requirement
sp2thereby, adjust the spacing CD between pattern mask layer
space3, i.e. spacing between adjacent patterns on material layer to be etched.With in prior art, to adjust CD simultaneously
coreand CD
sp1the technological parameter that simultaneously adjust to form sacrifice layer is compared with the technological parameter of the first side wall, and the technological parameter that the present embodiment can be only forms the second side wall by adjustment forms the etching figure that meets designing requirement on material layer to be etched, has saved processing step.
In prior art, the thickness of the first side wall forming is less, and using described the first side wall, as mask layer, material layer to be etched is carried out in the process of etching, adopt the method for dry etching in etching process, to described the first side wall, to cause damage, its pattern is changed, thereby affect the pattern of the etching figure forming after etching material layer to be etched; And, in etching process, due to the inhomogeneities in plasma etch process and the scattering process between plasma, can make to treat etch layer and carry out in the process of etching, except the etching of vertical direction, also have in the horizontal direction certain damage, thereby the etching dimension of picture that makes finally to obtain is less than the size of the first side wall, the pattern dimension finally obtaining incurs loss, and is less than the pattern dimension needing, and can not meet the demand of design.So in the present embodiment, form certain thickness the second side wall, make the size of the pattern mask layer that described the second side wall and the first side wall form be greater than the size of the etching pattern that final needs obtain, and then make up the loss of pattern dimension in etching process, make it finally can meet the requirement designing.And by changing the thickness of the second side wall, thereby can simply regulate the size of mask pattern to regulate the finally size of the dimension of picture of formation.
Above-mentioned by the explanation of embodiment, should be able to make professional and technical personnel in the field understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can do not depart from the spirit and scope of the invention in the situation that to above-described embodiment do various changes according to described principle herein and modification is apparent.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (12)
1. a formation method for semiconductor fine pattern, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has material layer to be etched and is positioned at the some discrete sacrifice layer of described material surface to be etched, and the spacing distance between described sacrifice layer equates;
In sacrifice layer both sides, form the first side wall;
Remove sacrifice layer;
In the first side wall both sides, form the second side wall, described the first side wall and the second side wall form pattern mask layer;
Take described pattern mask layer as mask etching material layer to be etched, at semiconductor substrate surface, form fine pattern.
2. the formation method of semiconductor fine pattern according to claim 1, it is characterized in that, the material of described sacrifice layer is one or more in photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, chemical vapour deposition (CVD) thin dielectric film or metal.
3. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the formation technique of described sacrifice layer is one or more in photoetching, plasma etching, wet etching, ashing, nano impression self assembly graphics art.
4. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the material of described the first side wall is one or more in photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, thin dielectric film or metal level.
5. the formation method of semiconductor fine pattern according to claim 4, is characterized in that, the material of described the first side wall is different from the material of sacrifice layer.
6. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the material of described the second side wall is one or more in photoresist, bottom layer anti-reflection layer, organic film, amorphous carbon, thin dielectric film or metal level.
7. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the formation technique of described the first side wall and the second side wall is coating, chemical vapour deposition (CVD), physical vapour deposition (PVD) or ald.
8. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the technique of removing described sacrifice layer is wet etching, dry etching or ashing.
9. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the thickness of described the first side wall is 5nm ~ 20nm.
10. the formation method of semiconductor fine pattern according to claim 1, is characterized in that, the thickness of described the second side wall is 5nm ~ 50nm.
The formation method of 11. semiconductor fine patterns according to claim 1, is characterized in that, by regulating the size of the fine pattern that the thickness adjustment of the second side wall forms.
The formation method of 12. semiconductor fine patterns according to claim 1, is characterized in that, the technique of material layer to be etched is plasma etching described in etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210378702.4A CN103715068A (en) | 2012-09-29 | 2012-09-29 | Forming method of semiconductor fine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210378702.4A CN103715068A (en) | 2012-09-29 | 2012-09-29 | Forming method of semiconductor fine pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103715068A true CN103715068A (en) | 2014-04-09 |
Family
ID=50407946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210378702.4A Pending CN103715068A (en) | 2012-09-29 | 2012-09-29 | Forming method of semiconductor fine pattern |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103715068A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104528634A (en) * | 2014-12-16 | 2015-04-22 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN106206307A (en) * | 2015-05-05 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
| CN107403719A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造（天津）有限公司 | The method for forming figure in the semiconductor device |
| CN108292591A (en) * | 2015-09-24 | 2018-07-17 | 东京毅力科创株式会社 | The method for forming the etching mask for Subresolution underlay pattern |
| CN109559978A (en) * | 2017-09-27 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109860041A (en) * | 2018-12-28 | 2019-06-07 | 芯创智（北京）微电子有限公司 | A kind of integrated circuit precision graphic preparation method |
| CN109920730A (en) * | 2017-12-13 | 2019-06-21 | 联华电子股份有限公司 | A kind of patterning method |
| CN110379706A (en) * | 2019-07-17 | 2019-10-25 | 上海华力微电子有限公司 | A method of optimization NAND flash double exposure critical size |
| CN111640665A (en) * | 2019-03-01 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112735947A (en) * | 2019-10-28 | 2021-04-30 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN114924461A (en) * | 2022-06-21 | 2022-08-19 | 广州新锐光掩模科技有限公司 | A method for adjusting critical dimensions of photomask film growth |
| CN115295570A (en) * | 2022-09-26 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Method for manufacturing CMOS image sensor |
| CN116825628A (en) * | 2023-08-30 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Side wall forming method and semiconductor device |
| CN117174583A (en) * | 2023-11-02 | 2023-12-05 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429123B1 (en) * | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
| US20060276032A1 (en) * | 2004-12-28 | 2006-12-07 | Hideki Arakawa | Fabrication method for a semiconductor device |
| CN101840890A (en) * | 2008-12-30 | 2010-09-22 | 东部高科股份有限公司 | Method for fabricating flash memory device |
-
2012
- 2012-09-29 CN CN201210378702.4A patent/CN103715068A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429123B1 (en) * | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
| US20060276032A1 (en) * | 2004-12-28 | 2006-12-07 | Hideki Arakawa | Fabrication method for a semiconductor device |
| CN101840890A (en) * | 2008-12-30 | 2010-09-22 | 东部高科股份有限公司 | Method for fabricating flash memory device |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104528634B (en) * | 2014-12-16 | 2017-01-18 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN104528634A (en) * | 2014-12-16 | 2015-04-22 | 南京工业大学 | Side wall forming manufacturing method of nano structure |
| CN106206307A (en) * | 2015-05-05 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN106206307B (en) * | 2015-05-05 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108292591A (en) * | 2015-09-24 | 2018-07-17 | 东京毅力科创株式会社 | The method for forming the etching mask for Subresolution underlay pattern |
| CN106910677B (en) * | 2015-12-23 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Patterning method for manufacturing semiconductor device, and semiconductor device manufacturing method |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
| CN107403719A (en) * | 2016-05-20 | 2017-11-28 | 中芯国际集成电路制造（天津）有限公司 | The method for forming figure in the semiconductor device |
| CN109559978B (en) * | 2017-09-27 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109559978A (en) * | 2017-09-27 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109920730A (en) * | 2017-12-13 | 2019-06-21 | 联华电子股份有限公司 | A kind of patterning method |
| CN109920730B (en) * | 2017-12-13 | 2021-04-20 | 联华电子股份有限公司 | a patterning method |
| CN109860041A (en) * | 2018-12-28 | 2019-06-07 | 芯创智（北京）微电子有限公司 | A kind of integrated circuit precision graphic preparation method |
| CN111640665B (en) * | 2019-03-01 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111640665A (en) * | 2019-03-01 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110379706B (en) * | 2019-07-17 | 2021-08-13 | 上海华力微电子有限公司 | Method for optimizing double exposure key size of NAND flash |
| US10943784B2 (en) | 2019-07-17 | 2021-03-09 | Shanghai Huali Microelectronics Corporation | Method for optimizing a critical dimension for double patterning for NAND flash |
| CN110379706A (en) * | 2019-07-17 | 2019-10-25 | 上海华力微电子有限公司 | A method of optimization NAND flash double exposure critical size |
| CN112735947A (en) * | 2019-10-28 | 2021-04-30 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
| CN114924461B (en) * | 2022-06-21 | 2024-10-22 | 广州新锐光掩模科技有限公司 | A method for adjusting critical dimensions of photomask film growth |
| CN114924461A (en) * | 2022-06-21 | 2022-08-19 | 广州新锐光掩模科技有限公司 | A method for adjusting critical dimensions of photomask film growth |
| CN115295570A (en) * | 2022-09-26 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Method for manufacturing CMOS image sensor |
| CN116825628A (en) * | 2023-08-30 | 2023-09-29 | 粤芯半导体技术股份有限公司 | Side wall forming method and semiconductor device |
| CN117174583B (en) * | 2023-11-02 | 2024-01-30 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN117174583A (en) * | 2023-11-02 | 2023-12-05 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103715068A (en) | Forming method of semiconductor fine pattern | |
| CN103839781B (en) | The formation method of semiconductor fine pattern | |
| CN104733291B (en) | Method for patterning integrated circuits | |
| TWI409852B (en) | Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning | |
| US9536987B2 (en) | Line-end cutting method for fin structures of FinFETs formed by double patterning technology | |
| CN103367258B (en) | Semiconductor circuit structure and manufacturing process thereof | |
| US20110294075A1 (en) | Patterning method | |
| CN108206131B (en) | Semiconductor structure and method for forming semiconductor structure | |
| KR20090090327A (en) | A method of reducing the critical dimension of a semiconductor device and a partially manufactured semiconductor device having a reduced critical dimension | |
| CN102446703A (en) | Dual patterning method | |
| TWI815116B (en) | Method of manufacturing semiconductor structure | |
| CN102446704B (en) | Dual patterning method | |
| TW201923834A (en) | Method of forming semiconductor structure | |
| CN108573865B (en) | Semiconductor device and method of forming the same | |
| CN111986983B (en) | Semiconductor structure and forming method thereof | |
| KR20090089497A (en) | Manufacturing method of fine pattern of semiconductor device | |
| US11557480B2 (en) | Semiconductor structure and fabrication method thereof | |
| CN210607186U (en) | Semiconductor structure | |
| CN104124143B (en) | The forming method of gate lateral wall layer | |
| TWI688013B (en) | Semiconductor structure and method for preparing the same | |
| Dupuy et al. | Spectral analysis of sidewall roughness during resist-core self-aligned double patterning integration | |
| CN114446768A (en) | Method for forming semiconductor structure | |
| US12322597B2 (en) | Pitch scaling in microfabrication | |
| US12334344B2 (en) | Formation of an array of nanostructures | |
| CN104425223B (en) | Graphic method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140409 |
|
| RJ01 | Rejection of invention patent application after publication |