CN104009043B - Pixel structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a pixel structure, which includes a thin film transistor element. The thin film transistor element includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, a first connection electrode, a second connection electrode, a dielectric layer, a source electrode and a drain electrode. The oxide semiconductor layer has a channel region, and a first contact region and a second contact region are respectively located on two opposite sides of the channel region. The first connection electrode covers the upper surface of the first contact area, and the second connection electrode covers the upper surface of the second contact area, wherein the first connection electrode and the second connection electrode do not overlap with the gate insulating layer in a vertical projection direction. The source electrode is electrically connected to the first contact region of the oxide semiconductor layer through the first connection electrode, and the drain electrode is electrically connected to the second contact region of the oxide semiconductor layer through the second connection electrode.

Description

Pixel structure and manufacturing method thereof

technical field

The present invention relates to a pixel structure and a manufacturing method thereof, in particular to a pixel structure and a manufacturing method thereof using connecting electrodes to connect source/drain electrodes to an oxide semiconductor layer.

Background technique

A thin film transistor (thin film transistor, TFT) element is a semiconductor element widely used in display panels, such as liquid crystal display panels (liquid crystal display panels, LCD panels), organic light emitting diode displays (organic light emitting diode display panels, OLED display panel) and electronic paper (electronic paper, E-paper) and other display panels. The electron mobility (mobility) of the thin film transistor element directly affects the switching speed of the thin film transistor element, and thus has a great influence on the quality of the display image.

At present, the thin film transistor elements of the display panel can be mainly divided into amorphous silicon thin film transistor (a-Si TFT) elements, polysilicon thin film transistor (polysilicon TFT) elements and oxide semiconductor thin film elements according to the different semiconductor layer materials used. Transistor (oxide semiconductor TFT) components. Amorphous silicon thin-film transistors are limited by the use of amorphous silicon semiconductor materials, so their electron mobility is low (currently, the electron mobility of amorphous silicon thin-film transistors is within 1cm2/Vs), so they cannot meet the needs of the currently visible future. Demand for higher specification displays. Benefiting from the properties of polysilicon material, polysilicon thin film transistors have greatly improved electron mobility (the best electron mobility of polysilicon thin film transistors can reach about 100 cm2/Vs). However, the process of polysilicon thin film transistors is complicated (the cost is relatively increased), and there is a problem of poor crystallinity uniformity when applied to large-sized panels. Therefore, polysilicon thin film transistors are still mainly used in small-sized panels. Oxide semiconductor thin film transistor elements are oxide semiconductor materials that have emerged in recent years. These materials generally have an amorphous lattice structure, which does not have the problem of poor uniformity when applied to large-scale panels, and can Various methods are used to form films, such as sputtering, spin-on, and printing, so the process is more flexible than amorphous silicon thin film transistors. The electron mobility of an oxide semiconductor thin film transistor device can generally be more than 10 times higher than that of an amorphous silicon thin film transistor (the electron mobility of an oxide semiconductor thin film transistor is generally between 10cm2/Vs and 50cm2/Vs), and this level has It can meet the needs of the currently visible future high-specification display panels.

However, in an oxide semiconductor thin film transistor device, if the contact resistance between the source/drain and the oxide semiconductor layer is too large, the performance of the thin film transistor device will be reduced and its high electron mobility cannot be effectively utilized. It is necessary to reduce the contact resistance between the oxide semiconductor layer and the source electrode/drain electrode so that the oxide semiconductor thin film transistor device exhibits high electron mobility characteristics.

Contents of the invention

One of the objectives of the present invention is to provide a pixel structure and a manufacturing method thereof, so as to improve the device characteristics of the thin film transistor element of the pixel structure.

An embodiment of the present invention provides a pixel structure, including a substrate, a thin film transistor element, a first protection layer and a first pixel electrode. The thin film transistor element is arranged on the substrate, and the thin film transistor element includes an oxide semiconductor layer, a gate insulating layer, a gate, a first connection electrode, a second connection electrode, a dielectric layer, a source and a drain. The oxide semiconductor layer is disposed on the substrate, and the oxide semiconductor layer has a channel area, and a first contact area and a second contact area are respectively located at two opposite sides of the channel area. The gate insulating layer is disposed on the oxide semiconductor layer, and the gate insulating layer covers an upper surface of the channel region and exposes an upper surface of the first contact region and an upper surface of the second contact region. The gate is disposed on the gate insulating layer. The first connection electrode and the second connection electrode are respectively arranged on both sides of the gate insulating layer, the first connection electrode covers the upper surface of the first contact region and is in contact with the upper surface of the first contact region, and the second connection electrode covers the first contact region. The upper surface of the second contact region is in contact with the upper surface of the second contact region, wherein the first connection electrode and the second connection electrode do not overlap with the gate insulation layer in a vertical projection direction. The dielectric layer is disposed on the grid, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially exposing an upper surface of the first connection electrode, and a second contact hole at least partly An upper surface of the second connecting electrode is exposed. The source and the drain are disposed on the dielectric layer, wherein the source is electrically connected to the first connection electrode through the first contact hole, and the drain is electrically connected to the second connection electrode through the second contact hole. The first protection layer is disposed on the dielectric layer, wherein the first protection layer has a third contact hole at least partially exposing the drain. The first pixel electrode is disposed on the first protective layer, wherein the first pixel electrode is electrically connected to the drain of the thin film transistor element through the third contact hole.

Another embodiment of the present invention provides a method for fabricating a pixel structure, including the following steps. A substrate is provided, and a patterned oxide semiconductor layer is formed on the substrate, wherein the patterned oxide semiconductor layer includes an oxide semiconductor layer, and the oxide semiconductor layer has a channel region, a first contact region and a first contact region. The two contact areas are respectively located on two opposite sides of the channel area. An insulating layer and a first conductive layer are sequentially formed on the substrate and the patterned oxide semiconductor layer. A patterned masking layer is formed on the first conductive layer, wherein the patterned masking layer partially covers the first conductive layer. removing the first conductive layer exposed by the patterned masking layer to form a first patterned conductive layer, and removing the exposed insulating layer of the patterned masking layer to form a patterned insulating layer, wherein the patterned insulating layer includes a The gate insulating layer, the gate insulating layer covers an upper surface of the channel region and exposes an upper surface of the first contact region and an upper surface of the second contact region, and the first patterned conductive layer includes a gate located at the gate pole insulating layer. A second conductive layer is formed on the substrate exposed by the patterned masking layer, the upper surface of the first contact region and the upper surface of the second contact region of the oxide semiconductor layer. performing a lift-off process, simultaneously removing the patterned masking layer and the second conductive layer on the patterned masking layer to form a second patterned conductive layer, wherein the second patterned conductive layer includes a first connection electrode and a The second connection electrode is formed on the upper surface of the first contact region and the upper surface of the second contact region in a self-aligned manner, and the first connection electrode and the second connection electrode are not perpendicular to the gate insulating layer. overlapping in the projection direction. A dielectric layer is formed on the grid, the first connection electrode and the second connection electrode, wherein the dielectric layer has a first contact hole at least partially exposing an upper surface of the first connection electrode, and a second contact hole at least An upper surface of the second connecting electrode is partially exposed. A third patterned conductive layer is formed on the dielectric layer, wherein the third patterned conductive layer includes a source and a drain, the source is electrically connected to the first connection electrode through the first contact hole, and the drain is electrically connected to the first connection electrode through the first contact hole. The second contact hole is electrically connected with the second connection electrode. A first protective layer is formed on the dielectric layer, wherein the first protective layer has a third contact hole at least partially exposing the drain. A first pixel electrode is formed on the first protection layer.

Description of drawings

1 to 8 are schematic diagrams illustrating a method for manufacturing a pixel structure according to a first embodiment of the present invention;

FIG. 9 and FIG. 10 are schematic diagrams illustrating the fabrication of a pixel structure according to a second embodiment of the present invention;

FIG. 11 illustrates a schematic diagram of a pixel structure of a comparative embodiment of the present invention;

FIG. 12 is a graph showing the relationship between the gate voltage VG and the drain current ID of the thin film transistor element of the pixel structure of the comparative embodiment of the present invention;

FIG. 13 is a graph showing the relationship between the gate voltage VG and the drain current ID of the thin film transistor element of the pixel structure of the present invention;

Explanation of the accompanying drawings:

10 Substrate

10S Switching element area

10C storage capacitor area

10P pixel area

12 buffer layer

14 Patterned oxide semiconductor layer

14S oxide semiconductor layer

14C channel area

141 First Contact Zone

142 Second contact zone

14B Lower electrode of storage capacitor

16 insulation

161 First insulating film

162 Second insulating film

18 First conductive layer

20 patterned masking layer

201 The first shielding layer

202 second shielding layer

22 The first patterned conductive layer

24 Patterned insulating layer

GI gate insulating layer

CD Capacitor Dielectric Layer

14X upper surface

14Y upper surface

14Z upper surface

G grid

22T storage capacitor upper electrode

Cst storage capacitor element

26 Second conductive layer

28 Second patterned conductive layer

281 First connection electrode

282 Second connecting electrode

Z vertical projection direction

283 conductive patterns

30 dielectric layer

TH1 first contact hole

TH2 second contact hole

32 The third patterned conductive layer

S source

D drain

TFT Thin Film Transistor Components

34 First layer of protection

TH3 third contact hole

36 First pixel electrode

50 pixel structure

38 Second protective layer

38A opening

40 Show media layer

42 Second pixel electrode

44 display elements

60 pixel structure

70 pixel structure

A curve

A' curve

B-curve

B' curve

C curve

C' curve

D curve

D' curve

E-curve

E' curve

detailed description

In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition of the present invention and the desired effects .

Please refer to Figure 1 to Figure 8. 1 to 8 are schematic diagrams illustrating a method for fabricating a pixel structure according to a first embodiment of the present invention. As shown in FIG. 1 , a substrate 10 is provided first. The substrate 10 can be a transparent substrate, and it can be a rigid substrate or a flexible substrate such as a glass substrate, a quartz substrate or a plastic substrate, but not limited thereto. The substrate 10 may have a switch element region 10S, a storage capacitor region 10C and a pixel region 10P. Next, a buffer layer 12 can be optionally formed on the substrate 10 . The buffer layer 12 may have insulating properties, and its material may be an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto, and the material of the buffer layer 12 may also be an organic insulating material. In addition, the buffer layer 12 can be a single layer structure or a composite layer structure. Subsequently, a patterned oxide semiconductor layer 14 is formed on the substrate 10 , and if the buffer layer 12 exists, the patterned oxide semiconductor layer 14 is formed on the buffer layer 12 . The material of the patterned oxide semiconductor layer 14 may include, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (indium tin oxide, ITO), zinc oxide (zinc oxide, ZnO), indium oxide (indium oxide, InO), (indium tin zinc oxide, ITZO), gallium oxide (gallium oxide, GaO) or other suitable oxide semiconductor materials . The patterned oxide semiconductor layer 14 may have an amorphous structure, and it may be formed by, for example, sputtering, spin coating, printing or other suitable methods. The patterned oxide semiconductor layer 14 includes an oxide semiconductor layer 14S disposed in the switching element region 10S, wherein the oxide semiconductor layer 14S has a channel region 14C, and a first contact region 141 and a second contact region 142 respectively Located on two opposite sides of the channel area 14C. In this embodiment, the channel region 14C, the first contact region 141 and the second contact region 142 are located on the same plane, and both ends of the channel region 14C are structurally connected to the first contact region 141 and the second contact region 142 respectively. , that is, the channel region 14C, the first contact region 141 and the second contact region 142 are respectively part of the oxide semiconductor layer 14S. In addition, the patterned oxide semiconductor layer 14 may further include a storage capacitor bottom electrode 14B disposed in the storage capacitor region 10C of the substrate 10 .

As shown in FIG. 2 , an insulating layer 16 and a first conductive layer 18 are sequentially formed on the substrate 10 and the patterned oxide semiconductor layer 14 . The material of the insulating layer 16 can be an inorganic insulating material such as silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto. In this embodiment, the insulating layer 16 can be a composite insulating layer, which can include a first insulating film 161 and a second insulating film 162, wherein the first insulating film 161 is formed on the patterned oxide semiconductor layer 14 , and the second insulating film 162 is formed on the first insulating film 161 . The first insulating film 161 and the second insulating film 162 can be made of the same material, wherein the first insulating film 161 can be formed by a low-temperature process, thereby preventing the patterned oxide semiconductor layer 14 from being damaged by high temperature, and the second insulating film 162 It can be formed by using a high temperature process, thereby having better insulation properties and structural strength. In a variant embodiment, the insulating layer 16 can also be a single insulating layer. In addition, the material of the first conductive layer 18 may include transparent conductive materials, such as: metal oxide conductive materials (such as indium tin oxide), opaque conductive materials, such as: metals such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum /Molybdenum, alloys of the above metals or other suitable metals or alloys, but not limited thereto. The first conductive layer 18 can be a single layer structure or a composite layer structure.

As shown in FIG. 3 , a patterned masking layer 20 is then formed on the first conductive layer 18 to partially cover the first conductive layer 18 . The patterned masking layer 20 can be, for example, a photoresist layer, which can be patterned by an exposure and development process, but is not limited thereto. The patterned shielding layer 20 may include a first shielding layer 201 and a second shielding layer 202, wherein the first shielding layer 201 is located in the switching element region 10S of the substrate 10 and covers the channel corresponding to the patterned oxide semiconductor layer 14 The first conductive layer 18 above the area 14C, and the second shielding layer 202 is located in the storage capacitor area 10C of the substrate 10 and covers the first conductive layer 18 corresponding to the upper electrode 14B of the storage capacitor. In this embodiment, the size of the first shielding layer 201 is substantially equal to the size of the channel region 14C of the patterned oxide semiconductor layer 14, and the size of the second shielding layer 202 is slightly smaller than the size of the lower electrode 14B of the storage capacitor, but not This is the limit. For example, in a variant embodiment, the size of the second shielding layer 202 may be equal to the size of the lower electrode 14B of the storage capacitor. Subsequently, the first conductive layer 18 exposed by the patterned masking layer 20 is removed to form a first patterned conductive layer 22 , and the insulating layer 16 exposed by the patterned masking layer 20 is removed to form a patterned insulating layer 24 . The patterned insulating layer 24 includes a gate insulating layer GI and a capacitor dielectric layer CD, wherein the gate insulating layer GI is located in the switching element region 10S, and covers the upper surface 14X of the channel region 14C and exposes the first contact region 141 The upper surface 14Y of the second contact region 142 and the upper surface 14Z of the second contact region 142; the capacitor dielectric layer CD is located in the storage capacitor region 10C and partially covers the storage capacitor lower electrode 14B. In this embodiment, the gate insulating layer GI and the capacitor dielectric layer CD are formed by stacking the first insulating film 161 and the second insulating film 162 respectively, but it is not limited thereto. The first patterned conductive layer 22 includes a gate G and a storage capacitor upper electrode 22T, wherein the gate G is located in the switching element region 10S and on the gate insulating layer GI; the storage capacitor upper electrode 22T is located in the storage capacitor region 10C And located on the lower electrode 14B of the storage capacitor. The storage capacitor bottom electrode 14B, the storage capacitor top electrode 22T and the capacitor dielectric layer CD sandwiched between the storage capacitor bottom electrode 14B and the storage capacitor top electrode 22T form a storage capacitor element Cst. In addition, the first patterned conductive layer 22 may further include a gate line (not shown) electrically connected to the gate G, or other necessary wires such as common lines (not shown). In this embodiment, the first conductive layer 18 exposed by the patterned masking layer 20 is removed to form the first patterned conductive layer 22 and the insulating layer 16 exposed by the patterned masking layer 20 is removed to form a patterned insulating layer. Step 24 utilizes the patterned masking layer 20 as an etching mask and implements an etching process. For example, the etching process can be an anisotropic etching process such as a dry etching process, so the pattern of the gate G and the pattern of the gate insulating layer GI will be substantially equal, that is, the sidewall of the gate G and the gate insulating layer The sidewalls of the GI will be substantially flush, but not limited to.

As shown in FIG. 4, a mask is subsequently formed on the substrate 10 exposed by the patterned masking layer 20, on the upper surface 14Y of the first contact region 141 of the oxide semiconductor layer 14, and on the upper surface 14Z of the second contact region 142. The second conductive layer 26 . That is to say, on the upper surface 14Y of the first contact region 141 exposed by the first masking layer 201 and on the upper surface 14Z of the second contact region 142 , the area exposed by the second masking layer 202 The second conductive layer 26 is formed on a part of the upper surface of the lower electrode 14B of the storage capacitor and on the substrate 10 (or the buffer layer 12 ). The material of the second conductive layer 26 may include transparent conductive materials, such as: metal oxide conductive materials (such as indium tin oxide), opaque conductive materials, such as: metals such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum/molybdenum , alloys of the above metals or other suitable metals or alloys, but not limited thereto. The second conductive layer 26 can be a single layer structure or a composite layer structure. The thickness of the second conductive layer 26 can be adjusted according to different materials. For example, if the material of the second conductive layer 26 is metal such as molybdenum, its thickness can be substantially between 50 angstrom (angstrom) and 200 angstrom, but not limited thereto; if the second conductive layer 26 The material is transparent conductive material, such as indium tin oxide, and its thickness can be thicker than that of metal, such as greater than 200 angstroms, but not limited thereto.

As shown in FIG. 5 , a lift-off process is then performed to simultaneously remove the patterned masking layer 20 and the second conductive layer 26 on the patterned masking layer 20 to form a second patterned conductive layer 28 . The second patterned conductive layer 28 includes a first connection electrode 281 and a second connection electrode 282, which are respectively formed on the upper surface 14Y of the first contact region 141 and the second contact region in a self-aligned manner. 142 on the upper surface 14Z, and the first connection electrode 281 and the second connection electrode 282 do not overlap with the gate insulating layer GI in the vertical projection direction Z. To be precise, the sidewalls of the first connection electrode 281 and the sidewalls of the second connection electrode 282 can be substantially aligned with the sidewalls of the gate insulating layer GI respectively and completely cover the upper surface 14Y of the first contact region 141 respectively. and the upper surface 14Z of the second contact region 142 . In addition, the second patterned conductive layer 28 further includes a conductive pattern 283, which is disposed on at least one side (for example, both sides) of the capacitor dielectric layer CD and partially covers the lower electrode 14B of the storage capacitor, thereby reducing the number of lower electrodes of the storage capacitor. 14B resistor. When the material of the second conductive layer 26 is metal oxide such as indium tin oxide, the first connection electrode 281 and the second connection electrode 282 are metal oxide conductive electrodes such as indium oxide electrodes; when the material of the second conductive layer 26 When metal or alloy is selected, the first connection electrode 281 and the second connection electrode 282 are metal electrodes such as aluminum electrodes, titanium/aluminum/titanium electrodes, molybdenum electrodes or molybdenum/aluminum/molybdenum electrodes. It can be known from the above that since the first connection electrode 281 and the second connection electrode 282 are formed by removing the patterned masking layer 20 and the second conductive layer 26 on the patterned masking layer 20 simultaneously by using a lift-off process, The patterned masking layer 20 itself also has the function of defining the pattern and position of the gate G and the gate insulating layer GI. Therefore, the practice of this embodiment has the effect of self-alignment, that is, the gate G and the gate insulating layer GI and the relative positions of the first connection electrode 281 and the second connection electrode 282 are fixed, and it can be ensured that the first connection electrode 281 will completely cover the upper surface 14Y of the first contact region 141, and the second connection electrode 282 will completely cover the second connection electrode 282. The upper surface 14Z of the two contact regions 142 , and the first connecting electrode 281 and the second connecting electrode 282 do not overlap with the gate insulating layer GI or the gate G in the vertical projection direction Z.

As shown in FIG. 6 , the first connection electrode 281 , the second connection electrode 282 and the conductive pattern 283 are retained, and other unnecessary parts of the second patterned conductive layer 28 , such as on the substrate 10 or the buffer layer 12 , are removed. The second patterned conductive layer 28. Subsequently, a dielectric layer 30 is formed on the gate G, the first connection electrode 281 and the second connection electrode 282, and a first contact hole TH1 is formed in the dielectric layer 30 to at least partially expose the first connection electrode 281. The upper surface 281S and a second contact hole TH2 at least partially expose the upper surface 282S of the second connection electrode 282 . The dielectric layer 30 may have a planarized surface to facilitate the formation of subsequent film layers. The material of the dielectric layer 30 can be an organic dielectric material or an inorganic dielectric material, and the dielectric layer 30 can be a single-layer structure or a composite layer structure.

As shown in FIG. 7 , a third patterned conductive layer 32 is then formed on the dielectric layer 30 . The third patterned conductive layer 30 includes a source S and a drain D, wherein the source S contacts and is electrically connected to the first connection electrode 281 through the first contact hole TH1, and the drain D passes through the second contact hole TH2 Contact and electrically connect with the second connection electrode 282 to manufacture the thin film transistor element TFT of this embodiment. The material of the third patterned conductive layer 32 may include transparent conductive materials, such as: metal oxide conductive materials (such as indium tin oxide), opaque conductive materials, such as: metals such as aluminum, titanium/aluminum/titanium, molybdenum, molybdenum/aluminum /Molybdenum, alloys of the above metals or other suitable metals or alloys, but not limited thereto. In addition, the third patterned conductive layer 32 can be a single layer structure or a composite layer structure. In addition, the third patterned conductive layer 32 may further include a data line (not shown) electrically connected to the source S, or other necessary wires. Then a first protection layer 34 is formed on the dielectric layer 30 , wherein the first protection layer 34 has a third contact hole TH3 at least partially exposing the drain D. The first passivation layer 34 may have a planarized surface to facilitate the formation of subsequent film layers. The material of the first protective layer 34 can be an organic insulating material or an inorganic insulating material, and the first protective layer 34 can be a single-layer structure or a composite layer structure.

As shown in FIG. 8 , a first pixel electrode 36 is formed on the first protection layer 34 to form the pixel structure 50 of this embodiment, wherein the first pixel electrode 36 is located in the pixel region 10P and extends into the switching element region 10S to It is in contact with and electrically connected to the drain D of the thin film transistor element TFT through the third contact hole TH3. In the present embodiment, the pixel structure 50 is applied to an organic electroluminescent display panel, and therefore may further include the following steps. A second passivation layer 38 is formed on the first passivation layer 34 , wherein the second passivation layer 38 has an opening 38A located in the pixel region 10P and at least partially exposing the first pixel electrode 36 . The material of the second protective layer 38 can be an organic insulating material or an inorganic insulating material, and the second protective layer 38 can be a single-layer structure or a composite layer structure. After that, a display medium layer 40 is formed in the opening 38A of the second protection layer 38 , wherein the display medium layer 40 is an organic electroluminescence layer. Finally, a second pixel electrode 42 is formed on the display medium layer 40 . The first pixel electrode 36 and the second pixel electrode 42 can serve as an anode and a cathode respectively, and together with the display medium layer 40 form a display element 44 , wherein the display element 44 is an organic electroluminescence element such as an organic light emitting diode element. One of the first pixel electrode 36 and the second pixel electrode 42 is a penetrating electrode, while the other can be a reflective electrode or a penetrating electrode. For example, if the display element 44 is a top-emitting display element, the first pixel electrode 36 is a reflective electrode, and the second pixel electrode 42 is a penetrating electrode; if the display element 44 is a bottom-emission display element, the first pixel electrode 36 is a penetrating electrode, and the second pixel electrode 42 is a reflective electrode; if the display element 44 is a double-sided light emitting display element, the first pixel electrode 36 and the second pixel electrode 42 can both be penetrating electrodes. In addition, film layers such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer can be selectively formed between the first pixel electrode 36 and the second pixel electrode 42 as required.

The pixel structure 50 of this embodiment is not limited to be applied to organic electroluminescent display panels but can be applied to other types of self-luminous or non-self-luminous display panels, such as liquid crystal display panels, electrophoretic display panels, electrowetting display panel or other suitable display panels. If the pixel structure 50 is to be applied to other types of display panels, other corresponding solid or liquid film layers such as liquid crystal layer, electrophoretic layer or hydrophilic/hydrophobic mixed liquid can be selected. Wherein, when the display medium layer 40 is a non-luminous material or other self-luminous material, at least one of the second protective layer 38 and the second pixel electrode 42 may be selectively not provided.

The pixel structure and its manufacturing method of the present invention are not limited to the above-mentioned embodiments. The following will introduce the pixel structure and the manufacturing method of other preferred embodiments of the present invention in sequence, and in order to facilitate the comparison of the differences between the various embodiments and simplify the description, the same symbols are used in the following embodiments to mark the same Components, and mainly describe the differences between the embodiments, and will not repeat the repeated parts.

Please refer to Figure 9 and Figure 10. FIG. 9 and FIG. 10 are schematic diagrams illustrating the fabrication of the pixel structure according to the second embodiment of the present invention. Different from the first embodiment, in this embodiment, the sidewall of the gate G is retracted from the sidewall of the gate insulating layer GI. Please refer to FIG. 9 following FIG. 2. As shown in FIG. 9, in this embodiment, the steps of forming the first patterned conductive layer 22 and forming the patterned insulating layer 24 use the patterned masking layer 20 as an etching mask and use etc. A tropic etching process such as a wet etching process is implemented. Therefore, although both the pattern of the gate G and the gate insulating layer GI use the patterned masking layer 20 as an etching mask, the pattern of the gate G and the pattern of the gate insulating layer GI are different. That is to say, since the gate G is located on the gate insulating layer GI, the etching time of the gate G is longer than that of the gate insulating layer GI, so a part of the sidewall of the gate G will be etched on the gate insulating layer GI. The layer GI is etched away continuously, and the sidewall of the gate G shrinks back into the sidewall of the gate insulating layer GI after etching. Similarly, the sidewalls of the upper electrode 22T of the storage capacitor are also retracted into the sidewalls of the capacitor dielectric layer CD. Then, the steps disclosed in FIG. 4 to FIG. 8 are performed sequentially to form the pixel structure 60 of this embodiment, as shown in FIG. 10 . It is worth noting that since the first connection electrode 281 and the second connection electrode 282 are formed by simultaneously removing the patterned shielding layer 20 and the second conductive layer 26 on the patterned shielding layer 20 through a lift-off process, the gate G The retracted sidewalls can more effectively ensure that there will be no short circuit between the gate G and the first connecting electrode 281 /second connecting electrode 282 after the lifting process.

The method for making the pixel structure of the present invention has the following advantages:

1. The source S and the drain D are respectively in contact with the first contact region 141 and the second contact region 142 of the patterned oxide semiconductor layer 14 through the first connection electrode 281 and the second connection electrode 282, so it can be selected and patterned. The oxide semiconductor layer 14 has a better contact material to reduce the resistance value, thereby increasing the electron mobility of the thin film transistor device TFT.

2. Since the first connection electrode 281 and the second connection electrode 282 are formed by lifting process, they have self-alignment effect without generating alignment error, and the source S and drain D are respectively connected through the first connection electrode 281 The first contact region 141 and the second contact region 142 are in contact with the second connection electrode 282 and the patterned oxide semiconductor layer 14, so even if the first contact hole TH1 and the second contact hole TH2 produce a process shift, it will not be caused by The asymmetry of the contact position between the source S/drain D and the first contact region 141 and the second contact region 142 of the patterned oxide semiconductor layer 14 affects device characteristics.

3. Since the first contact hole TH1 and the second contact hole TH2 expose the first connecting electrode 281 and the second connecting electrode 282 instead of exposing the patterned oxide semiconductor layer 14, the patterned oxide semiconductor layer 14 will not The dielectric layer 30 is damaged during the etching process, and the material selection of the dielectric layer 30 is not limited by the etching selection ratio of the dielectric layer 30 to the patterned oxide semiconductor layer 14 and thus has great flexibility.

4. The manufacturing method of the present invention uses a three-layer patterned conductive layer (comprising the first patterned conductive layer 22, the second patterned conductive layer 28 and the third patterned conductive layer 32) compared to the conventional method. The method of two patterned conductive layers has greater design flexibility.

Please refer to Figure 11. FIG. 11 is a schematic diagram of a pixel structure of a comparative embodiment of the present invention. As shown in FIG. 11 , in the pixel structure 70 of this comparative embodiment, the first contact hole TH1 and the second contact hole TH2 directly expose the patterned oxide semiconductor layer 14, and the source S and the drain D respectively pass through the second A contact hole TH1 is in direct contact with the second contact hole TH2 and the first contact region 141 is in direct contact with the second contact region 142 . The pixel structure 70 of this comparative embodiment has the following disadvantages:

1. The source S/drain D are in direct contact with the patterned oxide semiconductor layer 14 , so the source S/drain D are in poor contact with the patterned oxide semiconductor layer 14 .

2. When etching the dielectric layer 30 to form the first contact hole TH1 and the second contact hole TH2, dry etching cannot be used, otherwise it will cause damage to the patterned oxide semiconductor layer 14, and wet etching is also used The choice of materials for the dielectric layer 30 is limited, for example, materials etched by hydrofluoric acid cannot be used.

3. When the positions of the first contact hole TH1 and the second contact hole TH2 are shifted due to process deviation, the source S/drain D will form an asymmetric structure corresponding to the gate G. For thin film transistor components Characteristics are very influential.

Please refer to FIG. 12 and FIG. 13 again. Fig. 12 shows the relationship between the gate voltage VG and the drain current ID of the thin film transistor element of the pixel structure of the comparative embodiment of the present invention, and Fig. 13 shows the gate voltage of the thin film transistor element of the pixel structure of the present invention VG vs. drain current ID plot. Figure 12 shows the relationship between gate voltage VG and drain current ID of three samples of thin film transistor elements of the same size in the comparative embodiment, wherein curve A is the result measured at drain voltage VD=0.1V of sample 1 , Curve A' is the result of sample 1 measured at drain voltage VD=10V, curve B is the result of sample 2 measured at drain voltage VD=0.1V, curve B' is sample 2 at drain voltage VD = 10V, the curve C is the measurement result of sample 3 at drain voltage VD=0.1V, and the curve C' is the measurement result of sample 3 at drain voltage VD=10V. As shown in Figure 12, it can be clearly seen from the curves A-C that even at the same drain voltage VD=0.1V, the relationship between the gate voltage VG and the drain current ID of the thin film transistor elements of samples 1-3 has obvious difference. Similarly, it can be clearly seen from the curve A'-C' that even at the same drain voltage VD=10V, the relationship between the gate voltage VG and the drain current ID of the thin film transistor elements of samples 1-3 has the same significant difference. In addition, the threshold voltage (threshold voltage) of the thin film transistor devices of samples 1-3 also has obvious difference. Therefore, it can be confirmed from the measurement results in FIG. 12 that the thin film transistor device of the comparative example has poor device uniformity and device characteristics when no connecting electrodes are provided. Fig. 13 shows the relationship between the gate voltage VG and the drain current ID of samples of two thin film transistor elements of this embodiment, wherein sample 4 uses molybdenum with a film thickness=50 angstrom (angstrom) as the connecting electrode, and sample 5 uses Molybdenum with a film thickness of 100 angstroms is used as the connecting electrode. Curve D is the result measured at drain voltage VD=0.1V for sample 4. Curve D' is the result measured at drain voltage VD=5V for sample 4. Curve E is the measurement result of sample 5 at the drain voltage VD=0.1V, and the curve E' is the measurement result of sample 5 at the drain voltage VD=5V. As shown in Figure 13, under different drain voltages (VD) (such as VD=5V or VD=0.1V), the threshold voltages (threshold voltage) of the thin film transistor elements of samples 4-5 are almost the same, confirming the implementation The thin film transistor device of the example has good device uniformity and device characteristics. In addition, since the film thickness of the connection electrode of sample 5 is greater than that of sample 4, the resistance of the connection electrode of sample 5 is lower than that of sample 4, and it can also be seen from FIG. 13 that in the same Under the gate voltage VG and the drain voltage VD, the drain current ID of sample 5 (curve E or curve E′) is significantly higher than that of sample 4 (curve E or curve E′). It has been proved that the setting of the connection electrode can change the device characteristics of the thin film transistor element, and the smaller the resistance of the connection electrode is, the larger the drain current ID is. It is worth noting that when selecting the film thickness of the connecting electrode, in addition to its influence on the drain current ID of the thin film transistor device, whether the second conductive layer is easy to be removed during the lift-off process should also be considered.

In summary, the pixel structure of the present invention utilizes the connection electrode to connect the source/drain to the oxide semiconductor layer, which can effectively avoid the disadvantage that the source/drain is directly in contact with the oxide semiconductor layer, and effectively improve the performance of the thin film transistor device. characteristic.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (15)

1. a kind of dot structure, including：

One substrate；

One thin-film transistor element, is arranged on the substrate, and the thin-film transistor element includes：

Monoxide semiconductor layer, is arranged on the substrate, and the oxide semiconductor layer has a channel region, and one first connects Tactile area is with one second contact zone respectively positioned at the two opposite sides of the channel region；

One gate insulator, is arranged on the oxide semiconductor layer, and the gate insulator is arranged at a upper table of the channel region Face and a upper surface of first contact zone and a upper surface of second contact zone are not covered；

One grid, is arranged on the gate insulator；

One first connection electrode and one second connection electrode, are respectively arranged at the both sides of the gate insulator, the first connection electricity Pole covers the upper surface of first contact zone and covers with the upper surface of first contact zone, and second connection electrode Cover second contact zone the upper surface and with the upper surface of second contact zone, wherein first connection electrode with should Second connection electrode is not Chong Die on a upright projection direction with the gate insulator；

One dielectric layer, is arranged in the grid, first connection electrode and second connection electrode, and wherein the dielectric layer has one First contact hole does not cover a upper surface of at least part of first connection electrode, and one second contact hole does not cover at least One upper surface of partial second connection electrode；And

One source electrode and a drain electrode, are arranged on the dielectric layer, and wherein the source electrode first is connected electricity via the first contact hole with this Pole is electrically connected with, and the drain electrode is electrically connected with via the second contact hole with second connection electrode；

One first protective layer, is arranged on the dielectric layer, and wherein first protective layer has one the 3rd contact hole, does not cover at least The partial drain electrode；

One first pixel electrode, is arranged on first protective layer, wherein first pixel electrode via the 3rd contact hole with The drain electrode of the thin-film transistor element is electrically connected with；And

One storage capacitors element is arranged on the substrate, and wherein the storage capacitors element includes：

One storage capacitors bottom electrode, is arranged on the substrate；

One capacitance dielectric layer, is arranged on the storage capacitors bottom electrode and partly covers a upper table of the storage capacitors bottom electrode Face；

One storage capacitors Top electrode, is arranged on the capacitance dielectric layer；And

One conductive pattern, is arranged at least side of the capacitance dielectric layer and partly covers the upper table of the storage capacitors bottom electrode Face；

Wherein, the conductive pattern, first connection electrode and second connection electrode are made up of same layer patterned conductive layer And it is separated from one another in structure, the conductive pattern, first connection electrode and second connection electrode include metal electrode；And should Storage capacitors bottom electrode with the oxide semiconductor layer is made up of same layer patterned oxide semiconductor layer.

2. dot structure as claimed in claim 1, it is characterised in that first connection electrode and second connection electrode not with The grid is overlapped on the upright projection direction.

3. dot structure as claimed in claim 1, it is characterised in that the side wall of the grid is recessed in the gate insulator Side wall.

4. dot structure as claimed in claim 1, further includes：

One display dielectric layer, is arranged on first pixel electrode；And

One second pixel electrode, is arranged on the display dielectric layer.

5. dot structure as claimed in claim 4, it is characterised in that the display dielectric layer is an organic electric-excitation luminescent layer.

6. dot structure as claimed in claim 4, it is characterised in that separately include one second protective layer, is arranged at this and first protects On sheath, wherein second protective layer does not at least partly cover first pixel electrode, and the display dielectric layer with an opening It is arranged in the opening of second protective layer.

7. dot structure as claimed in claim 1, it is characterised in that the capacitance dielectric layer is with the gate insulator by same layer Patterned insulation layer is constituted, and the storage capacitors Top electrode is made up of with the grid same layer patterned conductive layer.

8. a kind of method for making dot structure, it is characterised in that include：

One substrate is provided；

A patterned oxide semiconductor layer is formed on the substrate, wherein the patterned oxide semiconductor layer includes an oxidation Thing semiconductor layer, and the oxide semiconductor layer has a channel region, and one first contact zone and one second contact zone difference Positioned at the two opposite sides of the channel region；

An insulating barrier and one first conductive layer are sequentially formed on the substrate and the patterned oxide semiconductor layer；

A patterned shielding is formed on first conductive layer, wherein to cover this first conductive for the patterned shielding part Layer；

First conductive layer that the patterned shielding exposed is removed to form one first patterned conductive layer, and is removed To form a patterned insulation layer, wherein the patterned insulation layer includes one to the insulating barrier that the patterned shielding is exposed Gate insulator, the gate insulator cover a upper surface of the channel region and expose a upper surface of first contact zone with And a upper surface of second contact zone, and first patterned conductive layer include a grid be located at the gate insulator on；

On the substrate that the patterned shielding is exposed, the upper table of first contact zone of the oxide semiconductor layer One second conductive layer is formed on face and on the upper surface of second contact zone；

Carry out one and lift off (lift-off) technique, while removing the patterned shielding and in the patterned shielding To form one second patterned conductive layer, wherein second patterned conductive layer includes one first connection electrode to second conductive layer With one second connection electrode, it is respectively formed on the upper surface of first contact zone with being voluntarily directed at (self-align) mode And on the upper surface of second contact zone, and first connection electrode and second connection electrode not with the gate insulator Overlap on a upright projection direction；

A dielectric layer is formed in the grid, first connection electrode and second connection electrode, wherein the dielectric layer has one First contact hole at least partly exposes a upper surface of first connection electrode, and one second contact hole at least partly exposes Go out a upper surface of second connection electrode；And

One the 3rd patterned conductive layer is formed on the dielectric layer, wherein the 3rd patterned conductive layer includes a source electrode and a leakage Pole, the source electrode is electrically connected with via the first contact hole with first connection electrode, and the drain electrode via the second contact hole with Second connection electrode is electrically connected with；

One first protective layer is formed on the dielectric layer, wherein first protective layer has one the 3rd contact hole, at least partly sudden and violent Expose the drain electrode；And

One first pixel electrode is formed on first protective layer.

9. the method for making dot structure as claimed in claim 8, it is characterised in that first connection electrode and second company Receiving electrode is underlapped on the upright projection direction with the grid.

10. the method for making dot structure as claimed in claim 8, it is characterised in that remove patterned shielding institute sudden and violent The step of first conductive layer for exposing is to form first patterned conductive layer includes making the grid using an isotropic etching Side wall be recessed in the side wall of the gate insulator.

The 11. as claimed in claim 8 methods for making dot structures, it is characterised in that first connection electrode with this second Connection electrode includes metal electrode.

The 12. as claimed in claim 8 methods for making dot structures, it is characterised in that first connection electrode with this second Connection electrode includes metal conductive oxide electrode.

13. methods for making dot structure as claimed in claim 8, it is characterised in that further include：

One second protective layer is formed on first protective layer, wherein second protective layer is with an opening, at least partly exposure Go out first pixel electrode；

A display dielectric layer is formed in the opening of second protective layer；And

One second pixel electrode is formed on the display dielectric layer.

14. methods for making dot structure as claimed in claim 13, it is characterised in that the display dielectric layer is an Organic Electricity Excite photosphere.

15. methods for making dot structure as claimed in claim 8, it is characterised in that the patterned oxide semiconductor layer Separately include that a storage capacitors bottom electrode, the patterned insulation layer are separately arranged at the storage capacitors bottom electrode including a capacitance dielectric layer Upper, first patterned conductive layer is separately arranged on the capacitance dielectric layer including a storage capacitors Top electrode, and second pattern Changing conductive layer separately includes a conductive pattern, is arranged at least side of the capacitance dielectric layer and partly covers electricity under the storage capacitors Pole.