CN103296034A - Array substrate, production method thereof and display device - Google Patents

Abstract

The invention belongs to the field of display technology, and relates to an array substrate, a preparation method and a display device. An array substrate, including a substrate, a thin film transistor and a storage capacitor formed on the substrate, the thin film transistor includes a gate, a source, a drain, and The gate insulating layer between the poles, the storage capacitor includes a first pole plate, a second pole plate, and a dielectric layer between the first pole plate and the second pole plate, wherein the gate insulation layer is adjacent to The dielectric constant of the gate insulating layer of the source and the drain part is less than or equal to the dielectric constant of the dielectric layer. The beneficial effects of the present invention are: although the thickness of the dielectric layer of the storage capacitor in the array substrate is small, the capacity of the storage capacitor is high, which significantly reduces the size of the storage capacitor and reduces the size of the pixel structure including the storage capacitor , providing a guarantee for the preparation of high-resolution display panels.

Description

A kind of array substrate, preparation method and display device

technical field

The invention belongs to the field of display technology, and relates to an array substrate, a preparation method and a display device.

Background technique

With the development of display technology, people's demand for display quality is increasing day by day, and the demand for high-quality, high-resolution flat panel display devices is becoming more and more common, and more and more attention has been paid by display panel manufacturers.

Thin Film Transistor (TFT for short) is the main driving device of flat panel display panels at present, and is directly related to the development direction of high-performance flat panel display devices. Thin film transistors have a variety of structures, and there are also many materials for preparing thin film transistors with corresponding structures. Among them, low-temperature polysilicon has a mobility of tens or even hundreds of times that of amorphous silicon. Small thin-film transistors can obtain greater driving capability than thin-film transistors formed of amorphous silicon materials, and low-temperature polysilicon thin-film transistors have therefore attracted the attention of research institutions and display panel manufacturers. Low-temperature polysilicon thin-film transistors that can provide high-quality, high-resolution images gradually appear in the market and continue to develop. OLED for short) provides a better display quality.

Although low-temperature polysilicon thin film transistors have the above advantages, in order to achieve continuous driving capability in low-temperature polysilicon thin film transistor array substrates, it is also necessary to set storage capacitors (Storing Capacity: Cs for short), especially in high-resolution display panels, usually It is necessary to equip the low-temperature polysilicon thin film transistor with a large-capacity storage capacitor to meet the driving requirements. At present, the commonly used process for preparing storage capacitors is to directly use the conductive metal materials that form the gate and source/drain to form the two plates of the storage capacitor while preparing the thin film transistor, and then directly use layer by layer An interlayer insulating layer or a layer of gate insulating layer is used as the dielectric layer of the storage capacitor, thereby forming the storage capacitor. However, considering the electrical characteristics of thin film transistors, neither the interlayer insulating layer nor the gate insulating layer can be made as thin as possible; at the same time, the interlayer insulating layer must play a role of passivation and protection, and the gate insulating layer must be in contact with polysilicon. Layers form a good contact interface. Therefore, usually, the interlayer insulating layer or the gate insulating layer is formed by silicon oxide material with a small dielectric constant.

The capacity of the storage capacitor is calculated by the following formula (1):

Cs=εS/4πkd………………(1)

In formula (1), ε is the dielectric constant, S is the facing area of the capacitor plates, k is the electrostatic force constant, and d is the distance (or thickness) between the capacitor plates.

It can be seen that the large thickness and small dielectric constant of the above-mentioned interlayer insulating layer or gate insulating layer limit the capacity of the storage capacitor, and the capacity of the storage capacitor directly restricts the performance of the high-resolution array substrate, thereby limiting the capacity of the high-resolution array substrate. Further development of resolution display devices.

Therefore, how to increase the capacity of the storage capacitor in the array substrate, obtain a thin film transistor with stable driving capability, reduce the size of the storage capacitor and the size of the pixel structure including the storage capacitor, and improve the display quality of the flat panel display device is an urgent problem to be solved at present. The problem.

Contents of the invention

The technical problem to be solved by the present invention is to provide an array substrate, a preparation method, and a display device for the above-mentioned deficiencies in the prior art. Although the thickness of the dielectric layer of the storage capacitor in the array substrate is small, the thickness of the storage capacitor The higher capacity significantly reduces the size of the storage capacitor.

The technical solution adopted to solve the technical problem of the present invention is the array substrate, which includes a substrate, a thin film transistor and a storage capacitor formed on the substrate, and the thin film transistor includes a gate, a source, a drain, and a The gate insulating layer between the source, the drain and the gate, the storage capacitor includes a first plate, a second plate, and between the first plate and the second plate A dielectric layer, wherein the dielectric constant of the gate insulating layer adjacent to the source and the drain is less than or equal to the dielectric constant of the dielectric layer.

Preferably, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, the dielectric constant of the first gate insulating layer is smaller than that of the second gate insulating layer, and the first gate insulating layer has a dielectric constant smaller than that of the second gate insulating layer. The gate insulating layer is adjacent to the source and the drain, the first plate and the second plate are respectively arranged on the upper and lower sides of the second gate insulating layer, and the dielectric layer is the second The gate insulation layer corresponds to the first plate and the second plate.

A preferred solution is that the source, the drain and the first plate are arranged on the same layer, and the first gate insulating layer completely covers the source and the drain, and does not cover the The first electrode plate; the second gate insulating layer completely covers the first gate insulating layer and the first electrode plate; the gate is arranged on the second gate insulating layer corresponding to the source and the above the region between the drains, and at the same time partially overlap the source and the drain in the direction of the orthographic projection, the second plate is disposed above the second gate insulating layer, and The first polar plate overlaps at least partially in the orthographic projection direction;

Alternatively, the source electrode, the drain electrode and the first electrode plate are arranged on the same layer, and the first gate insulating layer completely covers the source electrode and the drain electrode, and does not cover the first electrode plate ; the second gate insulating layer completely covers the first electrode plate, and does not cover the region corresponding to the source and the drain; the gate is arranged on the first gate insulating layer corresponding to the Above the region between the source and the drain, and at the same time partially overlap the source and the drain in the direction of the orthographic projection, the second plate is arranged on the second gate insulating layer above, and at least partially overlap with the first pole plate in the orthographic projection direction.

A preferred scheme is that the grid is arranged on the same layer as the second electrode plate, and the first gate insulating layer completely covers the grid and does not cover the second electrode plate; The insulating layer completely covers the first gate insulating layer and the second electrode plate; the source and the drain are arranged above the two ends of the second gate insulating layer corresponding to the gate, and respectively Partially overlapping with the gate in the direction of the orthographic projection, the first plate is disposed above the second gate insulating layer corresponding to the second plate;

Alternatively, the gate and the second electrode plate are arranged on the same layer, the first gate insulating layer completely covers the gate and does not cover the second electrode plate; the second gate insulating layer completely covers The second electrode plate does not cover the area corresponding to the gate; the source and the drain are arranged above the two ends of the first gate insulating layer corresponding to the gate, and are respectively Partially overlapping with the gate in the orthographic projection direction, the first pole plate is disposed above the second gate insulating layer corresponding to the second pole plate.

Preferably, the first gate insulating layer is formed of silicon oxide material, and the first gate insulating layer has a single-layer structure; the second gate insulating layer is formed of at least one of silicon oxide material and silicon nitride material Formed, the second gate insulating layer is a single-layer structure or a stacked structure of multiple sub-layers.

Preferably, the thickness range of the first gate insulating layer is The thickness range of the second gate insulating layer is

所述栅极与所述第二极板采用钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种材料形成，所述栅极与所述第二极板的厚度范围为

Preferably, the source, the drain and the first plate are formed of low-temperature polysilicon material, and the thickness of the source, the drain and the first plate is in the range of

The grid and the second pole plate are formed of at least one material selected from molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper, and the thickness range of the grid and the second pole plate is

Preferably, a buffer layer is also included, the buffer layer is a single-layer structure or a laminated structure of multiple sub-layers, the buffer layer is formed by at least one of silicon oxide material and silicon nitride material, and the buffer layer arranged between the substrate and the source, the drain, and the first plate; or, the buffer layer is arranged between the substrate, the gate, and the second plate .

Preferably, the array substrate further includes an interlayer insulating layer and an extraction electrode, the extraction electrode includes a first electrode and a second electrode, and the interlayer insulation layer is arranged between the thin film transistor and the storage capacitor. Above, the region of the interlayer insulating layer corresponding to the source and the drain is respectively provided with a first via hole and a second via hole, and the source is connected to the first via hole through the first via hole. The electrodes are electrically connected, and the drain is electrically connected to the second electrode through the second via hole.

A display device includes the above-mentioned array substrate.

A method for preparing an array substrate, comprising the step of forming a thin film transistor and a storage capacitor on the substrate, the step of forming the thin film transistor includes the steps of forming a gate, a source, and a drain, and The step of forming a gate insulating layer between the electrode and the gate, the step of forming the storage capacitor includes forming a first electrode plate, a second electrode plate and between the first electrode plate and the second electrode plate The step of forming a dielectric layer, wherein the dielectric constant of the gate insulating layer adjacent to the source and the drain is less than or equal to the dielectric constant of the dielectric layer.

Preferably, the step of forming the gate insulating layer includes the step of forming a first gate insulating layer and a second gate insulating layer, and the dielectric constant of the first gate insulating layer is smaller than that of the second gate insulating layer. constant, the first gate insulating layer is adjacent to the source and the drain, the first plate and the second plate are formed on the upper and lower sides of the second gate insulating layer, and the dielectric layer is the part of the second gate insulating layer corresponding to the first pole plate and the second pole plate.

A preferred version is that the preparation method specifically includes the following steps:

Step S1): forming a buffer layer on the substrate;

Step S2): forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form a silicon island including an active layer and an electrode Graphics of silicon islands on the board;

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), the first gate insulating layer completely covers the source and the drain, and does not cover the first a polar plate, and forming the first polar plate in the silicon island of the polar plate by ion implantation;

Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covering the first gate insulating layer and the first electrode plate;

Alternatively, step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the first electrode plate, and does not cover the source electrode and the the region corresponding to the drain;

Step S5): On the substrate after step S4), a pattern including a gate and a second electrode plate is formed on the second gate insulating layer, and the gate is formed corresponding to the source and the The region between the drains and at the same time partially overlaps the source and the drain in the orthographic projection direction, and the second electrode plate and the first electrode plate at least partially overlap in the orthographic projection direction;

Alternatively, step S5): on the substrate after step S4), a pattern including a gate is formed on the first gate insulating layer, and the gate is formed corresponding to the source and the drain and at the same time partially overlap with the source and the drain in the direction of the orthographic projection; a pattern including a second plate is formed above the second gate insulating layer, and the second plate and The first polar plate at least partially overlaps in the orthographic projection direction;

Step S6): on the substrate after step S5), the source and the drain are formed on both sides of the silicon island of the active layer by means of ion implantation.

A preferred version is that the preparation method specifically includes the following steps:

Step S1): forming a buffer layer on the substrate;

Step S2): forming a pattern including a gate and a second plate on the buffer layer;

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), the first gate insulating layer completely covering the gate and not covering the pattern of the second electrode plate;

Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covering the first gate insulating layer and the second electrode plate;

Alternatively, step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the second electrode plate and does not cover the corresponding gate electrode. the area where

Step S5): forming an amorphous silicon layer on the substrate after step S4), crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form an active layer Graphics of silicon islands and plate silicon islands;

Step S6): forming the source and the drain on both sides of the silicon island in the active layer by ion implantation, the source and the drain are at least at least the same as the gate in the direction of the orthographic projection Partially overlapping: a first pole plate is formed in the pole plate silicon island by means of ion implantation, and the first pole plate overlaps with the second pole plate in the orthographic projection direction.

Further preferably, it further includes step S7): forming a pattern including an interlayer insulating layer and a lead-out electrode above the thin film transistor and the storage capacitor, and the lead-out electrode includes a first electrode and a second electrode. A first via hole and a second via hole are respectively formed in regions above the interlayer insulating layer corresponding to the source electrode and the drain electrode, and the source electrode and the first electrode are electrically connected through the first via hole. connected, the drain is electrically connected to the second electrode through the second via hole.

沉积温度小于等于600℃。Preferably, forming the buffer layer on the substrate includes plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering. The thickness of the buffer layer ranges from

The deposition temperature is less than or equal to 600°C.

所述第二栅绝缘层的厚度范围为

Preferably, forming the first gate insulating layer and the second gate insulating layer includes plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition or sputtering form the corresponding first gate insulating layer film and the second gate insulating layer film, the thickness range of the first gate insulating layer is

The thickness range of the second gate insulating layer is

Preferably, forming the gate includes forming the gate film by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. , through a patterning process to form a pattern including the gate and the second plate, the thickness of the gate and the second plate is in the range of

对所述非晶硅层进行晶化包括采用准分子激光晶化方式、金属诱导晶化方式或固相晶化方式，或者还进一步包括：在晶化过程中增加热处理脱氢工艺、沉积诱导金属工艺、热处理晶化工艺或准分子激光照射晶化工艺、杂质掺杂及掺杂杂质的激活工艺。Preferably, forming the amorphous silicon layer includes plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, the deposition temperature is less than or equal to 600°C, and the thickness of the polysilicon layer is in the range of

Crystallizing the amorphous silicon layer includes excimer laser crystallization, metal-induced crystallization, or solid-phase crystallization, or further includes: adding a heat treatment dehydrogenation process during the crystallization process, depositing an induced metal process, heat treatment crystallization process or excimer laser irradiation crystallization process, impurity doping and impurity activation process.

Preferably, the ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid-state diffusion implantation method, wherein the implantation medium is a boron-containing element and /or phosphorus-containing gas, the implantation energy is in the range of 10-200keV, and the implantation dose is in the range of 1x10 ¹¹ -1x10 ²⁰ atoms/cm ³ .

Preferably, after the ion implantation, the TFT is activated by rapid heating annealing, excimer laser annealing or furnace annealing, the annealing temperature ranges from 300°C to 600°C, and the annealing time ranges from 0.5 to 4 hours.

The beneficial effects of the present invention are: in the array substrate, by changing the materials of the source electrode, the gate insulation layer between the drain electrode and the gate electrode, the electrode plate of the storage capacitor and the dielectric layer forming the thin film transistor, and adopting the corresponding array The preparation method of the substrate adopts the existing mask plate for forming the storage capacitor and is matched with an insulating material with a large dielectric constant, which not only reduces the thickness of the dielectric layer in the storage capacitor, but also effectively improves the capacity of the storage capacitor, significantly reducing The size of the storage capacitor is reduced, and the size of the pixel structure including the storage capacitor is reduced, thereby solving the problem that the size of the storage capacitor is large in the preparation of the low-temperature polysilicon thin film transistor array substrate and limiting the improvement of the resolution, and provides a high-resolution display panel. Guaranteed, that is, to provide a guarantee for the preparation of high-resolution liquid crystal display devices and organic electroluminescent display devices.

Description of drawings

1 is a cross-sectional view of an array substrate in the prior art;

2 is a cross-sectional view of the array substrate in Embodiment 1 of the present invention;

Fig. 3 is a flow chart of the method for preparing the array substrate in Fig. 2;

4 is a cross-sectional view of each step in the preparation process of the array substrate in FIG. 2;

in:

4A is a cross-sectional view of forming a buffer layer;

4B (4B-1, 4B-2) is a cross-sectional view of forming a polysilicon layer;

4C is a cross-sectional view of forming a first gate insulating layer and a mask layer;

4D is a cross-sectional view of forming a second gate insulating layer;

Figure 4E (4E-1, 4E-2) is a cross-sectional view of forming a pattern including a gate and a second plate;

Figure 4F is a cross-sectional view of forming a source and a drain;

4G is a cross-sectional view of forming a pattern including an interlayer insulating layer and including an extraction electrode;

5 is a cross-sectional view of the array substrate in Embodiment 2 of the present invention;

6 is a cross-sectional view of the array substrate in Embodiment 3 of the present invention;

7 is a cross-sectional view of an array substrate in Embodiment 4 of the present invention;

In the figure: 1-substrate; 2-buffer layer; 31-source; 32-drain; 33-polysilicon layer; 33a-active layer silicon island; 33b-plate silicon island; 33c-area to be implanted; 34- Gate; 340-first metal layer; 4-gate insulating layer; 41-first gate insulating layer; 41a-mask layer; 41b-area to be etched; 42-second gate insulating layer; 61-first electrode plate; 62-second pole plate; 7-interlayer insulating layer; 81-first electrode; 82-second electrode.

Detailed ways

In order to enable those skilled in the art to better understand the technical solution of the present invention, the array substrate, manufacturing method and display device of the present invention will be further described in detail below with reference to the drawings and specific embodiments.

An array substrate, including a substrate, a thin film transistor and a storage capacitor formed on the substrate, the thin film transistor includes a gate, a source, a drain, and The gate insulating layer between the poles, the storage capacitor includes a first pole plate, a second pole plate, and a dielectric layer between the first pole plate and the second pole plate, wherein the gate insulation layer is adjacent to The dielectric constant of the gate insulating layer of the source and the drain part is less than or equal to the dielectric constant of the dielectric layer.

A display device includes the above-mentioned array substrate.

A method for preparing an array substrate, comprising the step of forming a thin film transistor and a storage capacitor on the substrate, the step of forming the thin film transistor includes the steps of forming a gate, a source, and a drain, and The step of forming a gate insulating layer between the electrode and the gate, the step of forming the storage capacitor includes forming a first electrode plate, a second electrode plate and between the first electrode plate and the second electrode plate The step of forming a dielectric layer, wherein the dielectric constant of the gate insulating layer adjacent to the source and the drain is less than or equal to the dielectric constant of the dielectric layer.

Example 1:

As shown in FIG. 2, an array substrate includes a substrate 1, a buffer layer 2 formed on the substrate 1, and a thin film transistor and a storage capacitor formed on the buffer layer 2, and the thin film transistor includes a gate 34 , source 31, drain 32 and the gate insulating layer 4 arranged between the source 31, the drain 32 and the gate 34, the storage capacitor includes a first plate 61, a second plate plate 62 and the dielectric layer between the first pole plate and the second pole plate, the gate insulating layer 4 includes a first gate insulating layer 41 and a second gate insulating layer 42, and the first gate insulating layer 41 has a dielectric constant smaller than that of the second gate insulating layer 42, the first gate insulating layer 41 is adjacent to the source 31 and the drain 32, and the first plate 61 and the The second pole plate 62 is separately arranged on the upper and lower sides of the second gate insulating layer 42 , and the dielectric layer is that the second gate insulating layer 42 corresponds to the first pole plate 61 and the second pole plate 62 part.

In order to perform insulation protection and signal extraction for thin film transistors and storage capacitors, the array substrate also includes an interlayer insulating layer 7 and extraction electrodes, the extraction electrodes include a first electrode 81 and a second electrode 82, and the interlayer insulation layer 7 layer 7 is disposed above the thin film transistor and the storage capacitor, and the regions of the interlayer insulating layer 7 corresponding to the source electrode 31 and the drain electrode 32 are respectively provided with a first via hole and a second via hole , the source 31 is electrically connected to the first electrode 81 through the first via hole, and the drain 32 is electrically connected to the second electrode 82 through the second via hole.

Wherein, the source electrode 31, the drain electrode 32 and the first electrode plate 61 are arranged in the same layer, and the first gate insulating layer 41 completely covers the source electrode 31 and the drain electrode 32, and does not cover The first electrode plate 61; the second gate insulating layer 42 completely covers the first gate insulating layer 31 and the first electrode plate 61; the gate 34 is disposed on the second gate insulating layer 42 Corresponding to the upper part of the area between the source 31 and the drain 32 and at the same time partially overlapping the source 31 and the drain 32 in the orthographic projection direction, the second plate 62 is set It is above the second gate insulating layer 42 and at least partially overlaps with the first electrode plate 61 in the orthographic projection direction.

所述第二栅绝缘层42的厚度范围为 In this embodiment, the first gate insulating layer 41 is formed of silicon oxide material, and the first gate insulating layer 41 has a single-layer structure; the second gate insulating layer 42 is formed of silicon oxide material, silicon nitride material At least one of them is formed, and the second gate insulating layer 42 is a single-layer structure or a stacked structure of multiple sub-layers. The thickness range of the first gate insulating layer 41 is

The thickness range of the second gate insulating layer 42 is

所述栅极34与所述第二极板62采用钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种材料形成，所述栅极34与所述第二极板62的厚度范围为

In this embodiment, the source 31, the drain 32 and the first plate 61 are formed of low-temperature polysilicon material, and the source 31, the drain 32 and the first plate 61 The thickness range is

The grid 34 and the second pole plate 62 are formed of at least one material selected from molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper, and the grid 34 and the second pole plate 62 The thickness range is

In this embodiment, the buffer layer 2 is a single-layer structure or a laminated structure of multiple sub-layers, and the buffer layer 2 is formed using at least one of silicon oxide materials and silicon nitride materials. In this embodiment, the thin film transistor has a top-gate structure, and the buffer layer 2 is disposed between the substrate 1 , the source 31 , the drain 32 , and the first plate 61 .

Correspondingly, a method for preparing an array substrate includes the step of forming a thin film transistor and a storage capacitor on the substrate, and the step of forming the thin film transistor includes the steps of forming a gate, a source, and a drain, and forming a gate, a source, and a drain on the source, The step of forming a gate insulating layer between the drain and the gate, the step of forming the storage capacitor includes the step of forming a first plate and a second plate, wherein the step of forming the gate insulating layer includes a step of forming a first gate insulating layer and a second gate insulating layer, the dielectric constant of the first gate insulating layer is smaller than that of the second gate insulating layer, the first gate insulating layer is adjacent to the source pole, the drain, the first pole plate and the second pole plate are formed on the upper and lower sides of the second gate insulating layer, and the dielectric layer is the second gate insulating layer corresponding to the Parts of the first pole plate and the second pole plate.

Preferably, as shown in Figure 3, the preparation method specifically includes the following steps:

Step S1): forming a buffer layer on the substrate.

优选厚度范围为

沉积温度小于等于600℃。As shown in FIG. 4A, in this step, on the substrate 1, plasma enhanced chemical vapor deposition (Plasma Enhanced: PECVD for short), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition: LPCVD for short), The buffer layer 2 is formed by Atmospheric Pressure Chemical Vapor Deposition (APCVD for short) or Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD for short) or sputtering. The buffer layer 2 can be a single layer of silicon oxide, silicon nitride or a stack of the two, and its thickness ranges from

The preferred thickness range is

The deposition temperature is less than or equal to 600°C.

Wherein, the substrate 1 is made of transparent material such as glass and has been pre-cleaned. The buffer layer 2 is used to prevent the impurities contained in the substrate 1 from diffusing into the active layer of the thin film transistor (TFT), so as to prevent the characteristics such as threshold voltage and leakage current of the TFT from being affected. In addition to the introduction of the buffer layer 2, since the traditional alkali glass has a high content of metal impurities such as aluminum, barium, and sodium, the diffusion of metal impurities is easy to occur in the high-temperature treatment process, so it is preferable that the substrate 1 is made of alkali-free glass.

Step S2): forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form an active layer silicon island and an electrode Graphics of the board silicon island.

优选厚度范围为对所述非晶硅层进行晶化包括采用准分子激光晶化方式、金属诱导晶化方式或固相晶化方式，将非晶硅层转变为多晶硅层33（图4B-1），需要说明的是，采用不同的晶化方式，其具体的工艺过程及薄膜晶体管的结构会有所不同。或者，根据具体生产工艺，还进一步包括：在晶化过程中增加热处理脱氢工艺、沉积诱导金属工艺、热处理晶化工艺、准分子激光照射晶化工艺、杂质掺杂及掺杂杂质的激活工艺，其中杂质掺杂主要是源漏极区域的掺杂（P型掺杂或者N型掺杂）。As shown in Figure 4B, in this step, the amorphous silicon layer is formed on the buffer layer 2 by deposition methods, the deposition methods include plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition, and the deposition temperature is less than or equal to 600°C, the thickness of the amorphous silicon layer ranges from

The preferred thickness range is Crystallizing the amorphous silicon layer includes using excimer laser crystallization, metal-induced crystallization, or solid-phase crystallization to convert the amorphous silicon layer into a polysilicon layer 33 (FIG. 4B-1), which needs to be explained What's more, the specific process and the structure of the thin film transistor will be different with different crystallization methods. Or, according to the specific production process, it further includes: adding heat treatment dehydrogenation process, deposition induction metal process, heat treatment crystallization process, excimer laser irradiation crystallization process, impurity doping and impurity activation process in the crystallization process , where the impurity doping is mainly the doping of the source and drain regions (P-type doping or N-type doping).

After the crystallization process is completed, a pattern including the active layer silicon island 33 a and the electrode plate silicon island 33 b is formed in the polysilicon layer 33 by using a patterning process ( FIG. 4B-2 ). Among them, the patterning process may only include a photolithography process, or include a photolithography process and an etching step, and may also include other processes for forming predetermined patterns such as printing and inkjet; , exposure, development and other processes using photoresist, mask plate, exposure machine, etc. to form graphics. The corresponding patterning process can be selected according to the structure formed in the present invention.

In this embodiment, a layer of photoresist is formed on the polysilicon layer 33, the photoresist is exposed and developed, and then the polysilicon layer 33 is dry-etched to form an active layer silicon island 33a and a polar plate. The pattern of the silicon island 33b, the area of the active layer silicon island 33a is used to form the active layer of the TFT, and the area of the plate silicon island 33b is used to form the first plate 61 of the storage capacitor.

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), the first gate insulating layer completely covers the source and the drain, and does not cover the first plate, and forming the first plate in the silicon island of the plate by ion implantation.

In this step, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering are applied to the active layer silicon island 33a and the pole plate silicon island 33b. The first gate insulating layer film is formed on the top of the , and the deposition temperature is less than or equal to 600°C.

Then, as shown in FIG. 4C, a layer of photoresist is formed on the first gate insulating layer film, and the photoresist is exposed and developed to form a mask layer 41a, and the mask layer 41a corresponds to the The photoresist of the silicon island 33b of the pole plate is removed except for the edge region, thereby exposing the first gate insulating layer film region corresponding to the region where the first pole plate will be formed, and the exposed region corresponds to the first gate insulating layer film region. The part is the region to be etched 41b (that is, defines the region to be etched in the first gate insulating layer film), and the corresponding electrode plate silicon island 33b region of the exposed region is the region to be implanted 33c (that is, defines the region to be etched in the polysilicon layer 33 the ion implantation area of the first plate 61). The mask in the photolithography process can directly use the storage capacitor mask in the common process without additional design, so that additional mask design and manufacturing costs do not need to be increased.

或根据具体工艺需要选择合适的厚度。Wherein, the first gate insulating layer 41 can be formed by a single layer of silicon oxide material, which can form a good interface contact with the active layer (active layer silicon island 33a) below it, and improve the performance of thin film transistors. electrical properties. The thickness of the first gate insulating layer 41 is

Or choose the appropriate thickness according to the specific process needs.

Next, ion implantation is performed on the to-be-implanted region 33c of the polar plate silicon island 33b to form the first polar plate 61 (the to-be-implanted region 33c forms the first polar plate 61 after ion implantation). The ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid-state diffusion implantation method. In this embodiment, the mainstream ion cloud implantation method is preferably adopted, and a heavy dose is implanted into the region 33c to be implanted to form the first plate of the storage capacitor. According to design requirements, the injection medium is a gas containing boron and/or phosphorus, and a preferred method is to use a mixture of boron, such as B ₂ H ₆ /H ₂ (ratio between 5% and 15%) Gas is used as the implant medium; the implant energy range is 10-200keV, more preferably the energy range is 40-100keV; the implant dose range is 1x10 ¹¹ -1x10 ²⁰ atoms/cm ³ , the more preferred implant dose range is 1x10 ¹³ -8x10 ¹⁵ atoms /cm ³ ; or, phosphorus-containing elements, such as mixed gas of PH ₃ /H ₂ , can also be used as the injection medium, and the injection energy and injection dose are similar to the above-mentioned B ₂ H ₆ /H ₂ method, which will not be described in detail here .

Furthermore, dry etching or wet etching is performed on the to-be-etched region 41 b of the first gate insulating layer film to form the first gate insulating layer 41 . In dry etching, gas containing fluorine elements, such as SF ₆ , CF ₄ , CHF _{3 ,} etc., or a mixture of the aforementioned gas and O ₂ can be used as the etching medium. etch in a machine or a reaction-coupled plasma etch machine. During wet etching, hydrofluoric acid or a hydrofluoric acid solution added with a corrosion inhibitor can be used as an etching medium to etch and remove the first gate insulating layer film in the region 41b to be etched at room temperature or high temperature. The above two etching methods can both obtain better etching effects in this embodiment, and the remaining photoresist can be stripped and removed by a common stripping process after the etching is completed.

It should be understood here that, in this step, the process sequence of forming the first electrode plate by ion implantation and forming the first gate insulating layer by etching can be changed, and the process sequence can be flexibly adjusted as required in the actual production process.

Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), and the second gate insulating layer completely covers the first gate insulating layer and the first electrode plate.

As shown in FIG. 4D, in this step, the second gate insulating layer 42 is formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering. , the deposition temperature is less than or equal to 600°C.

或根据具体工艺需要选择合适的厚度。The second gate insulating layer 42 can use a single layer of silicon oxide material, silicon nitride material or at least one of the two materials to form a stack of multiple sub-layers. In order to increase the capacity of the storage capacitor, the second gate insulating layer The thickness of the second gate insulating layer 42 can be as thin as possible, and is preferably formed of silicon nitride material with a relatively high dielectric constant. The thickness range of the second gate insulating layer 42 is

Or choose the appropriate thickness according to the specific process needs.

Step S5): On the substrate after step S4), a pattern including a gate and a second plate is formed on the second gate insulating layer, and the gate is formed corresponding to the source and the The region between the drains and at the same time partially overlaps with the source and the drain in the orthographic projection direction, and the second electrode plate and the first electrode plate at least partially overlap in the orthographic projection direction.

优选厚度范围为

As shown in FIG. 4E, in this step, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or Electron cyclotron resonance chemical vapor deposition forms the first metal layer 340 (FIG. 4E-1), and through one patterning process (film formation, exposure, development, wet etching or dry etching), simultaneously forms the gate 34 and The pattern of the second pole plate 62 ( FIG. 4E-2 ). The first metal layer 340 is formed of conductive materials such as metals and metal alloys, such as molybdenum and molybdenum alloys, and the thickness range of the grid 34 and the second electrode plate 62 is

The preferred thickness range is

So far, the storage capacitor is formed, wherein: the first pole plate 61 and the second pole plate 62 respectively form two pole plates of the storage capacitor, and the first pole plate 61 and the second pole plate 62 The second gate insulating layer 42 in between forms a dielectric layer. In this embodiment, since the second gate insulating layer 42 can be made as thin as possible and has a relatively large dielectric constant, according to the formula (1), the storage capacitor can obtain a larger capacitance with a smaller size (Compared with the existing technology, it can be increased by at least 2 times), and it also effectively reduces the size occupied by the storage capacitor on the array substrate, so that the density of the pixel area in the array substrate can be further increased, and it is necessary to prepare high-resolution The display panel is guaranteed.

Step S6): on the substrate after step S5), the source and the drain are formed on both sides of the silicon island of the active layer by means of ion implantation.

As shown in FIG. 4F , in this step, the source 31 and the drain 32 are formed on both sides of the active layer silicon 33 a island. The ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method or a solid-state diffusion implantation method. According to design requirements, the injection medium is a gas containing boron and/or phosphorus, preferably a mixture of boron, such as B ₂ H ₆ /H ₂ (ratio between 5% and 15%), as the injection medium The range of implantation energy is 10-200keV, more preferably the range of energy is 40-100keV; the range of implantation dose is 1x10 ¹¹ -1x10 ²⁰ atoms/cm ³ , and the range of implantation dose is more preferably 1x10 ¹³ -8x10 ¹⁵ atoms/cm ³ .

After the ion implantation process, the thin film transistor can be activated by rapid thermal annealing (Rapid Thermal Annealer: RTA), excimer laser annealing (Excimer Laser Annealer: ELA) or furnace annealing. In this embodiment, the furnace annealing method is preferred for activation and heat treatment of the thin film transistor. The furnace annealing method has the advantages of economy, simplicity, and better uniformity. The annealing temperature range is 300°C-600°C, and the annealing time range is 0.5-4 hours , a further preferred time range is 1-3 hours.

It should be understood here that the process sequence in step S4), step S5) and step S6) can be reversed, that is, in this embodiment, the source and drain can also be formed by ion implantation, and then the patterning process The second gate insulating layer is formed first, and then the pattern including the gate and the first plate is formed. In the actual production process, the process sequence can be flexibly adjusted according to needs.

In order to insulate and protect the thin film transistor and the storage capacitor, the preparation method further includes step S7): forming an interlayer insulating layer above the thin film transistor and the storage capacitor; in order to extract signals from the thin film transistor, the The preparation method further includes: respectively forming a pattern including a first via hole, a second via hole, and a lead-out electrode in the region of the interlayer insulating layer corresponding to the source electrode and the drain electrode, and the lead-out electrode It includes a first electrode and a second electrode, the source is electrically connected to the first electrode through the first via hole, and the drain is electrically connected to the second electrode through the second via hole.

优选厚度范围为

与沉积第一栅绝缘层以及第二栅绝缘层的方式相同，可采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式沉积形成层间绝缘层7，沉积温度小于等于600℃。所述层间绝缘层7可采用单层的氧化硅材料或者氧化硅材料、氮化硅材料形成多个子层的叠层。As shown in FIG. 4G, an interlayer insulating layer 7 is deposited above the thin film transistor and the storage capacitor, and the thickness range of the interlayer insulating layer 7 is

The preferred thickness range is

In the same manner as the deposition of the first gate insulating layer and the second gate insulating layer, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition can be used to form an interlayer The insulating layer 7 is deposited at a temperature lower than or equal to 600°C. The interlayer insulating layer 7 may use a single layer of silicon oxide material or a stack of multiple sub-layers formed of silicon oxide material and silicon nitride material.

Next, a mask layer is formed on the interlayer insulating layer 7 by a photolithography process, and a first via hole and a second via hole are formed by dry etching. Dry etching can adopt various methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, etc. The etching gas can be a gas containing fluorine and chlorine, such as CF ₄ , CHF ₃ , SF ₆ , CCl _{2 F2} and other gases or the mixed gas formed by the above gases and _O2 .

优选厚度范围为 Then, the second metal is deposited on the interlayer insulating layer 7 by sputtering, thermal evaporation or plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. layer. A mask layer is formed on the second metal layer by a photolithography process, and a pattern comprising a first electrode 81 and a second electrode 82 is formed by wet etching or dry etching, and the first electrode 81 runs through the first The via hole is electrically connected to the source 31 , and the second electrode 82 passes through the second via hole and is electrically connected to the drain 32 . Further, the first electrode 81 is electrically connected to the data line in the array substrate, and the second electrode 82 is electrically connected to the pixel electrode in the array substrate. The second metal layer is made of metal, metal alloy, such as: molybdenum, molybdenum alloy, aluminum, aluminum alloy, titanium and other conductive materials, and the thickness range is

The preferred thickness range is

In this embodiment, among the two plates of the storage capacitor, one plate is made of the same low-temperature amorphous silicon material (needs to be doped) as the source and drain of the thin film transistor, and the other plate is made of the same Form the same conductive metal material as the gate of the thin film transistor; while the gate insulating layer of the thin film transistor is formed by stepwise deposition, the first gate insulating layer has good interface contact with the source and drain, and has a small dielectric constant The second gate insulating layer is formed of a material with a relatively high dielectric constant (such as silicon nitride), and the second gate insulating layer between the two plates of the storage capacitor is the dielectric layer. In this way, under the same capacitance condition, compared with the existing storage capacitor, the thickness of the dielectric layer is thinner, and the size of the storage capacitor is smaller, so that the capacitance required by the design can be achieved by using a small-sized storage capacitor, which reduces the The size of the pixel structure of the storage capacitor provides a guarantee for the preparation of a high-resolution display panel.

Example 2:

The thin film transistors in this embodiment and the array substrate in Embodiment 1 are the same top-gate type. The difference lies in that the structure of the first gate insulating layer in the array substrate of this embodiment is different from that of Embodiment 1.

As shown in FIG. 5 , in this embodiment, the source electrode 31 and the drain electrode 32 are arranged on the same layer as the first plate 61 , and the first gate insulating layer 41 completely covers the source electrode 31 and the drain 32 without covering the first plate 61; the second gate insulating layer 42 completely covers the first plate 61 and does not cover the source 31 and the drain 32 Corresponding region; the gate 34 is disposed above the first gate insulating layer 41 corresponding to the region between the source 31 and the drain 32, and is simultaneously connected to the source 31 and the drain. The drain 32 partially overlaps in the direction of the orthographic projection, and the second plate 62 is disposed above the second gate insulating layer 42 and at least partially overlaps with the first plate 61 in the direction of the orthographic projection.

Correspondingly, the method for preparing the array substrate of this embodiment specifically includes the following steps:

Step S1): forming a buffer layer on the substrate;

Step S2): forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form a silicon island including an active layer and an electrode Graphics of silicon islands on the board;

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), the first gate insulating layer completely covers the source and the drain, and does not cover the first a polar plate, and forming the first polar plate in the silicon island of the polar plate by ion implantation;

Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the first plate, and does not cover the source and the The area corresponding to the drain;

Step S5): On the substrate after step S4), a pattern including a gate is formed on the first gate insulating layer, and the gate is formed between the corresponding source and the drain area, and at the same time partially overlap with the source and the drain in the direction of the orthographic projection; a pattern including a second plate is formed on the second gate insulating layer, and the second plate and the The first polar plate overlaps at least partially in the direction of the orthographic projection;

Step S6): on the substrate after step S5), the source and the drain are formed on both sides of the silicon island of the active layer by means of ion implantation.

The other structures of the array substrate in this embodiment are the same as those in Embodiment 1, and the specific process or process parameters in the preparation process can refer to the preparation method in Embodiment 1, which will not be repeated here.

Example 3:

The difference between this embodiment and Embodiments 1 and 2 is that the thin film transistors in the array substrate of this embodiment are bottom gate type.

As shown in FIG. 6, in this embodiment, an array substrate includes a substrate 1, a buffer layer 2 formed on the substrate 1, and a thin film transistor and a storage capacitor formed on the buffer layer 2, the The thin film transistor includes a gate 34, a source 31, a drain 32, and a gate insulating layer 4 disposed between the source 31, the drain 32, and the gate 34, and the storage capacitor includes a first electrode plate 61 and a second electrode plate 62, the gate insulating layer 4 includes a first gate insulating layer 41 and a second gate insulating layer 42, the dielectric constant of the first gate insulating layer 41 is smaller than that of the second gate insulating layer The dielectric constant is 42, and the first electrode plate 61 and the second electrode plate 62 are respectively disposed on two sides of the second gate insulating layer 42 .

In this embodiment, since the thin film transistor has a bottom-gate structure, the buffer layer 2 is disposed between the substrate 2 , the gate 34 , and the second plate 62 . The gate 34 and the second pole plate 62 are arranged on the same layer, and the first gate insulating layer 41 completely covers the gate 34 and does not cover the second pole plate 62; the second gate insulation layer 41 Layer 42 completely covers the first gate insulating layer 41 and the second plate 62; the source 31 and the drain 32 are arranged on the second gate insulating layer 42 corresponding to the gate 34 Above the two ends and partially overlapping with the grid 34 in the orthographic projection direction, the first electrode plate 61 is disposed above the second gate insulating layer 42 corresponding to the second electrode plate 62 .

Correspondingly, the method for preparing the array substrate in this embodiment specifically includes the following steps:

Step S1): forming a buffer layer on the substrate;

Step S2): forming a pattern including a gate and a second plate on the buffer layer;

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), and the first gate insulating layer completely covers the gate and does not cover the second electrode plate;

Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covering the first gate insulating layer and the second electrode plate;

Step S5): forming an amorphous silicon layer on the substrate after step S4), crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form an active layer Graphics of silicon islands and plate silicon islands;

Step S6): forming the source and the drain on both sides of the silicon island in the active layer by ion implantation, the source and the drain are at least at least the same as the gate in the direction of the orthographic projection Partially overlapping: a first pole plate is formed in the pole plate silicon island by means of ion implantation, and the first pole plate overlaps with the second pole plate in the orthographic projection direction.

The other structures of the array substrate in this embodiment are the same as those in Embodiment 1, and the specific process or process parameters in the preparation process can refer to the preparation method in Embodiment 1, which will not be repeated here.

Example 4:

The thin film transistors in the array substrate of this embodiment and the third embodiment are both bottom gate type. The difference lies in that the structure of the second gate insulating layer in the array substrate of this embodiment is different from that of Embodiment 3.

As shown in FIG. 7 , in this embodiment, the gate 34 and the second plate 62 are arranged on the same layer, and the first gate insulating layer 41 completely covers the gate 34 and does not cover the gate 34 . The second plate 62; the second gate insulating layer 42 completely covers the second plate 62 and does not cover the area corresponding to the gate 34; the source 31 and the drain 32 are arranged on The first gate insulating layer 41 corresponds to the top of the two ends of the gate 34 and partially overlaps with the gate 34 in the orthographic projection direction, and the first electrode plate 62 is arranged on the second gate. The insulating layer 42 corresponds to the top of the second plate 62 .

Correspondingly, the method for preparing the array substrate of this embodiment specifically includes the following steps:

Step S1): forming a buffer layer on the substrate;

Step S2): forming a pattern including a gate and a second plate on the buffer layer;

Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), and the first gate insulating layer completely covers the gate and does not cover the second electrode plate;

Step S4): Forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the second electrode plate and does not cover the gate corresponding to area;

Step S5): forming an amorphous silicon layer on the substrate after step S4), crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form an active layer Graphics of silicon islands and plate silicon islands;

Step S6): forming the source and the drain on both sides of the silicon island in the active layer by ion implantation, the source and the drain are at least at least the same as the gate in the direction of the orthographic projection Partially overlapping: a first pole plate is formed in the pole plate silicon island by means of ion implantation, and the first pole plate overlaps with the second pole plate in the orthographic projection direction.

Other structures of the array substrate in this embodiment are the same as those in Embodiment 3, and the specific process or process parameters in the preparation process can refer to the preparation method in Embodiment 1, which will not be repeated here.

The present invention also provides a display device, including the array substrate in any one of the embodiments 1-4. The display device may be a liquid crystal display device or an electroluminescence display device, such as a liquid crystal panel, a liquid crystal TV, a mobile phone, a liquid crystal display, etc., which include a color filter substrate and the array substrate in the above-mentioned embodiments; except for the liquid crystal display device, all The above-mentioned display device may also be other types of display devices, such as electronic readers, which do not include the color filter substrate, but include the array substrate in the above-mentioned embodiments.

In the array substrate of the present invention, by changing the materials forming the gate insulating layer between the source, drain and gate of the thin film transistor, the electrode plate of the storage capacitor and the dielectric layer, and adopting the corresponding preparation method of the array substrate, adopting The existing mask for forming the storage capacitor is matched with an insulating material with a large dielectric constant, which not only reduces the thickness of the dielectric layer in the storage capacitor, but also effectively improves the capacity of the storage capacitor, significantly reduces the size of the storage capacitor, and reduces the The size of the pixel structure including the storage capacitor is reduced, thereby solving the problem that the size of the storage capacitor is large in the preparation of the low-temperature polysilicon thin film transistor array substrate and limiting the improvement of resolution, and providing a guarantee for the preparation of high-resolution display panels, that is, for The preparation of high-resolution liquid crystal display devices and organic electroluminescent display devices provides assurance.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (17)

1. An array substrate, comprising a substrate, a thin film transistor and a storage capacitor formed on the substrate, the thin film transistor comprising a gate, a source, a drain, and an array arranged between the source, the drain and the A gate insulating layer between the gates, the storage capacitor includes a first pole plate, a second pole plate, and a dielectric layer between the first pole plate and the second pole plate, characterized in that the The dielectric constant of the gate insulating layer adjacent to the source and the drain is less than or equal to the dielectric constant of the dielectric layer. 2. The array substrate according to claim 1, wherein the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, and the dielectric constant of the first gate insulating layer is smaller than that of the second gate insulating layer. The dielectric constant of the gate insulating layer, the first gate insulating layer is adjacent to the source and the drain, and the first electrode plate and the second electrode plate are separately arranged on the upper and lower sides of the second gate insulating layer On both sides, the dielectric layer is the part of the second gate insulating layer corresponding to the first pole plate and the second pole plate. 3. The array substrate according to claim 2, wherein the source electrode, the drain electrode and the first electrode plate are arranged on the same layer, and the first gate insulating layer completely covers the source electrode and the drain electrode. The drain does not cover the first electrode plate; the second gate insulating layer completely covers the first gate insulating layer and the first electrode plate; the gate is arranged on the second gate The insulating layer corresponds to the upper part of the area between the source and the drain, and at the same time partially overlaps the source and the drain in the orthographic projection direction, and the second plate is arranged on the Above the second gate insulating layer and at least partially overlapping with the first electrode plate in the orthographic projection direction; Alternatively, the source electrode, the drain electrode and the first electrode plate are arranged on the same layer, and the first gate insulating layer completely covers the source electrode and the drain electrode, and does not cover the first electrode plate ; the second gate insulating layer completely covers the first electrode plate, and does not cover the region corresponding to the source and the drain; the gate is arranged on the first gate insulating layer corresponding to the Above the region between the source and the drain, and at the same time partially overlap the source and the drain in the direction of the orthographic projection, the second plate is arranged on the second gate insulating layer above, and at least partially overlap with the first pole plate in the orthographic projection direction. 4. The array substrate according to claim 2, wherein the gate is arranged on the same layer as the second plate, and the first gate insulating layer completely covers the gate and does not cover the gate. The second electrode plate; the second gate insulating layer completely covers the first gate insulating layer and the second electrode plate; the source and the drain are arranged on the second gate insulating layer corresponding to the Above both ends of the grid, and partially overlap with the grid in the direction of the orthographic projection, the first electrode plate is arranged above the second gate insulating layer corresponding to the second electrode plate; Alternatively, the gate and the second electrode plate are arranged on the same layer, the first gate insulating layer completely covers the gate and does not cover the second electrode plate; the second gate insulating layer completely covers The second electrode plate does not cover the area corresponding to the gate; the source and the drain are arranged above the two ends of the first gate insulating layer corresponding to the gate, and are respectively Partially overlapping with the gate in the orthographic projection direction, the first pole plate is disposed above the second gate insulating layer corresponding to the second pole plate. 5. The array substrate according to claim 3 or 4, wherein the first gate insulating layer is formed of a silicon oxide material, and the first gate insulating layer has a single-layer structure; the second gate insulating layer It is formed by using at least one of silicon oxide material and silicon nitride material, and the second gate insulating layer has a single-layer structure or a stacked structure of multiple sub-layers. 6. The array substrate according to claim 5, wherein the thickness range of the first gate insulating layer is

The thickness range of the second gate insulating layer is

7. The array substrate according to claim 6, wherein the source, the drain and the first plate are made of low-temperature polysilicon material, and the source, the drain and the The thickness range of the first plate is

The grid and the second pole plate are formed of at least one material selected from molybdenum, molybdenum-niobium alloy, aluminum, aluminum neodymium alloy, titanium and copper, and the thickness range of the grid and the second pole plate is

8. The array substrate according to claim 7, wherein the array substrate further comprises a buffer layer, the buffer layer is a single-layer structure or a laminated structure of multiple sub-layers, and the buffer layer is made of silicon oxide material 1. At least one of silicon nitride materials is formed, and the buffer layer is arranged between the substrate and the source, the drain, and the first plate; or, the buffer layer is arranged between the between the substrate, the grid, and the second plate. 9. The array substrate according to claim 8, wherein the array substrate further comprises an interlayer insulating layer and an extraction electrode, the extraction electrode comprises a first electrode and a second electrode, and the interlayer insulation layer is provided Above the thin film transistor and the storage capacitor, a first via hole and a second via hole are opened in the interlayer insulating layer corresponding to the source electrode and the drain electrode, and the source electrode passes through The first via hole is electrically connected to the first electrode, and the drain is electrically connected to the second electrode through the second via hole. 10. A display device, comprising the array substrate according to any one of claims 1-9. 11. A method for preparing an array substrate, comprising the step of forming a thin film transistor and a storage capacitor on the substrate, the step of forming the thin film transistor includes the steps of forming a gate, a source, a drain, and forming a gate, a source, and a drain on the source, the The step of forming a gate insulating layer between the drain and the gate, the step of forming the storage capacitor includes forming a first electrode plate, a second electrode plate, and connecting the first electrode plate and the second electrode plate The step of forming a dielectric layer therebetween is characterized in that the dielectric constant of the gate insulating layer adjacent to the source and the drain is less than or equal to the dielectric constant of the dielectric layer. 12. The preparation method according to claim 11, wherein the step of forming the gate insulating layer comprises the step of forming a first gate insulating layer and a second gate insulating layer, the dielectric of the first gate insulating layer The constant is smaller than the dielectric constant of the second gate insulating layer, the first gate insulating layer is adjacent to the source and the drain, and the first electrode plate and the second electrode plate are formed on the second electrode. On the upper and lower sides of the second gate insulating layer, the dielectric layer is the part of the second gate insulating layer corresponding to the first pole plate and the second pole plate. 13. The preparation method according to claim 12, characterized in that, the preparation method specifically comprises the steps of: Step S1): forming a buffer layer on the substrate; Step S2): forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer to form a polysilicon layer, and performing a patterning process on the polysilicon layer to form a silicon island including an active layer and an electrode Graphics of silicon islands on the board; Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), the first gate insulating layer completely covers the source and the drain, and does not cover the first a polar plate, and forming the first polar plate in the silicon island of the polar plate by ion implantation; Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covering the first gate insulating layer and the first electrode plate; Alternatively, step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the first electrode plate, and does not cover the source electrode and the the region corresponding to the drain; Step S5): On the substrate after step S4), a pattern including a gate and a second electrode plate is formed on the second gate insulating layer, and the gate is formed corresponding to the source and the The region between the drains and at the same time partially overlaps the source and the drain in the orthographic projection direction, and the second electrode plate and the first electrode plate at least partially overlap in the orthographic projection direction; Alternatively, step S5): on the substrate after step S4), a pattern including a gate is formed on the first gate insulating layer, and the gate is formed corresponding to the source and the drain and at the same time partially overlap with the source and the drain in the direction of the orthographic projection; a pattern including a second plate is formed above the second gate insulating layer, and the second plate and The first polar plate at least partially overlaps in the orthographic projection direction; Step S6): on the substrate after step S5), the source and the drain are formed on both sides of the silicon island of the active layer by means of ion implantation. 14. The preparation method according to claim 12, characterized in that, the preparation method specifically comprises the following steps: Step S1): forming a buffer layer on the substrate; Step S2): forming a pattern including a gate and a second plate on the buffer layer; Step S3): forming a pattern including a first gate insulating layer on the substrate after step S2), and the first gate insulating layer completely covers the gate and does not cover the second electrode plate; Step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covering the first gate insulating layer and the second electrode plate; Alternatively, step S4): forming a pattern including a second gate insulating layer on the substrate after step S3), the second gate insulating layer completely covers the second electrode plate and does not cover the corresponding gate electrode. the area where Step S5): forming an amorphous silicon layer on the substrate after step S4), and crystallizing the amorphous silicon layer to form a polysilicon layer, performing a patterning process on the polysilicon layer to form an active layer Graphics of silicon islands and plate silicon islands; Step S6): forming the source and the drain on both sides of the active layer silicon island by ion implantation, the source and the drain are at least at least the same as the gate in the direction of the orthographic projection Partially overlapping: a first pole plate is formed in the pole plate silicon island by means of ion implantation, and the first pole plate overlaps with the second pole plate in the orthographic projection direction. 15. The preparation method according to claim 13 or 14, further comprising step S7): forming a pattern including an interlayer insulating layer and an extraction electrode above the thin film transistor and the storage capacitor, so that The lead-out electrode includes a first electrode and a second electrode, and a first via hole and a second via hole are respectively formed in a region above the interlayer insulating layer corresponding to the source electrode and the drain electrode, and the source electrode and the drain electrode are respectively formed. The first electrode is electrically connected through the first via hole, and the drain is electrically connected with the second electrode through the second via hole. 16. The preparation method according to claim 15, wherein forming the first gate insulating layer and the second gate insulating layer comprises plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition The corresponding first gate insulating layer film and the second gate insulating layer film are formed by electron cyclotron resonance chemical vapor deposition or sputtering, and the thickness range of the first gate insulating layer is

The thickness range of the second gate insulating layer is

17. The preparation method according to claim 16, wherein forming the gate comprises sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition to form the gate film, and form a pattern including the gate and the second plate through a patterning process, and the thickness range of the gate and the second plate is

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