CN104009041A

CN104009041A - NAND flash memory structure logic MTP compatible with CMOS technology

Info

Publication number: CN104009041A
Application number: CN201410264647.5A
Authority: CN
Inventors: 方钢锋
Original assignee: Su Zhoufeng Microtronics Of Speeding AS
Current assignee: Su Zhoufeng Microtronics Of Speeding AS
Priority date: 2014-06-13
Filing date: 2014-06-13
Publication date: 2014-08-27
Anticipated expiration: 2034-06-13
Also published as: CN104009041B

Abstract

The invention relates to an NAND flash memory structure logic MTP compatible with the CMOS technology. The NAND flash memory structure logic MTP comprises a PMOS transistor and a unit composed of an NCAP capacitor, wherein a drain electrode of the NCAP capacitor is connected with a programming line, and a floating gate of the NCAP capacitor is connected with a grid electrode of the PMOS transistor. Then, two or more units are combined together in a serial-connecting mode, and in other words, a drain electrode of each PMOS transistor is connected with a source electrode of the next PMOS transistor; the PMOS transistors which are connected in series end to end are further respectively connected with one PMOS transistor in series, substrates of all the PMOS transistors are connected together through an N trap, and substrates of all the NCAP capacitors are connected together through a P trap. The P trap can be or not be made in the deep N trap, and the P trap and a p-type substrate in the deep N trap are separated through the deep N trap. The NAND flash memory structure logic MTP compatible with the CMOS technology has the advantages that the PMOS transistors and the basic unit composed of the NCAP capacitors are connected in series so that the storage function can be achieved, connection between the source electrode and the drain electrode of each PMOS transistor can be omitted, the bit area of each basic unit is greatly reduced, and cost is reduced.

Description

Logic MTP with the nand flash memory structure of CMOS process compatible

Technical field

The present invention relates to a kind of non-volatility memory, especially a kind of can with the non-volatility memory of CMOS logic process compatibility, belong to technical field of integrated circuits.

Background technology

For SOC (system on a chip) (SoC) application, there is module integration to integrated circuit of many difference in functionalitys.Conventionally need non-volatility memory to store data, ID etc., but common embedded Flash needs special technique and expensive, the R&D cycle is long, and incompatible with common CMOS logic process.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, a kind of logic MTP of nand flash memory structure of and CMOS process compatible is provided, can reduce costs, individual bit area is little, and completely compatible with traditional semiconductor technology, CMOS logic process.

According to technical scheme provided by the invention, the logic MTP of described nand flash memory structure comprises: a PMOS transistor and a NCAP electric capacity component units, wherein the drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the transistorized grid of PMOS; Then combined by 2 or multiple this units in series, each PMOS transistor drain is connected to the transistorized source electrode of next PMOS; The PMOS transistor of respectively connecting again on the head and the tail PMOS of tandem compound transistor, the transistorized substrate of all PMOS links together by N trap, and the substrate of all NCAP electric capacity links together by P trap.

Described P trap can not be made in dark N trap, also can be made in dark N trap, isolates P trap and the p-type substrate of dark N trap the inside with dark N trap

Specifically, wherein the source electrode of first PMOS transistor PMOS1 is connected to the drain electrode of a PMOS pipe PMOS0, the grid of PMOS pipe PMOS0 is as the control line WL of byte, source electrode is as the control line BL of bit, the drain electrode of last PMOS transistor PMOSn connects the source electrode of a PMOS pipe PMOSn+1 again, the grid of PMOS pipe PMOSn+1 is as the control line SWL of the byte of drain electrode end, and drain electrode is as the control line SL of drain electrode end.N is more than or equal to 2 natural number.

Advantage of the present invention is: the logic MTP of this most basic enable nand gate is a PMOS transistor and NCAP component units, then this elementary cell is together in series and realizes memory function.Due to by the mode of series connection, can save the connection in PMOS transistor source and drain electrode, so just greatly reduce the area of the bit of single elementary cell, thereby reduced cost.

Brief description of the drawings

Fig. 1 is the structural representation of an embodiment of the present invention.

Fig. 2 is that P trap is not made in the generalized section in dark N trap.

Fig. 3 is the structure chart that P trap is made in another embodiment in dark N trap.

Fig. 4 is that P trap is made in the generalized section in dark N trap.

Fig. 5 is the example structure figure as an example of two unit example.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described.

The logic MTP of nand flash memory structure of the present invention comprises: PMOS transistor and a NCAP (NMOS is made in N trap) electric capacity component units, wherein NCAP electric capacity has floating boom, the drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the transistorized grid of PMOS; As the NCAP1 in Fig. 1 and PMOS1 component units, NCAP2 and PMOS2 component units, etc.NCAP electric capacity NCAP1, NCAP2 ..., NCAPn drain electrode connect respectively line program P1, P2 ... Pn.Then combined by 2 or multiple this units in series, each PMOS transistor drain is connected to the transistorized source electrode of next PMOS, as the PMOS1 connecting in Fig. 1, PMOS2 ..., PMOSn.The source electrode of first PMOS transistor PMOS1 is connected to the drain electrode of a PMOS pipe PMOS0, the grid of PMOS pipe PMOS0 is as the control line WL (word line) of byte, source electrode is as the control line BL (Bit line) of bit, the drain electrode of last PMOS transistor PMOSn connects the source electrode of a PMOS pipe PMOSn+1 again, the grid of PMOS pipe PMOSn+1 is as the control line SWL of the byte of drain electrode end, and drain electrode is as the control line SL of drain electrode end.The transistorized substrate of all PMOS links together by N trap (NW).The substrate of all NCAP electric capacity links together by P trap (PW).

Described P trap (Pwell) can not be made in dark N trap, and as Fig. 2, P trap and P type substrate (P-Sub) are communicated with; Also can be made in dark N trap (D-Nwell) inner, as Fig. 3 and 4, isolate P trap and the p-type substrate of dark N trap the inside with dark N trap; Dark N trap is what to beat in P type substrate depths, need to make a circle in P trap week beat N trap (Nwell) thus it is picked out, N trap links together with the transistorized substrate NW of PMOS.

PMOS transistor PMOS0, as transmission gate (pass gate), is made up of the control line (word line) of byte and the control line (Bit line) of bit.By the logic MTP (memory of multiple programmable) of an a string enable nand gate the most basic of other PMOS transistor compositions of this PMOS transistor series.

As shown in Figure 5, below with two unit Cell1, the structure of Cell2 composition is that example describes, Cell1 comprises NCAP1 and PMOS1, Cell2 comprises NCAP2 and PMOS2.

A, write PMOS pipe PMOS1 namely cell1 choose to write, cell2 is what do not write.

WL

BL

P1

P2

SWL

SL

NW

0V

7V

0V

Like this, hold at P1, and will produce larger pressure reduction between Poly1, to carrying out the voltage difference of FN tunneling (FN tunnelling) or the condition of electric field, electronics just passes through FN tunnelling from floating boom floating poly1 to P1 like this, the threshold V T of PMOS1 raises, and is relatively not easy energising.The corresponding cell2 not choosing, because P2 end is 0 with the voltage difference of the grid poly2 of PMOS2, does not have to carrying out the voltage difference of FN tunnelling or the condition of electric field, so PMOS2 does not become.

B, wipe (wipe two, wipe together)

WL

BL

P1

P2

SWL

SL

NW

5V

-5V

5V

Like this, between P1 end and Poly1, between P2 end and Poly2 (grid of PMOS2), will produce larger pressure reduction, to carrying out the voltage difference of FN tunnelling or the condition of electric field, electronics is just from P1 to floating boom floating poly1 like this, P2 is to floating boom floating poly2 by FN tunnelling, and the threshold V T of PMOS1 raises, and is relatively not easy energising.

C, read PMOS pipe PMOS1

WL

BL

P1

P2

SWL

SL

NW

0

1V

0

3V

Electric current is from SL to BL like this, judges by the size of electric current relatively state that P1 writes or the state of wiping of writing.

If as Fig. 3, shown in 4, P trap is made in dark N trap, benefit is, can on P trap, add negative pressure, has not so just needed high pressure, has just improved the simple and easy of transistorized reliability and periphery circuit.Such as, 7v can be divided into 3.5V and-3.5V comes, effect is the same.

Claims

1. with the logic MTP of the nand flash memory structure of CMOS process compatible, it is characterized in that, comprising: a PMOS transistor and a NCAP electric capacity component units, wherein the drain electrode of NCAP electric capacity connects line program, and the floating boom of NCAP electric capacity connects the transistorized grid of PMOS; Then combined by 2 or multiple this units in series, each PMOS transistor drain is connected to the transistorized source electrode of next PMOS; The PMOS transistor of respectively connecting again on the head and the tail PMOS of tandem compound transistor, the transistorized substrate of all PMOS links together by N trap, and the substrate of all NCAP electric capacity links together by P trap.

2. the logic MTP of the nand flash memory structure of as claimed in claim 1 and CMOS process compatible, it is characterized in that, wherein the source electrode of first PMOS transistor PMOS1 is connected to the drain electrode of a PMOS pipe PMOS0, the grid of PMOS pipe PMOS0 is as the control line WL of byte, source electrode is as the control line BL of bit, the drain electrode of last PMOS transistor PMOSn connects the source electrode of a PMOS pipe PMOSn+1 again, the grid of PMOS pipe PMOSn+1 is as the control line SWL of the byte of drain electrode end, drain electrode is as the control line SL of drain electrode end, and n is more than or equal to 2 natural number.

3. the logic MTP of the nand flash memory structure of as claimed in claim 1 and CMOS process compatible, is characterized in that, the P trap of the substrate of described NCAP electric capacity is separated by dark N trap with the P type substrate of whole chip.

4. the logic MTP of the nand flash memory structure of as claimed in claim 3 and CMOS process compatible, is characterized in that, while adding negative voltage, on NCAP electric capacity, can pass negative voltage on P trap.