CN103905039B - A kind of linear wide scope digital controlled oscillator being applied to FPGA - Google Patents

Abstract

A linear wide-range numerically controlled oscillator applied to FPGA. The core part of the numerically controlled oscillator is a ring oscillator, and the output frequency of the oscillator can be selected through a frequency selection control word. Utilizing the configurable feature of FPGA, the output center frequency of the numerically controlled oscillator can be flexibly changed, so that the output frequency of the numerically controlled oscillator can be continuously and linearly adjusted in a wide range.

Description

A Linear Wide Range Numerically Controlled Oscillator Applied to FPGA

technical field

The invention relates to a numerically controlled oscillator, in particular to a numerically controlled oscillator with a wide frequency range applied in FPGA.

Background technique

Digitally controlled oscillator (hereinafter referred to as DCO) is essentially an oscillator. The oscillation frequency is controlled by the frequency selection control word. The main difference between DCO and other oscillators is the use of digital control codes to control the output frequency. This feature makes DCO widely used in digital frequency synthesizer.

A typical ring oscillator usually uses an odd number of identical inverters. Figure 1 is a schematic diagram of a typical three-stage ring oscillator structure. The inverters in the oscillator are used to provide a fixed delay. The oscillation frequency of the oscillator is determined by Formula (1) gives.

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; osc</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; NT</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

In the formula, T _d refers to the delay provided by each inverter unit, and N indicates the number of inverter units included in the ring oscillator. Therefore, the oscillation frequency of the oscillator can be changed by changing the number N of inverters or the delay T _d provided by each stage of inverter. The delay Td of each delay unit can be obtained by formula (2),

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In the formula, _CL is the load capacitance of the inverter, ΔV is the output voltage swing of the inverter, and Id is the driving current of the load capacitance. It can be found from the formula (2) that the output frequency of the oscillator can be controlled by changing the load capacitance _CL or the driving current without changing the number N of delay units. The expression of the load capacitance _CL can be obtained by formula (3).

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; wxya</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; wxya</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; dbM</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; dbM</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\\ <span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gD</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gD</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; w</span>}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

In the formula, g, s, d, b represent the gate, source, drain and substrate of the MOS transistor respectively, and C _w represents the line capacitance. Usually, the load capacitance of the inverter output can be realized by MIM capacitance or MOS tube capacitance. However, with the development of semiconductor process technology, under the current sub-micron process conditions, the proportion of connection capacitance between devices It is getting bigger and bigger, so it is more and more difficult to change the oscillator frequency by changing the load capacitance. Therefore, the present invention realizes the digitally controlled oscillator DCO by controlling the magnitude of the driving current _Id for driving the load capacitance. This approach ensures that the DCO of the present invention has excellent linearity.

A large number of programmable logic resources are integrated in the field programmable logic gate array (hereinafter referred to as FPGA), and the use of DCO can provide high-quality clocks for the system. On the other hand, different users may require the FPGA to work at different clock frequencies, so the DCO is required to work reliably in a very wide frequency range. However, traditional oscillators can only be adjusted around a specific frequency, which limits the range and occasions in which the frequency synthesizer can be applied.

Contents of the invention

The problem solved by the technology of the present invention is: to overcome the deficiencies of the prior art, and to provide a numerically controlled oscillator with a wide frequency range applied in the FPGA. The DCO is mainly integrated in the FPGA. Using the programmable characteristics of the FPGA, it can flexibly The frequency selection control word of the DCO is modified, thereby greatly expanding the output frequency range of the oscillator, so that the DCO can work reliably in a very wide frequency range.

Technical solution of the present invention is:

A linear wide-range numerically controlled oscillator circuit for FPGA application, comprising a buffer, a multiplexer, an SRAM, and at least two tri-state inverter chains;

Each tri-state inverter chain has the same structure, including at least five tri-state inverters connected end to end; the output of the last tri-state inverter is the output of the tri-state inverter chain to which it belongs, and each The outputs of the three-state inverter chains are all connected together and fed to the input of the multiplexer;

In the n-th tri-state inverter chain, the first enabling terminals of each tri-state inverter are connected together, controlled by the nth bit of the externally input control signal, and the first enable terminal of each tri-state inverter The two enabling terminals are connected together, controlled by the nth bit of the inverse signal of the externally input control signal, n is a positive integer greater than or equal to 1, that is, n=1, 2, 3, 4, 5...;

Each tri-state inverter in the tri-state inverter chain is connected in parallel with the corresponding tri-state inverters in other tri-state inverter chains; the mth tri-state inverter in the tri-state inverter chain The output of is connected to the input of the multiplexer, m=3+i, i is an even number greater than or equal to 0, that is, i=0,2,4,6,8...

The SRAM is connected to the selection control terminal of the multiplexer, which is used to select the length of the three-state inverter chain, and the output feedback of the multiplexer is connected to the input of the three-state inverter chain, so that the three-state inverter chain constitutes The ring oscillator, at the same time, the output of the multiplexer is buffered and shaped by the buffer, which is the output of the digitally controlled oscillator circuit.

The number of the three-state inverter chains is the same as the number of bits of the external input control signal.

The tri-state inverter includes PMOS transistors M1, M3, M4, NMOS transistors M2, M5 and M6;

The source of the PMOS transistor M3 is connected to the drain of the NMOS transistor M5 as the input terminal of the three-state inverter, the sources of the PMOS transistors M1 and M4 are connected to the power supply, the sources of the NMOS transistors M2 and M6 are grounded, and the gate of the PMOS transistor M4 The pole and the gate of the NMOS transistor M5 are connected to the external input control signal, and the gate of the PMOS transistor M3 and the gate of the NMOS transistor M6 are connected to the inverse signal of the external input control signal;

The drain of the PMOS transistor M3, the drain of the PMOS transistor M4, and the gate of the PMOS transistor M1 are connected together, the source of the NMOS transistor M5, the drain of the NMOS transistor M6, and the gate of the NMOS transistor M2 are connected together, and the PMOS transistor M2 is connected together. The drain of M1 is connected to the drain of NMOS transistor M2 as the output of the tri-state inverter.

The advantage of the present invention compared with prior art is:

The DCO of the present invention is an all-digital control oscillator, and the central frequency of the oscillator can be flexibly set by using the programmable characteristics of FPGA, and the desired frequency output can be obtained by changing the frequency selection control word D[7:0] of the DCO . Compared with the traditional oscillator, the DCO of the present invention has a wider frequency adjustment range and better linearity.

Description of drawings

Fig. 1 is a schematic structural diagram of a traditional ring oscillator;

Fig. 2 is the principle schematic diagram of DCO circuit of the present invention;

Fig. 3 is a schematic diagram of the tri-state inverter circuit principle of the present invention;

FIG. 4 is a schematic diagram of the relationship between the output frequency of the DCO and the frequency selection control word in the present invention.

detailed description

The DCO of the present invention introduces a special frequency selection control signal, uses the configuration code of the FPGA to control, and realizes the output of different frequencies by changing the control word of the DCO.

A linear wide-range digitally controlled oscillator circuit applied to FPGA provided by the present invention is shown in FIG. 2 . When using the DCO in Figure 2, according to the configuration register information, the output frequency of the DCO can be adjusted in a series of intervals. The output frequency range is the sum of all intervals, and the final oscillator can be in a wider interval. internally regulated linearly.

As shown in FIG. 2, the DCO of the present invention includes a buffer 210, a multiplexer 220, an SRAM 230, and at least two tri-state inverter chains. The first tri-state inverter chain includes tri-state inverters 201, 202, 203, 204, 205... The second tri-state inverter chain includes tri-state inverters 211, 212, 213, 214, 215...;

The structure of each tri-state inverter chain is the same, including at least five tri-state inverters connected end to end, for example, the output of the tri-state inverter 201 is connected to the input of the tri-state inverter 202, and the tri-state inverter The output of the phaser 202 is used as the input of the tri-state inverter 203 again, and so on, the tri-state inverters 201, 202, 203, 204, 205, 206 and 207 are connected end to end in turn to form the first tri-state inverter chain , in the same way, the output of the tri-state inverter 211 is used as the input of the tri-state inverter 212, and the output of the tri-state inverter 212 is connected to the input of the tri-state inverter 213, so that the tri-state inverter 211 , 212, 213, 214, 215, 216 and 217 are connected end to end in turn to form a second tri-state inverter chain;

In the n-th tri-state inverter chain, the first enabling terminals of each tri-state inverter are connected together, controlled by the nth bit of the externally input control signal, and the first enable terminal of each tri-state inverter The two enabling terminals are connected together, controlled by the nth bit of the inverse signal of the externally input control signal, n is a positive integer greater than or equal to 1, that is, n=1,2,3,4,5...for example , the first enabling terminals of the tri-state inverters 201, 202, 203, 204, 205, 206 and 207 are connected to the control signal D0, and the tri-state inverters 201, 202, 203, 204, 205, 206 and 207 The second enabling terminal is connected to the control signal Db0;

Each of the three-state inverters in the three-state inverter chain is connected in parallel with the corresponding three-state inverters in the other three-state inverter chains, that is, the inputs of the three-state inverters 201 and 211 are connected, and the three-state The outputs of the inverters 201 and 211 are connected, similarly, the inputs of the three-state inverters 202 and 212 are connected, the outputs of the three-state inverters 202 and 212 are connected, and so on;

The output of the last tri-state inverter of each tri-state inverter chain is the output of the tri-state inverter chain to which it belongs, and the output of the mth tri-state inverter in the tri-state inverter chain is connected to The input terminal of the multiplexer 220, m=3+i, i is an even number greater than or equal to 0, that is, i=0, 2, 4, 6, 8... For example, the three-state inverters 203, 205 and 207 The output is connected to the data input of the multiplexer 220;

The SRAM230 is connected to the selection control terminal of the multiplexer for selecting the length of the three-state inverter chain, the number of bits of the SRAM230 is determined by the length of the three-state inverter chain, and the output feedback of the multiplexer 220 is connected to the three The input of the three-state inverter chain makes the three-state inverter chain constitute a ring oscillator. At the same time, the output of the multiplexer 220 is output after being buffered and shaped by the buffer 210, which is the output OUT of the numerically controlled oscillator circuit;

The number of the three-state inverter chains is the same as the number of bits of the external input control signal;

Described tri-state inverter all adopts the tri-state inverter structure shown in Fig. 3, and the width, length ( W, L) are the same, the size of the three-state inverters of different chains is different, for example, the size of the three-state inverters gradually increases from 201 to 271, so as to ensure that the output frequency of the numerically controlled oscillator has a linear relationship with the frequency selection control word .

As shown in FIG. 3, the tri-state inverter includes PMOS transistors M1, M3, M4, and NMOS transistors M2, M5, and M6;

The source of the PMOS transistor M3 is connected to the drain of the NMOS transistor M5 as the input terminal of the tri-state inverter, denoted as CLK_IN, the sources of the PMOS transistors M1 and M4 are connected to the power supply, the sources of the NMOS transistors M2 and M6 are grounded, and the PMOS The gate of the transistor M4 and the gate of the NMOS transistor M5 are connected to the external input control signal D, and the gate of the PMOS transistor M3 and the gate of the NMOS transistor M6 are connected to the inverse signal Db of the external input control signal;

The drain of the PMOS transistor M3, the drain of the PMOS transistor M4, and the gate of the PMOS transistor M1 are connected together, denoted as node N1, the source of the NMOS transistor M5, the drain of the NMOS transistor M6, and the gate of the NMOS transistor M2 Connected together, denoted as node N2, the drain of the PMOS transistor M1 and the drain of the NMOS transistor M2 are connected as the output of the tri-state inverter, denoted as CLK_OUT;

The function of PMOS transistor M3 and NMOS transistor M2 is similar to an inverter, and the function of PMOS transistor M3 and NMOS transistor M5 is similar to a transmission gate. The control signals D and Db control the propagation of the clock signal from input to output. If D=1, Db=0, the input clock signal can pass through the tri-state inverter; on the contrary, when D=0 and Db=1, both the PMOS transistor M1 and the NMOS transistor M2 are turned off, thereby disconnecting the connection between the output CLK_OUT and the input;

Different from traditional tri-state inverters, the introduction of PMOS transistor M4 and NMOS transistor M6 ensures that under the conditions of D=0 and Db=1, the gate of PMOS transistor M1 is connected to Vdd, and the gate of NMOS transistor M2 is connected to Gnd In this way, it can ensure that the PMOS transistor M1 and the NMOS transistor M2 can be completely turned off, and prevent the node N1 and the node N2 from floating when D=0 and Db=1, and the PMOS transistor M1 and the NMOS transistor M2 cannot be completely turned off, so that the output Terminal CLK_OUT will also be charged or discharged.

As shown in FIG. 4 , it is a schematic diagram of the relationship between the output clock frequency and the frequency selection control word when the DCO of the present invention is working, and the output of the DCO and the frequency selection control word are approximately linear. At the frequency selection control word D[7:0]=128, the output frequency of the DCO is f _o .

Claims (2)

1. A linear wide-range digitally controlled oscillator circuit applied to FPGA is characterized in that: comprise buffer, multiplexer, SRAM and at least two tri-state inverter chains; Each tri-state inverter chain has the same structure, including at least five tri-state inverters connected end to end; the output of the last tri-state inverter is the output of the tri-state inverter chain to which it belongs, and each The outputs of the three-state inverter chains are all connected together and fed to the input of the multiplexer; In the qth three-state inverter chain, the first enabling terminals of each three-state inverter are connected together, controlled by the nth bit of the externally input control signal, and the first enable terminal of each three-state inverter The two enabling terminals are connected together, controlled by the nth bit of the inverse signal of the externally input control signal, n is a positive integer greater than or equal to 1, that is, n=1, 2, 3, 4, 5...; q is the number of tri-state inverter chains; Each tri-state inverter in the tri-state inverter chain is connected in parallel with the corresponding tri-state inverters in other tri-state inverter chains; the mth tri-state inverter in the tri-state inverter chain The output of is connected to the input terminal of the multiplexer, m=3+i, i is an even number greater than or equal to 0, that is, i=0,2,4,6,8... The SRAM is connected to the selection control terminal of the multiplexer, which is used to select the length of the three-state inverter chain, and the output feedback of the multiplexer is connected to the input of the three-state inverter chain, so that the three-state inverter chain constitutes A ring oscillator, meanwhile, the output of the multiplexer is output after being buffered and shaped by a buffer, which is the output of the numerically controlled oscillator circuit; The tri-state inverter includes PMOS transistors M1, M3, M4, NMOS transistors M2, M5 and M6; The source of the PMOS transistor M3 is connected to the drain of the NMOS transistor M5 as the input terminal of the three-state inverter, the sources of the PMOS transistors M1 and M4 are connected to the power supply, the sources of the NMOS transistors M2 and M6 are grounded, and the gate of the PMOS transistor M4 The pole and the gate of the NMOS transistor M5 are connected to the external input control signal, and the gate of the PMOS transistor M3 and the gate of the NMOS transistor M6 are connected to the inverse signal of the external input control signal; The drain of the PMOS transistor M3, the drain of the PMOS transistor M4, and the gate of the PMOS transistor M1 are connected together, the source of the NMOS transistor M5, the drain of the NMOS transistor M6, and the gate of the NMOS transistor M2 are connected together, and the PMOS transistor M2 is connected together. The drain of M1 is connected to the drain of NMOS transistor M2 as the output of the tri-state inverter. 2. A kind of linear wide-range digitally controlled oscillator circuit applied to FPGA according to claim 1, characterized in that: the number of said three-state inverter chains is the same as the number of bits of the external input control signal.