CN103887328A - Thin film transistor array substrate, liquid crystal display device and manufacturing method - Google Patents

Abstract

The invention discloses a low-temperature polysilicon thin film transistor array substrate, a liquid crystal display device and a corresponding manufacturing method. In the thin film transistor array substrate, the metal layer used to form the source and drain electrodes of the thin film transistor and the data line of the array substrate is formed on the transparent conductive layer of the pixel electrode, so that the pattern of the via hole only needs to be performed once in the manufacturing process At the same time, since the metal layer and the transparent conductive layer are stacked together, the semi-transparent mask process can be used to etch to realize the patterning of the two layers, thereby reducing the number of mask exposure processes and reducing the process cost. difficulty and cost.

Description

Thin film transistor array substrate, liquid crystal display device and manufacturing method

technical field

The invention relates to the field of low-temperature polysilicon liquid crystal display, in particular to a low-temperature polysilicon thin film transistor array substrate, a liquid crystal display device and a manufacturing method thereof.

Background technique

The low temperature polysilicon thin film transistor (LTPS-TFT, Low Temperature Poly-Silicon Thin Film Transistor) array substrate used in the existing low temperature polysilicon liquid crystal display device usually uses the structure shown in FIG. 1 . As shown in FIG. 1, the thin film transistor array substrate 10 includes a substrate 11, an active layer 12, a gate insulating layer 13, a patterned first metal layer 14 including a gate pattern 14a and a gate line pattern 14b, and a first protective layer. 15, the second metal layer 16 patterned on the first protective layer 15, the second protective layer 17 and the transparent conductive layer 181 on the second protective layer 17 for forming a common electrode, covering the transparent conductive layer 181 The passivation layer 19 and the transparent conductive layer 182 formed on the passivation layer 19 for forming a pixel electrode. Wherein, the active layer 12 is used to form the active region of the thin film transistor, and the second metal layer 16 is connected with the active region through the via hole penetrating the first protective layer 15 and the gate insulating layer 13 to form the source and the source electrode of the thin film transistor. Drain and data lines connected to source. The transparent conductive layer 182 is connected to the drain through the via hole penetrating the second protection layer, so that the transparent conductive layer 182 is electrically connected to the drain. Meanwhile, the active layer 12 extends below the gate line 142 , and forms a storage capacitor with a part of the gate line 142 .

In the manufacturing process of the thin film transistor array substrate with the structure shown in Figure 1, it needs to go through the formation of polysilicon layer pattern (Mask1), the definition of channel doping region (Mask2), the definition of N-type ion implantation region (Mask3), the first metal layer Gate and gate pattern formation (Mask4), definition of P-type ion implantation region (Mask5), formation of via holes exposing the polysilicon layer (Mask6), second metal layer source, drain and data line pattern formation (Mask7), Formation of via holes exposing the drain (Mask8), patterning of the transparent conductive layer forming the common electrode layer (Mask9), patterning of the passivation layer (Mask10), patterning of the transparent conductive layer forming the pixel electrode (Mask11), etc. Mask exposure process. A large number of masking processes will significantly increase the manufacturing complexity and cost. At the same time, the difference in mutual coverage between the layers of the existing array substrate structure will lead to poor display effects and increase the difficulty of the process.

Contents of the invention

The technical problem to be solved by the present invention is to provide a thin film transistor array substrate, a liquid crystal display device and a manufacturing method, reduce the number of mask exposures in the manufacturing process, and reduce the process complexity and manufacturing cost.

For this reason, the invention discloses a low temperature polysilicon thin film transistor array substrate, comprising:

Substrate;

an active layer formed on the substrate;

a gate insulating layer covering the active layer;

a patterned first metal layer disposed on the gate insulating layer, the first metal layer constitutes the gate of the thin film transistor and the gate line of the array substrate;

a protective layer covering the grid and gate lines;

a patterned first transparent conductive layer disposed on the protective layer, the first transparent conductive layer constitutes a pixel electrode of the array substrate;

A patterned second metal layer disposed on the first transparent conductive layer and electrically connected to the active layer through a via hole, the second metal layer constitutes the drain and source of the thin film transistor and the array substrate data line.

Preferably, the patterned active layer includes an active region and a storage capacitor region;

The active region of the active layer is located below the gate and includes a source region, a drain region and a channel region, and the source of the thin film transistor is connected to the active layer of the source region through a first via hole. Electrically connected, the drain of the thin film transistor is electrically connected to the active layer of the drain region through a second via hole;

The storage capacitor region is located under the gate line.

Preferably, the storage capacitor region of the active layer is electrically connected to the drain through a third via hole.

Preferably, the storage capacitor region of the active layer is directly electrically connected to the drain region of the active region as a whole.

Preferably, the array substrate further includes a passivation layer covering the second metal layer and the first transparent conductive layer, and a second transparent conductive layer disposed on the passivation layer, the second transparent conductive layer constitutes common electrode.

Preferably, the second transparent conductive layer further includes a redundant common electrode extending along the direction of the data line and at least partially overlapping the data line, and the redundant common electrode is electrically isolated from the common electrode.

Preferably, the protection layer includes an interlayer dielectric insulating layer covering the first metal layer and a planarization layer formed on the interlayer dielectric insulating layer.

Preferably, a buffer layer is further included between the substrate and the active layer.

The invention also discloses a low-temperature polysilicon liquid crystal display device, which comprises the above-mentioned thin film transistor array substrate.

The invention also discloses a method for manufacturing a low-temperature polysilicon thin film transistor array substrate, including:

forming a patterned active layer on the substrate;

forming a gate insulating layer on the active layer;

forming a patterned first metal layer on the gate insulating layer, the first metal layer constitutes the gate of the thin film transistor and the gate line of the array substrate;

forming a protection layer on the gate and gate lines;

patterning the passivation layer and the gate insulating layer to form via holes exposing part of the active layer;

forming a patterned first transparent conductive layer on the protective layer, and forming a patterned second metal layer on the first transparent conductive layer;

Wherein, the first transparent conductive layer constitutes a pixel electrode of the array substrate, and the second metal layer constitutes a drain and a source of a thin film transistor and a data line of the array substrate.

Preferably, forming a patterned active layer on the substrate includes:

Depositing an amorphous silicon layer on the substrate;

The amorphous silicon layer forms an active layer through a laser thermal annealing process, a masking process and a doping process;

patterning the active layer to form the active region of the thin film transistor and the storage capacitor region located below the gate line;

Channel doping is performed on the active region of the active layer to form a source region, a drain region and a channel region, and the source of the film transistor is connected to the source of the active layer through the first via hole. The electrode region is electrically connected, and the drain of the film transistor is electrically connected to the drain region of the active layer through the second via hole.

Preferably, the storage capacitor region of the active layer is electrically connected to the drain through a third via hole.

Preferably, the storage capacitor region of the active layer is directly electrically connected to the drain region of the active region as a whole.

Preferably, the method also includes:

forming a passivation layer on the second metal layer and the first transparent conductive layer;

A second transparent conductive layer is formed on the passivation layer, and the second transparent conductive layer constitutes a common electrode of the array substrate.

Preferably, forming the second transparent conductive layer on the passivation layer further includes:

The second transparent conductive layer is patterned to form a redundant common electrode extending along the direction of the data line and at least partially overlapping the data line, the redundant common electrode is electrically isolated from the common electrode.

Preferably, forming a protective layer on the gate and gate lines includes:

forming an interlayer dielectric insulating layer covering the first metal layer;

A planarization layer is formed on the interlayer dielectric insulating layer.

Preferably, forming a patterned first transparent conductive layer on the protective layer and forming a patterned second metal layer on the first transparent conductive layer comprises:

forming a first transparent conductive layer;

forming a second metal layer on the first transparent conductive layer;

coating photoresist on the second metal layer;

The photoresist is exposed using a gray-tone mask or a semi-transparent mask, and after development, a photoresist is completely retained, a photoresist is semi-retained and a photoresist is completely removed, wherein the photoresist The glue fully reserved area corresponds to the source electrode, the drain electrode and the data line area; the photoresist half reserved area corresponds to the pixel electrode area;

The patterned first transparent conductive layer and the second metal layer are obtained by etching.

Preferably, the method further includes: forming a buffer layer between the substrate and the active layer.

In the present invention, by changing the structure of the low-temperature polysilicon thin film transistor array substrate, the metal layer used to form the source electrode, the drain electrode and the data line is formed on the transparent conductive layer of the pixel electrode, so that only one via hole is required in the manufacturing process At the same time, since the metal layer and the transparent conductive layer are stacked together, the semi-transparent mask process can be used to etch to realize the patterning of the two layers, thereby reducing the number of mask exposure processes and reducing the process difficulty and cost. At the same time, since the drain electrode is directly stacked and connected to the pixel electrode, compared with the via hole connection, the connection electrical characteristics are improved, and the display performance of the array substrate is improved.

Description of drawings

1 is a schematic cross-sectional view of an existing low-temperature polysilicon thin film transistor array substrate;

2 is a schematic cross-sectional view of a low temperature polysilicon thin film transistor array substrate according to the first embodiment of the present invention;

3 is a schematic cross-sectional view of a low-temperature polysilicon thin film transistor array substrate according to a second embodiment of the present invention;

FIG. 4 is a schematic top view of a low-temperature polysilicon thin film transistor array substrate according to a second embodiment of the present invention;

5 is a schematic cross-sectional view of a low temperature polysilicon thin film transistor array substrate according to a third embodiment of the present invention;

6 is a schematic cross-sectional view of a low-temperature polysilicon thin film transistor array substrate according to a fourth embodiment of the present invention;

FIG. 7 is a schematic top view of a low-temperature polysilicon thin film transistor array substrate according to a fourth embodiment of the present invention;

8 is a flow chart of a method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to a fifth embodiment of the present invention;

FIG. 9 is a flowchart of a manufacturing method of a low temperature polysilicon thin film transistor array substrate according to the sixth embodiment of the present invention.

Detailed ways

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

FIG. 2 is a schematic cross-sectional view of the low temperature polysilicon thin film transistor array substrate according to the first embodiment of the present invention. As shown in FIG. 2, the array substrate 20 includes a substrate 21; a patterned active layer 22; a gate insulating layer 23 covering the active layer; a patterned first metal layer 24 disposed on the gate insulating layer The protective layer 25 covering the first metal layer; the patterned first transparent conductive layer 26 arranged on the protective layer 25 and the patterned second metal arranged on the first transparent conductive layer 26 Layer 27.

Wherein, the first metal layer 24 includes a gate 24a and a gate line 24b, and the gate line 24b is used as a scan line of the array substrate to selectively gate the thin film transistor to drive the pixel electrode to work according to the scan signal of the driver.

The active layer 22 includes an active region 22a and a storage capacitor region 22b. The active region 22a is located under the gate and includes a source region 22a1, a drain region 22a2 and a channel region 22a3. Meanwhile, the storage capacitor region 22b is located under the gate line 24b, and is electrically connected to the drain of the second metal layer 27 through the third via hole 28c. The storage capacitor region 22b of the active layer and the gate line 24b above it form a storage capacitor of the thin film transistor pixel driving circuit.

The above is only one of the embodiments, and the storage capacitor region 22b of the active layer and the drain region 22a2 of the active region 22a can also be directly electrically connected as a whole without connecting the two via holes. or electrically connected together.

The first transparent conductive layer 26 includes the pixel electrode part of the array substrate 20 . The second metal layer 27 constitutes the source 27 a and the drain 27 b of the thin film transistor and the data line 27 c of the array substrate 20 . The second metal layer 27 is arranged on the transparent conductive layer, and is conductively connected with the active layer through a via hole so as to form the corresponding part as a drain electrode and a source electrode, and the source electrode 27a of the thin film transistor is connected with the active layer through the first via hole 28a. The source region 22a1 of the active layer is electrically connected, and the drain 27b of the thin film transistor is electrically connected to the drain region 22a2 of the active layer through a second via hole 28b.

At the same time, in a preferred implementation of this embodiment, the photoresist of the source electrode 27a, the drain electrode 27b and the corresponding part of the data line 27c of the second metal layer 27 are fully reserved by using a semi-transparent mask exposure process, and the first transparent The photoresist in the part corresponding to the pixel electrode of the conductive layer 26 is half reserved, and the photoresist in the remaining part is not reserved. Therefore, the first transparent conductive layer 26 and the second metal layer 27 can be simultaneously patterned by one etching, which simplifies the manufacturing process. At the same time, because it is formed by one patterning process, the first transparent conductive layer 26 under the pattern of the second metal layer 27 is retained, and thus the pixel electrode of the first transparent conductive layer 26 is electrically connected to the drain electrode 27b.

The protection layer 25 generally includes an interlayer dielectric insulating layer 25a for protecting the gate and a planarization layer 25b for planarization, and the planarization layer 25b is usually formed of organic materials.

Therefore, in this embodiment, by changing the structure of the low-temperature polysilicon thin film transistor array substrate, the second metal layer for forming the source electrode, the drain electrode and the data line is formed on the transparent conductive layer of the pixel electrode, so that in the manufacturing process It is only necessary to manufacture the via hole once. Specifically, the protective layer and the gate insulating layer can be exposed to the same mask to form the via hole. At the same time, since the second metal layer and the first transparent conductive layer are stacked together, it can The semi-transparent mask process is used to etch to realize the patterning of two layers, thereby reducing the number of mask exposure processes and reducing process difficulty and cost. At the same time, since the drain electrode is directly stacked and connected to the pixel electrode, compared with the via hole connection, the connection electrical characteristics are improved, and the display performance of the array substrate is improved.

3 is a schematic cross-sectional view of a low-temperature polysilicon thin film transistor array substrate according to a second embodiment of the present invention. FIG. 4 is a schematic top view of a low temperature polysilicon thin film transistor array substrate according to a second embodiment of the present invention. As shown in Figures 3 and 4, the array substrate 30 includes a substrate 31; a patterned active layer 32; a gate insulating layer 33 covering the active layer; The first metal layer 34; the interlayer dielectric insulating layer (ILD, Inter-Layer Dielectric) 35 covering the first metal layer; the planarization layer (PLN) 36 covering the interlayer dielectric insulating layer; arranged on the The patterned first transparent conductive layer 37 on the planarization layer (PLN) 36 and the patterned second metal layer 38 disposed on the first transparent conductive layer 37 .

Different from the first embodiment, the array substrate of this embodiment is a thin film transistor array substrate for an in-plane switching (IPS, In-PlaneSwitch) liquid crystal display. Thus, the array substrate 30 further includes a passivation layer 391 covering the first transparent conductive layer 37 and the second metal layer 38 and a second transparent conductive layer 392 formed on the passivation layer 391 . The second transparent conductive layer 392 forms an entire surface electrode in the pixel display area, which constitutes a common electrode of the array substrate.

Meanwhile, the first metal layer 34 includes a gate 34a and a gate line 34b, and the gate line 34b is used as a scan line of the array substrate to selectively gate the thin film transistor to drive the pixel electrode to work according to the scan signal of the driver.

The patterned active layer 32 includes an active region 32a and a storage capacitor region 32b, the active region 32a is located under the gate and includes a source region 32a1, a drain region 32a2 and a channel region 32a3. Meanwhile, the storage capacitor region 32b is located under the gate line pattern 34b and is electrically connected to the drain pattern of the second metal layer 38 through the third via hole 3A3. The storage capacitor region 32b of the active layer and the gate line 34b above it form a storage capacitor of the thin film transistor pixel driving circuit.

The above is only an example of an embodiment, and the storage capacitor region 32b of the active layer and the drain region 32a2 of the active region 32a can also be directly electrically connected as a whole without connecting the drain region 32a through the third via hole. The two are electrically connected together.

The first transparent conductive layer 37 constitutes a pixel electrode of the array substrate 30 . Since it is an array substrate for an IPS-type low-temperature polysilicon liquid crystal display, the pixel electrodes of the first transparent conductive layer 37 may be in the shape of strips, fishbone or broken lines.

The second metal layer 38 constitutes the source 38 a and the drain 38 b of the thin film transistor and the data line 38 c of the array substrate 30 . The second metal layer 38 is disposed on the first transparent conductive layer 37, and is conductively connected to the active layer through a via hole so as to form the corresponding part as a drain and a source, and the source 38a of the thin film transistor passes through the first transparent conductive layer. A via 3A1 is electrically connected to the source region 32a1 of the active layer, and the drain 38b of the thin film transistor is electrically connected to the drain region 32a2 of the active layer through a second via 3A2.

At the same time, in this embodiment, the semi-transparent mask exposure process is used to make the photoresist of the source electrode, the drain electrode and the corresponding part of the data line of the second metal layer 38 all remain, and the corresponding part of the pixel electrode of the first transparent conductive layer 37 Half of the photoresist remains, and the rest of the photoresist does not. Thus, the first transparent conductive layer 37 and the second metal layer 38 can be simultaneously patterned by one etching, which simplifies the manufacturing process. At the same time, because it is formed by one patterning process, the first transparent conductive layer 37 under the pattern of the second metal layer 38 is retained, and thus the pixel electrode of the first transparent conductive layer 37 is electrically connected to the drain electrode 38b.

Among them, in a preferred implementation of this embodiment, the active layer of the thin film transistor is projected on the deposited amorphous silicon layer by using the molecular laser as the heat source, and the laser beam with uniform energy distribution generated after the laser passes through the projection system. Glass substrate, when the amorphous silicon film absorbs the energy of the excimer laser, the atoms are rearranged to form a polysilicon structure, and then the semiconductor structure of the active layer is formed by channel doping.

In a preferred implementation of this embodiment, the interlayer dielectric insulating layer 35 is preferably made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ). The first metal layer 34 used to form gates and gate lines and the second metal layer used to form source electrodes, drain electrodes and data lines are preferably molybdenum (Mo), titanium-aluminum-titanium alloy (Ti-Al-Ti) Or a combination thereof is formed as a preparation material.

In this embodiment, the optimized structure of the thin film transistor array substrate is applied to the array substrate of the IPS liquid crystal display device, and the passivation layer and the second transparent conductive layer as the common electrode are covered on the first transparent conductive layer forming the pixel electrode. The structure places the common electrode above the pixel electrode, so that it is not necessary to pattern the passivation layer on the common electrode in order to form the connection via hole between the pixel electrode and the drain as in the prior art solution, further reducing the IPS type. The number of masking processes for the array substrate of the liquid crystal display device reduces process difficulty and manufacturing cost.

5 is a schematic cross-sectional view of a low temperature polysilicon thin film transistor array substrate according to a third embodiment of the present invention. As shown in FIG. 5 , different from Embodiment 1, the array substrate 50 in this embodiment adopts a double-gate structure, and the active layer 51 is formed with two channel regions 511 and 512 through channel doping. Correspondingly, the first A metal layer 52 forms two gates 522 and 523 respectively above the two channel regions, and the source 531 of the second metal layer 53 is electrically connected to the source region 513 of the active layer through the first via hole 541 , the drain 532 of the second metal layer 53 is electrically connected to the drain region 514 of the active layer through the second via hole 542 . Compared with the thin film transistor structure of one gate structure, the number of junctions between the source and drain increases, and the electric field strength applied to both ends of each junction decreases, so the thin film transistor in the off state The leakage current is reduced and the switching performance of the thin film transistor is optimized.

FIG. 6 is a schematic cross-sectional view of a thin film transistor array substrate according to a fourth embodiment of the present invention. FIG. 7 is a schematic top view of a thin film transistor array substrate according to a fourth embodiment of the present invention. As shown in Figures 6 and 7, on the basis of the second embodiment, the array substrate 60 in this embodiment has a redundant common electrode 611 formed on the second transparent conductive layer 61, and other parts of the second transparent conductive layer 61 as the common electrode 612 . Wherein, the redundant common electrode 611 extends along the direction of the data line 62 and at least partially overlaps the data line 62 , and the redundant common electrode 611 is electrically isolated from the common electrode 612 . The redundant common electrode 611 is overlapped with the data line 62 , so it is greatly affected by the current signal of the data line 62 . However, since the redundant common electrode 611 and the common electrode 612 are not connected to each other, there is no electrical connection, therefore, the signal on the data line 62 can be suppressed from forming an electric field with the common electrode 612, and the impact on the pixel electrode and the common electrode 612 can be reduced or eliminated. The influence of the electric field.

In this embodiment, a redundant common electrode 611 extending along the direction of the data line 62 on the second transparent conductive layer 61 and at least partially overlapping the data line 62 is used, and the redundant common electrode 611 is electrically connected to the common electrode 612. Sexual isolation suppresses the influence of the data line signal on the electric field of the common electrode 612, and improves the stability of the electric field of the array substrate.

The thin film transistor array substrate mentioned in the above embodiments can be used as a component of a liquid crystal display device, and the liquid crystal display device includes a backlight module, the array substrate mentioned in the above embodiment, and a liquid crystal layer and an optical filter array substrate.

FIG. 8 is a flowchart of a manufacturing method of a thin film transistor array substrate according to a fifth embodiment of the present invention. As shown in Figure 8, the manufacturing method includes the following steps:

Step 100, forming a patterned active layer on the substrate.

Specifically, step 100 may specifically include the following steps:

Step 110 , depositing an amorphous silicon layer on the substrate, and forming a polysilicon layer (ie, an active layer) through a laser thermal annealing process, a masking process, and a doping process.

Step 120, forming the active region of the thin film transistor and the storage electrode region under the gate line through the patterning process of glue coating, mask exposure, etching and ashing;

Step 130, performing channel doping on the active region by applying glue and exposing a mask, and then defining an N-type ion implantation region on the active layer by applying glue and exposing a mask, and finally injecting N-type ions, A source region, a drain region and a channel region are formed. The source of the film transistor is electrically connected to the active layer of the source region through the first via hole, and the drain of the film transistor is electrically connected to the active layer of the drain region through the second via hole. connect. The storage capacitor region of the active layer is electrically connected to the drain of the second metal layer through a third via hole.

The above is only an example of an embodiment, and the storage capacitor region 32b of the active layer and the drain region 32a2 of the active region 32a can also be directly electrically connected as a whole without connecting the drain region 32a through the third via hole. The two are electrically connected together. In a preferred embodiment of the present invention, the active layer is a polysilicon layer. By using molecular laser as a heat source, the laser beam with uniform energy distribution generated after the laser passes through the projection system is projected on the deposited amorphous silicon layer. Glass substrate, when the amorphous silicon film absorbs the energy of the excimer laser, the atoms are rearranged to form a polysilicon structure.

Step 200, forming a gate insulating layer on the active layer.

Preferably, the gate insulating layer is formed of silicon oxide or silicon nitride.

Step 300 , forming a patterned first metal layer on the gate insulating layer, the first metal layer constituting the gate of the thin film transistor and the gate line of the array substrate.

Specifically, step 300 includes firstly sputtering to form a first metal layer, and then forming gates and gate lines by using a patterning process of glue coating, mask exposure, etching, and ashing.

In a preferred implementation of this embodiment, after the patterning of the first metal layer is formed, it is necessary to further define the implantation region of P-type ions by applying glue and mask exposure, and implant a small amount of P-type ions.

Preferably, the first metal layer is formed using molybdenum, titanium-aluminum-titanium alloy or a combination thereof.

Step 400, forming a protection layer on the gate and the gate line.

Wherein, forming the protection layer on the first metal layer specifically includes: first forming an interlayer dielectric insulating layer covering the first metal layer; and then forming a planarization layer on the interlayer dielectric insulating layer. The interlayer dielectric insulating layer is preferably made of silicon nitride or silicon oxide, and the planarization layer is preferably made of insulating organic material.

Step 500 , pattern the protection layer and the gate insulating layer to form via holes exposing part of the source region, the drain region and the storage capacitor region of the active layer.

In this embodiment, since the drain and source of the thin film transistor to be manufactured are located above the first transparent conductive layer, and the two are in direct contact to form an electrical connection, the penetration protection layer can be formed by one etching process The electrical connection between the drain electrode, the active region and the pixel electrode is directly realized through the via holes in the gate isolation layer. As a result, the number of mask exposure processes is reduced, and the process difficulty and cost are reduced. At the same time, since the drain electrode is directly stacked and connected to the pixel electrode, compared with the via hole connection, the connection electrical characteristics are improved, and the display performance of the array substrate is improved.

Step 600 , forming a patterned first transparent conductive layer on the protection layer, and forming a patterned second metal layer on the first transparent conductive layer.

Wherein, the first transparent conductive layer constitutes a pixel electrode of the array substrate, and the second metal layer constitutes a drain and a source of a thin film transistor and a data line of the array substrate.

The source of the TFT is electrically connected to the active layer of the source region through the first via hole, and the drain of the TFT is electrically connected to the active layer of the drain region through the second via hole. The storage capacitor region of the active layer is electrically connected to the drain of the second metal layer through a third via hole.

The above is only one of the embodiments, and the storage capacitor region of the active layer and the drain region of the active region can also be directly electrically connected as a whole without connecting the two through a third via hole. electrically connected together.

Specifically, step 600 may include the following steps:

Step 610, forming a first transparent conductive layer. The first transparent conductive layer is preferably formed by using indium tin oxide (ITO), indium zinc oxide (IZO) or a combination thereof, or other transparent conductive materials through a deposition process.

Step 620, forming a second metal layer on the first transparent conductive layer. The second metal layer is preferably formed by using molybdenum (Mo) or titanium-aluminum-titanium alloy (Ti-Al-Ti) or a combination thereof through a metal sputtering process.

Preferably, the above-mentioned first transparent conductive layer and the second metal layer are continuously formed into films.

Step 630 , coating photoresist on the second metal layer.

Step 640, exposing the photoresist with a gray-tone mask or a semi-transparent mask, and forming a photoresist completely reserved area, a photoresist semi-retained area, and a photoresist completely removed area after development, wherein , the photoresist completely reserved region corresponds to the source electrode, the drain electrode and the data line region; the photoresist half reserved region corresponds to the pixel electrode region.

Step 650 , obtaining the patterned first transparent conductive layer and the second metal layer by etching.

Thus, a pixel electrode, a drain electrode, a source electrode and a data line can be obtained through one patterning process. Compared with the existing process, one mask exposure process is reduced, and the cost is saved accordingly.

FIG. 9 is a flowchart of a manufacturing method of a thin film transistor array substrate according to a sixth embodiment of the present invention. The manufacturing method is used for manufacturing a thin film transistor array substrate of an IPS mode liquid crystal display device. In this preferred embodiment, the manufacturing method further includes, after the second metal layer is formed, forming a passivation layer and a second transparent conductive layer for forming a common electrode. As shown in Figure 8, the method includes:

Step 100', forming a patterned active layer on the substrate.

Step 200', forming a gate insulating layer on the active layer.

Step 300', forming a patterned first metal layer on the gate insulating layer, the first metal layer constitutes the gate of the thin film transistor and the gate line of the array substrate.

Step 400', forming a protection layer on the first metal layer.

Step 500', patterning the protective layer and the gate insulating layer to form via holes exposing part of the active layer.

Step 600', forming a patterned first transparent conductive layer on the protection layer, and forming a patterned second metal layer on the first transparent conductive layer.

Wherein, the first transparent conductive layer constitutes a pixel electrode of the array substrate, and the second metal layer constitutes a drain and a source of a thin film transistor and a data line of the array substrate.

Step 700', forming a passivation layer on the second metal layer and the first transparent conductive layer;

Step 800', forming a second transparent conductive layer on the passivation layer, the second transparent conductive layer constitutes a common electrode of the array substrate. The second transparent conductive layer is preferably formed by a deposition process using indium tin oxide (ITO), indium zinc oxide (IZO) or a combination thereof, or other transparent conductive materials.

Specifically, step 800' may include the following steps:

Patterning the second transparent conductive layer to form a redundant common electrode pattern extending along the direction of the data line and at least partially overlapping the data line, the dummy redundant common electrode and the second transparent conductive layer Electrically isolated.

In this embodiment, the optimized structure of the thin film transistor array substrate is applied to the array substrate of the IPS liquid crystal display device, and the isolation layer and the second transparent conductive layer as the common electrode are covered on the first transparent conductive layer forming the pixel electrode pattern. The structure places the common electrode above the pixel electrode, so that it is not necessary to pattern the isolation layer on the common electrode in order to form the connection via hole between the pixel electrode and the drain as in the prior art solution, further reducing the IPS liquid crystal The mask process times of the array substrate of the display device reduces process difficulty and manufacturing cost.

In a preferred implementation of this embodiment, after forming the second transparent conductive layer, the manufacturing method further includes patterning the second transparent conductive layer to form a common electrode pattern and a portion opposite to the data line The dummy common electrode pattern is not connected to the common electrode pattern, and there is no electrical connection between the two. Preferably, a non-connected patterned second transparent conductive layer is formed by etching the transparent electrode layer around the dummy common electrode pattern.

This implementation mode can suppress the signal on the data line from forming an electric field with the common electrode, and reduce or eliminate the influence on the electric field between the pixel electrode and the common electrode.

In the present invention, by changing the structure of the thin film transistor array substrate, the second metal layer for forming the source electrode, the drain electrode and the data line is formed on the first transparent conductive layer of the pixel electrode, so that only one time is required in the manufacturing process. The patterning process of via holes, and at the same time, since the second metal layer and the transparent conductive layer are stacked together, the semi-transparent mask process can be used to etch to realize the patterning of two layers, thereby reducing the mask exposure process The number of times reduces the difficulty and cost of the process. At the same time, since the drain electrode is directly stacked and connected to the pixel electrode, compared with the via hole connection, the connection electrical characteristics are improved, and the display performance of the array substrate is improved.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (18)

1. A low temperature polysilicon thin film transistor array substrate, comprising: Substrate; an active layer formed on the substrate; a gate insulating layer covering the active layer; a patterned first metal layer disposed on the gate insulating layer, the first metal layer constitutes the gate of the thin film transistor and the gate line of the array substrate; a protective layer covering the grid and gate lines; a patterned first transparent conductive layer disposed on the protective layer, the first transparent conductive layer constitutes a pixel electrode of the array substrate; A patterned second metal layer disposed on the first transparent conductive layer and electrically connected to the active layer through a via hole, the second metal layer constitutes the drain and source of the thin film transistor and the array substrate data line. 2. The low-temperature polysilicon thin film transistor array substrate according to claim 1, wherein the patterned active layer comprises an active region and a storage capacitor region; The active region of the active layer is located below the gate and includes a source region, a drain region and a channel region, and the source of the thin film transistor is connected to the source region of the active layer through a first via hole. Electrically connected, the drain of the thin film transistor is electrically connected to the drain region of the active layer through a second via hole; The storage capacitor region is located under the gate line. 3 . The low temperature polysilicon thin film transistor array substrate according to claim 2 , wherein the storage capacitor region of the active layer is electrically connected to the drain through a third via hole. 4 . 4 . The low temperature polysilicon thin film transistor array substrate according to claim 2 , wherein the storage capacitor region of the active layer is directly electrically connected to the drain region of the active region as a whole. 5. The low-temperature polysilicon thin film transistor array substrate according to claim 1, wherein the array substrate further comprises a passivation layer covering the second metal layer and the first transparent conductive layer, and a passivation layer disposed on the passivation layer. layer on the second transparent conductive layer, the second transparent conductive layer constitutes the common electrode. 6. The low temperature polysilicon thin film transistor array substrate according to claim 5, wherein the second transparent conductive layer further comprises a redundant common electrode extending along the direction of the data line and at least partially overlapping with the data line, The redundant common electrode is electrically isolated from the common electrode. 7. The low-temperature polysilicon thin film transistor array substrate according to claim 1, wherein the protective layer comprises an interlayer dielectric insulating layer covering the first metal layer and a planarization layer formed on the interlayer dielectric insulating layer. layer. 8 . The low temperature polysilicon thin film transistor array substrate according to claim 1 , further comprising a buffer layer between the substrate and the active layer. 9. A low temperature polysilicon liquid crystal display device, characterized in that it comprises the thin film transistor array substrate according to any one of claims 1-8. 10. A method for manufacturing a low-temperature polysilicon thin film transistor array substrate, comprising: forming a patterned active layer on the substrate; forming a gate insulating layer on the active layer; forming a patterned first metal layer on the gate insulating layer, the first metal layer constitutes the gate of the thin film transistor and the gate line of the array substrate; forming a protection layer on the gate and gate lines; patterning the passivation layer and the gate insulating layer to form via holes exposing part of the active layer; forming a patterned first transparent conductive layer on the protective layer, and forming a patterned second metal layer on the first transparent conductive layer; Wherein, the first transparent conductive layer constitutes a pixel electrode of the array substrate, and the second metal layer constitutes a drain and a source of a thin film transistor and a data line of the array substrate. 11. The method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to claim 10, wherein forming a patterned active layer on the substrate comprises: Depositing an amorphous silicon layer on the substrate; The amorphous silicon layer forms an active layer through a laser thermal annealing process, a masking process and a doping process; patterning the active layer to form the active region of the thin film transistor and the storage capacitor region located below the gate line; Channel doping is performed on the active region of the active layer to form a source region, a drain region and a channel region, and the source of the film transistor is connected to the source of the active layer through the first via hole. The electrode region is electrically connected, and the drain of the film transistor is electrically connected to the drain region of the active layer through the second via hole. 12 . The low temperature polysilicon thin film transistor array substrate according to claim 11 , wherein the storage capacitor region of the active layer is electrically connected to the drain through a third via hole. 13 . 13 . The low temperature polysilicon thin film transistor array substrate according to claim 11 , wherein the storage capacitor region of the active layer is directly electrically connected to the drain region of the active region as a whole. 14. The method for manufacturing a low temperature polysilicon thin film transistor array substrate according to claim 10, further comprising: forming a passivation layer on the second metal layer and the first transparent conductive layer; A second transparent conductive layer is formed on the passivation layer, and the second transparent conductive layer constitutes a common electrode of the array substrate. 15. The method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to claim 14, wherein forming a second transparent conductive layer on the passivation layer further comprises: The second transparent conductive layer is patterned to form a redundant common electrode extending along the direction of the data line and at least partially overlapping the data line, the redundant common electrode is electrically isolated from the common electrode. 16. The method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to claim 10, wherein forming a protective layer on the gate and gate lines comprises: forming an interlayer dielectric insulating layer covering the first metal layer; A planarization layer is formed on the interlayer dielectric insulating layer. 17. The method for manufacturing a low-temperature polysilicon thin film transistor array substrate according to claim 10, wherein a patterned first transparent conductive layer is formed on the protective layer and a pattern is formed on the first transparent conductive layer. The second metallization layer consists of: forming a first transparent conductive layer; forming a second metal layer on the first transparent conductive layer; coating photoresist on the second metal layer; The photoresist is exposed using a gray-tone mask or a semi-transparent mask, and after development, a photoresist is completely retained, a photoresist is semi-retained and a photoresist is completely removed, wherein the photoresist The glue fully reserved area corresponds to the source electrode, the drain electrode and the data line area; the photoresist half reserved area corresponds to the pixel electrode area; The patterned first transparent conductive layer and the second metal layer are obtained by etching. 18. The method for manufacturing a low temperature polysilicon thin film transistor array substrate according to claim 10, further comprising: forming a buffer layer between the substrate and the active layer.

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