CN103854978A - Semiconductor device manufacturing method - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor device, comprising: forming a dummy gate insulating layer and a dummy gate layer on a substrate; photoetching/etching the dummy gate insulating layer and the dummy gate layer to form a dummy gate stack; removing the dummy gate layer to form a gate trench; forming an inner wall in the gate trench. According to the semiconductor device manufacturing method of the present invention, the inner wall is formed in the gate trench formed by removing the dummy gate, which reduces the gate line width, improves the filling rate of the high-k metal gate, and improves the performance and reliability of the device. sex.

Description

Semiconductor device manufacturing method

technical field

The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a semiconductor device that can effectively control the fineness of grid lines in a gate-last process.

Background technique

After MOSFET devices are scaled down to 45nm, the device requires a stack structure of high dielectric constant (high k) as the gate insulating layer and metal as the gate conductive layer to suppress high gate leakage due to polysilicon gate depletion issues and the gate capacitance is reduced. In order to control the profile of the gate stack more effectively, the gate-last process is widely used in the industry, that is, the dummy gates made of polysilicon and other materials are usually deposited on the substrate first, and the dummy gates are removed after depositing the interlayer dielectric layer (ILD). gate, followed by filling the remaining gate trenches with a stack of high-k/metal gate (HK/MG) film layers.

It is worth noting that in the existing gate-last process, the formation of the lightly doped source and drain regions in the substrate (the source and drain extension regions of the LDD structure or the halo-like halo structure) often needs to be used after the formation of the dummy gate stack. This makes the length of the channel region under the control of the gate of the final device equal to the sum of the width of the dummy gate and twice the thickness of the offset sidewall, which cannot effectively realize fine and small-sized devices, and the degree of performance improvement is limited .

In addition, limited by the photolithography/etching process of the dummy gate lines, the upper and lower widths of the lines are often different, and usually the lower width is greater than the upper width, thus forming a positive trapezoidal profile. This trapezoidal cross-section will affect the filling of the gate metal when the dummy gate is subsequently removed to form a gate trench and the gate trench is filled to form a gate stack, so that there are holes or even breakpoints in the gate, which affects the device performance, reducing reliability.

However, in the prior art, in order to improve the collimation of (false) gate lines, it is necessary to adopt a relatively complex and expensive advanced photolithography/etching process, which increases the manufacturing cost and increases the time consumption.

Contents of the invention

From the above, the purpose of the present invention is to overcome the above-mentioned technical difficulties, and propose a new semiconductor device manufacturing method, which can effectively control the fineness of the gate line, and at the same time, due to the characteristics of the side wall shape, it is formed by this method. The device is more conducive to the filling of high-K metal gate.

For this reason, the present invention provides a kind of semiconductor device manufacturing method, comprising: forming dummy gate insulating layer and dummy gate layer on substrate; Photoetching/etching dummy gate insulating layer and dummy gate layer form dummy gate electrode stacking; removing the dummy gate layer to form a gate trench; forming an inner wall in the gate trench.

Wherein, after the dummy gate stack is formed, the dummy gate stack is directly used as a mask to lightly dope the source and drain to form a source-drain extension region and/or a halo-shaped source-drain doped region.

Wherein, after forming the dummy gate stack, it also includes forming gate spacers on the substrates on both sides of the dummy gate stack.

Wherein, the gate sidewall is a multi-layer structure.

Wherein, after forming the gate spacer, it also includes using the gate spacer as a mask to perform heavy doping of the source and drain to form the source and drain regions.

Wherein, after forming the dummy gate stack, it also includes forming an interlayer dielectric layer on the substrate.

Wherein, the dummy gate layer is removed by wet etching and/or dry etching, and stays on the dummy gate insulating layer.

Wherein, the wet etching adopts TMAH etching solution, and the dry etching includes oxygen plasma etching, fluorine-based or chlorine-based plasma etching, and reactive ion etching.

Wherein, the inner wall includes silicon oxide, silicon nitride, DLC and combinations thereof.

Wherein, the dummy gate insulating layer includes silicon oxide, high-k materials and combinations thereof, and the dummy gate layer includes polysilicon, amorphous silicon, SiGe, Si:C, amorphous germanium, amorphous carbon and combinations thereof.

Wherein, after removing the dummy gate layer, further includes removing the dummy gate insulating layer.

According to the semiconductor device manufacturing method of the present invention, the inner wall is formed in the gate trench formed by removing the dummy gate, which reduces the gate line width, improves the filling rate of the high-k metal gate, and improves the performance and reliability of the device. sex.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 to 4 are schematic diagrams of various steps of a semiconductor device manufacturing method according to the present invention.

Detailed ways

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a semiconductor device manufacturing method capable of effectively controlling the fineness of gate lines is disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

The technical solution of the present invention will be described in detail below with reference to the schematic diagrams of each step in FIGS. 1 to 4 .

Referring to the cross-sectional view of FIG. 1 , a dummy gate insulating layer and a dummy gate layer are formed on a substrate, and a dummy gate stack is formed by photolithography/etching.

A substrate 1 is provided, and the substrate 1 is reasonably selected according to the application requirements of the device, and may include single crystal silicon (Si), single crystal germanium (Ge), strained silicon (Strained Si), silicon germanium (SiGe), or a compound semiconductor material, such as Gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, etc. In consideration of compatibility with CMOS technology, the substrate 1 is preferably bulk Si. Before forming the dummy gate insulating layer, it is preferable to use a fluorine-based solution such as dilute HF (dHF) solution or dilute slow-release etchant (dBOE) for short-term surface cleaning to remove the dummy gate insulating layer and the substrate. There may be oxides, such as thin layers of silicon oxide, in between.

Subsequently, a CVD process, such as LPCVD, PECVD, HDPCVD, etc., is used to deposit a dummy gate insulating layer 2 on the substrate 1, and its material may be silicon oxide, a high-k material or a combination thereof. High-k materials include, but are not limited to, nitrides (e.g., SiN, AlN, TiN), metal oxides (mainly oxides of subgroup and lanthanide metal elements, such as MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), perovskite phase oxides (such as PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)). The thickness of the dummy gate insulating layer 2 should not be too thick to avoid affecting the gate morphology, preferably 1-5 nm.

Afterwards, common processes such as CVD and PVD, such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputtering and other processes, are used to form the dummy gate layer 3, and its material can be polysilicon, amorphous silicon, SiGe, Si:C , amorphous germanium, amorphous carbon, etc. and combinations thereof, preferably polysilicon, amorphous silicon.

The dummy gate layer 3 and the dummy gate insulating layer 2 are patterned by a common photolithography/etching process to form a dummy gate stack structure 3/2. Directly use the dummy gate stack structure 3/2 as a mask to perform the first low-dose, low-energy source-drain doping ion implantation to form lightly doped source-drain in the substrate 1 on both sides of the dummy gate stack Extensions 1SL and 1DL. In addition, oblique ion implantation can also be performed to form a halo-shaped source-drain doped region (HaIo region, not shown). Since the formation step of the offset side wall is removed, the length of the channel region under gate control is shortened, which is beneficial to the manufacture of fine and small-scale devices.

Referring to FIG. 2 , gate spacers are formed on both sides of the dummy gate stack structure, and heavily doped source and drain regions are formed in the substrate on both sides of the gate spacer. Using LPCVD, PECVD, HDPCVD and other processes, insulating materials such as silicon nitride, silicon oxynitride, and diamond-like amorphous carbon (DLC) are deposited on the entire device and etched to form gate spacers 4 . Using the gate spacer 4 as a mask, a second high-dose, high-energy source-drain doping ion implantation is performed to form heavily doped source-drain regions 1SH and 1SH on the substrate 1 on both sides of the gate spacer 4 1DH. Preferably, the gate spacer 4 may be a multi-layer structure (not shown in the figure), for example, including at least a three-layer stack structure, which are respectively the first gate spacer on the inner side and the first gate spacer in contact with the dummy gate stack. L-shaped gate spacer spacer (with a longitudinal first part and a lateral second part) outside the pole spacer, and a second gate spacer outside and above the gate spacer spacer (which is located at the gate outside of the first longitudinal portion of the pole spacer spacer and on the second lateral portion of the gate spacer spacer). The material of the first gate spacer is, for example, amorphous carbon or silicon nitride, which can be formed by LPCVD, PECVD, or HDPCVD, and silicon nitride produced by LPCVD is preferred. The gate spacer spacer layer is, for example, silicon oxide prepared by CVD, so as to provide a high etching selectivity with other adjacent layers, thereby controlling the morphology of the gate/spacer. The second gate spacer can be silicon nitride prepared by CVD, diamond-like amorphous carbon (DLC), silicon oxynitride and the like.

Referring to FIG. 3 , the dummy gate layer is removed to form gate trenches. The interlayer dielectric layer 5 is formed on the entire device by processes such as spin coating, spray coating, screen printing, and CVD deposition. organic polymers), inorganic low-k materials (such as amorphous carbon-nitrogen films, polycrystalline boron-nitride films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (such as Porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). Subsequently, the dummy gate layer 3 is removed by etching, leaving a gate trench in the ILD5. For the dummy gate layer 3 made of silicon, it can be removed by TMAH wet etching; for the amorphous carbon material, oxygen plasma etching can be used, which can effectively avoid the erosion of adjacent materials and help improve the fineness of lines. For other materials, plasma dry etching or reactive ion etching (RIE) with fluorine-based or chlorine-based etching gases can be used. Preferably, the etching stops on the upper layer 2 of the dummy gate insulating layer 2 to protect the surface of the channel region of the substrate from erosion during the etching process, which is beneficial to reduce channel surface defects and improve device reliability. In addition, it is also possible to further remove the dummy gate insulating layer 2 after removing the dummy gate layer 3 (the step of removing layer 2 is not shown in the figure), until the substrate 1 is exposed, and then use chemical oxidation (such as immersion in 10ppm ozone 20s in deionized water) method to form an ultra-thin (for example, less than or equal to 1 nm thickness) silicon oxide interface layer, which is used to reduce interface defects between the high-k gate dielectric and the substrate.

Referring to FIG. 4 , inner sidewalls are formed in the gate trenches. Through LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD and other processes, an insulating material is deposited in the gate trench, and the inner wall 6 is formed by etching. The inner wall 6 is in contact with the gate spacer 4 and is located inside the gate spacer 4 . The material of the inner wall 6 can be commonly used silicon oxide, silicon nitride and combinations thereof, and can also be diamond-like amorphous carbon (DLC) to apply stress to the channel region to increase carrier mobility. Since the inner wall 6 is usually formed to be narrow at the top and wide at the bottom, the remaining space in the gate trench becomes an inverted trapezoid with a wide top and a narrow bottom. Holes are formed, improving device reliability. In addition, the width of the finally formed gate line is the width of the dummy gate 3 minus the thickness of the two inner wall 6 , which is beneficial to control the line fineness of small-sized devices.

Thereafter, the conventional gate-last process can be further adopted to complete the fabrication of the device. For example, it may include: depositing a gate insulating layer of high-k material in the gate trench, depositing a metal/metal nitride gate conductive layer (including work function adjustment layer and resistance adjustment layer) on the gate insulation layer, CMP Planarize each layer until the ILD5 is exposed, etch the ILD5 to form a contact hole, and form a metal silicide in the contact hole to reduce the contact resistance (the metal silicide can also be formed on the source and drain regions before forming the ILD5), in the contact hole The filling metal forms contact plugs.

According to the semiconductor device manufacturing method of the present invention, the inner wall is formed in the gate trench formed by removing the dummy gate, which reduces the gate line width, improves the filling rate of the high-k metal gate, and improves the performance and reliability of the device. sex.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (11)

1. A method of manufacturing a semiconductor device, comprising: forming a dummy gate insulating layer and a dummy gate layer on the substrate; Photolithography/etching dummy gate insulating layer and dummy gate layer to form a dummy gate stack; removing the dummy gate layer to form a gate trench; An inner wall is formed in the gate trench. 2. The semiconductor device manufacturing method according to claim 1, wherein, after forming the dummy gate stack, the source and drain are lightly doped directly using the dummy gate stack as a mask to form source and drain extension regions and/or halo source and drain doped area. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising forming gate spacers on the substrates on both sides of the dummy gate stack after forming the dummy gate stack. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the gate spacer is a multi-layer structure. 5 . The method for manufacturing a semiconductor device according to claim 3 , further comprising, after forming the gate spacer, heavily doping the source and drain using the gate spacer as a mask to form the source and drain regions. 6. The method for manufacturing a semiconductor device according to claim 1, further comprising forming an interlayer dielectric layer on the substrate after forming the dummy gate stack. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the dummy gate layer is removed by wet etching and/or dry etching, and stays on the dummy gate insulating layer. 8. The semiconductor device manufacturing method according to claim 7, wherein the wet etching uses TMAH etchant, and the dry etching includes oxygen plasma etching, fluorine-based or chlorine-based plasma etching, and reactive ion etching. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the inner wall comprises silicon oxide, silicon nitride, DLC, and combinations thereof. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the dummy gate insulating layer comprises silicon oxide, high-k materials and combinations thereof, and the dummy gate layer comprises polysilicon, amorphous silicon, SiGe, Si:C, amorphous germanium , amorphous carbon and combinations thereof. 11. The method for manufacturing a semiconductor device according to claim 1, further comprising removing the dummy gate insulating layer after removing the dummy gate layer.

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