CN105632921B - Self-aligned contact fabrication method - Google Patents

Abstract

A method for manufacturing a self-aligned contact, comprising: forming a gate opening in a first interlayer dielectric layer on a substrate; forming a metal gate in the gate opening; on the metal gate and the first interlayer dielectric layer forming a second interlayer dielectric layer; forming a mask pattern above the metal gate on the second interlayer dielectric layer; using the mask pattern as a mask, sequentially etching the second interlayer dielectric layer and the first interlayer dielectric layer until the substrate is exposed, forming self-aligned source-drain contact holes. According to the self-aligned contact manufacturing method of the present invention, a protective layer is directly formed on the top of the metal gate instead of a recess, which can effectively and properly relax the restrictions on the critical dimension and the overlap size, and improve the stability against process fluctuations and device reliability. , reducing the manufacturing cost and process difficulty.

Description

Self-aligned contact fabrication method

technical field

The present invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a self-aligned contact.

Background technique

After scaling down to 45nm for MOSFET devices, the device requires a stack of high dielectric constant (high-k) as gate insulating layer and metal as gate conductive layer to suppress high gate leakage due to polysilicon gate depletion issues and reduced gate capacitance. In order to control the profile of the gate stack more effectively, the gate-last process is generally adopted in the industry, that is, a dummy gate made of materials such as polysilicon is usually deposited on the substrate first, and then the interlayer dielectric (ILD) is deposited to remove the dummy gate. The gate is then filled with a stack of high-k/metal gate (HK/MG) films in the remaining gate trenches. After that, the ILD is etched to form a contact hole exposing the source and drain regions, and a metal material is deposited in the contact hole to form a contact plug (plug) to complete the source-drain interconnection.

However, with the improvement of device integration, the feature size of the device continues to shrink, and the gate length and the size of the source and drain regions are reduced in equal proportions. When the size of the source and drain regions is small, eg, sub-20 nm, it will bring great challenges to the contact process. This is mainly reflected in the higher requirements on the critical dimension (CD) and overlap of photolithography. For example, in order to reduce the series resistance of the contact itself, the size of the contact hole is required to be substantially close to the size of the source and drain regions. If the size of the contact hole is significantly smaller than the size of the source and drain regions (especially the heavily doped source and drain regions SD), this requires higher critical dimensions for photolithography, and the smaller size of the contact hole itself will have a larger series resistance. In addition, since the distance between the contact hole and the gate is reduced, the overlap of the contact hole lithography is required to be high. If the overlap is large, it will cause a short circuit between the contact and the gate.

To solve this problem, a process with relatively low requirements for lithographic CD and overlay is required. At present, the industry has proposed a self-aligned contact (SAC) process and other similar SAC processes to solve the above problems.

Typically, the SAC process includes dummy gate stack patterning in a gate-last process, forming source and drain regions, depositing ILD and removing the dummy gate stack to form gate openings, depositing gate dielectric layers and double metal layers in the gate openings gate conductive layer. Subsequently, in order to enable the formation of self-aligned source-drain contacts, the top of the metal gate is recessed by an etch-back or CMP process, because the two sides of the metal gate are gate spacers (usually nitrided Silicon material) and ILD, so it is possible to control the etching process parameters or the composition of the CMP abrasive so that the metal etching and polishing rates are high, and the self-aligned formation of depressions. The formed recesses are filled with a hard material such as silicon nitride as a top insulating layer and an etch stop layer, and then CMP is performed until the ILD is exposed. Then, the process parameters are adjusted for etching. Since the top of the metal gate is covered by a hard silicon nitride material, the vertical etching is only for soft materials such as low-k materials and silicon oxide, and the metal gate and both sides of the sidewall are removed. until the source and drain regions are exposed, self-aligned contact holes with approximately the same size as the source and drain regions on both sides of the gate are formed. This process requires less CD error control and overlay size for photolithography than conventional processes.

However, as mentioned above, in order to avoid a short circuit between the contact and the gate when the lithography offset is large, the metal inside the gate needs to be self-aligned and etched, and then the etched cavity is filled with SiN as an insulating material and CMP is performed. This requires the gate to be high enough, otherwise recessing processes such as etchback and CMP will remove most of the metal gate, resulting in device failure. The increase in the height of the gate is not conducive to the miniaturization of the multi-layer interconnection above it, and increases the difficulty of depositing a filling metal layer in the gate opening in the ILD, which is easy to form defects such as bubbles and holes. At the same time, one step of CMP is added, which will increase the difficulty and cost of the process.

SUMMARY OF THE INVENTION

From the above, the purpose of the present invention is to overcome the above-mentioned technical difficulties, and propose a new method for manufacturing self-aligned contact holes, which can effectively and properly relax the restrictions on critical dimensions and overlapping sizes, and improve the stability of process fluctuations and the reliability of devices. , reducing the manufacturing cost and process difficulty.

To this end, the present invention provides a method for manufacturing a self-aligned contact, comprising: forming a gate opening in a first interlayer dielectric layer on a substrate; forming a metal gate in the gate opening; forming a metal gate and A second interlayer dielectric layer is formed on the first interlayer dielectric layer; a mask pattern located above the metal gate is formed on the second interlayer dielectric layer; and the second interlayer dielectric is sequentially etched using the mask pattern as a mask layer and the first interlayer dielectric layer until the source and drain regions of the device are exposed to form self-aligned source and drain contact holes.

Wherein, the step of forming the gate opening further includes: forming a dummy gate stack on the substrate; forming source and drain regions in the substrate on both sides of the dummy gate stack; forming a dummy gate stack on the substrate a first interlayer dielectric layer; planarizing the interlayer dielectric layer until the dummy gate stack is exposed; selective etching to remove the dummy gate stack, leaving a gate opening in the first interlayer dielectric layer.

The sidewalls of the gate opening have gate spacers.

The material of the second interlayer dielectric layer is different from that of the first interlayer dielectric layer.

Wherein, the density of the second interlayer dielectric layer and/or the gate spacer is greater than that of the first interlayer dielectric layer.

Wherein, the thickness of the second interlayer dielectric layer is smaller than the height of the metal gate.

The width of the mask pattern is equal to or close to the sum of twice the width of the gate spacer and the width of the metal gate.

The source-drain contact holes expose the gate spacers.

Wherein, the etching is one-step etching or two-step etching; or the etching is dry etching, wet etching and combinations thereof.

Wherein, the mask pattern is a photoresist, silicon oxide, or ONO structure.

According to the self-aligned contact manufacturing method of the present invention, a protective layer is directly formed on the top of the metal gate instead of a recess, which can effectively and properly relax the restrictions on the critical dimension and the overlap size, and improve the stability against process fluctuations and device reliability. , reducing the manufacturing cost and process difficulty.

Description of drawings

The technical solutions of the present invention are described in detail below with reference to the accompanying drawings, wherein:

1 to 4 are cross-sectional views of steps of a method for fabricating a self-aligned contact according to the present invention.

Detailed ways

The features and technical effects of the technical solutions of the present invention are described in detail below with reference to the accompanying drawings and schematic embodiments, and a method for manufacturing a semiconductor device capable of effectively controlling the fineness of gate lines is disclosed. It should be noted that similar reference numerals denote similar structures, and the terms "first", "second", "upper", "lower", etc. used in this application may be used to modify various device structures or fabrication processes . These modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures or fabrication processes unless otherwise specified.

The technical solution of the present invention will be described in detail below with reference to the schematic diagrams of each step in FIGS. 1 to 4 .

As shown in FIG. 1 , a metal gate conductive layer is deposited in the gate opening in the first interlayer dielectric layer and planarized until the first interlayer dielectric layer is exposed.

Specifically, a substrate 1 is provided first. The substrate 1 is reasonably selected according to the needs of the device, and may include single crystal silicon (Si), single crystal germanium (Ge), strained silicon (Strained Si), silicon germanium (SiGe), or a compound Semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes, and the like. For compatibility with the CMOS process, the substrate 1 is preferably bulk Si. Before forming the dummy gate insulating layer, preferably, a fluorine-based solution, such as a diluted HF (dHF) solution or a diluted slow release etchant (dBOE), is used for short-term surface cleaning to remove the dummy gate insulating layer and the liner. A thin layer of oxide, such as silicon oxide, that may exist between the substrates.

Subsequently, a CVD process, such as LPCVD, PECVD, HDPCVD, etc., is used to deposit a dummy gate insulating layer (not shown) on the substrate 1, and its material may be silicon oxide, high-k material and combinations thereof. High-k materials include, but are not limited to, nitrides (eg, SiN, AlN, TiN), metal oxides (mainly subgroup and lanthanide metal oxides, such as MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), perovskite phase oxides (eg PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _{1- x} TiO _{3 )} (BST)). The thickness of the dummy gate insulating layer cannot be too thick to avoid affecting the gate shape, and is preferably 1-5 nm.

After that, common processes such as CVD and PVD are used, such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputtering and other processes to form a dummy gate layer (not shown), and its material can be polysilicon, amorphous silicon, SiGe , Si:C, amorphous germanium, amorphous carbon, etc. and combinations thereof, preferably polycrystalline silicon, amorphous silicon.

A common photolithography/etching process is used to pattern the dummy gate layer and the dummy gate insulating layer to form a dummy gate stack structure. Directly using the dummy gate stack structure as a mask, the first source-drain doping ion implantation with low dose and low energy is performed, and lightly doped source-drain extension regions 1L are formed in the substrate 1 on both sides of the dummy gate stack. . In addition, oblique ion implantation can also be performed to form halo-shaped source-drain doped regions (Halo regions, not shown). In another embodiment of the present invention, the extended source and drain regions may be formed by epitaxial growth alone, or a combination of epitaxial growth and ion doping. In addition, gate spacers can be formed to control the distance between the LDD structure and the channel region before the source and drain extension regions are implanted with doping, but the gate spacers can also be directly used as masks without forming gate spacers. However, if an LDD structure is formed on both sides of the gate spacer on the surface of the substrate by epitaxial growth, the spacer must be formed on both sides of the gate first to avoid the LDD structure and the polysilicon, amorphous silicon, And materials with similar lattice constants such as SiGe grow together to destroy the device structure.

Gate spacers 2 are formed on both sides of the dummy gate stack structure, and heavily doped source and drain regions are formed in the substrate on both sides of the gate spacer 2 . Using LPCVD, PECVD, HDPCVD and other processes, deposit denser and harder insulating materials such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC) on the entire device, and etch to form gate spacers 2. Using the gate spacer 2 as a mask, a second source-drain doping ion implantation with high dose and high energy is performed, and heavily doped source and drain regions 1H are formed on the substrate 1 on both sides of the gate spacer 2 . In another embodiment of the present invention, the heavily doped source and drain regions are formed by epitaxy and in-situ doping simultaneously, or the source and drain regions are epitaxially grown and then heavily doped ion implantation is performed to form the source and drain regions 1H. Preferably, the gate spacer 2 may be a multi-layer structure (not shown in the figure), for example, it includes at least a three-layer stack structure, which are the inner first gate spacer and the first gate that are in contact with the dummy gate stack, respectively. L-shaped (having a longitudinal first portion and a lateral second portion) gate spacer spacer outside the pole spacer, and a second gate spacer outside and above the gate spacer spacer (which is located in the gate spacer) the outer side of the longitudinal first portion of the pole spacer spacer and on the lateral second portion of the gate spacer spacer). The material of the first gate spacer is, for example, amorphous carbon or silicon nitride, which can be formed by LPCVD, PECVD, and HDPCVD processes, and preferably silicon nitride made by LPCVD. The gate spacer spacer is, for example, silicon oxide prepared by CVD, so as to provide a high etching selectivity ratio with other adjacent layers, thereby controlling the topography of the gate/spacer. The second gate spacers may be silicon nitride, diamond-like amorphous carbon (DLC), silicon oxynitride, etc. prepared by CVD. In a preferred embodiment of the present invention, the width of the sidewall spacers 2 is preferably greater than half of the difference between the gate width and the source/drain region width, for example, 15 nm, which corresponds to the overlay in the subsequent self-aligned contact formation process (ie The maximum size of the lateral deviation of the contact hole) is less than 15 nm, that is, the contact hole offset distance is less than the width of the gate spacer 2 to avoid short circuit with the metal gate. In contrast, in the conventional process, since the sum of the width of the gate opening and the sidewall spacer is similar to the width of the source and drain regions, a higher overlay limit, such as less than 5 nm, is required in the process of accurately forming the contact hole.

The first interlayer dielectric layer 3 is formed on the entire device by processes such as spin coating, spray coating, screen printing, CVD (eg LPCVD) deposition, and its material is preferably silicon oxide, silicon nitride or other low-k materials. Low-k materials include, but are not limited to, organic low-k materials (such as organic polymers containing aromatic groups or multiple rings), inorganic low-k materials (such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicate glass, BSG, PSG) , BPSG), porous low-k materials such as disiloxane (SSQ) based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). Subsequently, the dummy gate layer is etched away, leaving a gate opening in ILD 3 . For the dummy gate layer of silicon material, TMAH wet etching can be used to remove it; for amorphous carbon material, oxygen plasma etching can be used, which can effectively avoid the erosion of adjacent materials and help to improve the fineness of the lines. ; For other materials, plasma dry etching or reactive ion etching (RIE) with fluorine-based or chlorine-based etching gas can be used. Preferably, the etching stops on the dummy gate insulating layer, and the dummy gate insulating layer is used as an interface layer to protect the surface of the channel region of the substrate from erosion during the etching process, which is beneficial to reduce channel surface defects , Improve device reliability. In addition, the dummy gate insulating layer (not shown in the figure) can also be further removed after removing the dummy gate layer until the substrate 1 is exposed, and then chemical oxidation (eg, immersion in deionized water containing 10 ppm ozone for 20 s) is used. An ultra-thin (for example, a thickness of less than or equal to 1 nm) an interface layer of silicon oxide is formed to reduce interface defects between the high-k gate dielectric and the substrate.

A gate dielectric layer 4 and a metal gate conductive layer 5 are sequentially formed in the gate opening in the ILD 3 by HDPCVD, MOCVD, MBE, ALD, sputtering and other processes. The gate dielectric layer 4 is, for example, a high-k material, including but not limited to nitrides (such as SiN, AlN, TiN), metal oxides (mainly oxides of subgroup and lanthanide metal elements, such as MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), oxynitrides (eg HfSiON); perovskite phase oxides (eg PbZr _x Ti _{1 ) -x} O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)). More preferably, between the gate dielectric layer 4 and the channel region of the substrate 1, there is an ultra-thin (eg, 0..8-1..5 nm) silicon oxide interface layer (not formed by thermal oxidation and chemical oxidation). shown) to reduce the interface state density. The material of the metal gate conductive layer 5 may include metal elements such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc., Or alloys of these metals and nitrides of these metals, in addition, C, F, N, O, B, P, As and other elements can be added to adjust the work function by in-situ doping or ion implantation doping. Preferably, a nitride barrier layer (not shown) is preferably formed between the metal gate conductive layer 5 and the gate dielectric layer 4 by conventional methods such as PVD, CVD, ALD, etc., and the material of the barrier layer is M _x N _y , M _x Si _y N _z , M _{x A ly} N _z , Ma Al _x Si _y N _z , where M is Ta, Ti, Hf, Zr, Mo, W or other elements.

Preferably, the stack of layers 5, 4 is planarized using a CMP process until the first ILD 3 is exposed. It is worth noting that the embodiment shown in the drawings of the present invention is a cross-sectional view of a cell array transistor according to a memory device, so a plurality of self-aligned source-drain contact holes need to be formed between a plurality of gates, and adjacent transistors need to be formed. The source and drain regions are shared. Naturally, for devices with other structures, the thickness and spacing of the gate spacers 2 can be adjusted to obtain the required contact hole width and the source and drain regions can be separated. But preferably, for a highly integrated device with a feature size of less than 20 nm, it is preferable to widen the width of the contact hole to make it close to the width of the source and drain regions.

As shown in FIG. 2 , a second ILD 6 is formed on the metal gate conductive layer 5 . Different from the first ILD 3 of low-k material, the second ILD preferably adopts relatively dense stress-free silicon nitride or compressive stress (for example, the stress is between 600MPa and 2GPa) silicon nitride, and its formation process is such as PECVD, HDPCVD, MBE, ALD, sputtering. Preferably, the density of the second ILD 6 is greater than that of the first ILD 3 , for example, the etching rate of the second ILD 6 and/or the gate spacer 5 in the subsequent self-aligned etching of the source and drain holes is lower than that of the first ILD 3 . An etch rate of ILD 3. Preferably, the etching selection ratio between the material of the ILD 6 and the material of the ILD 3 is greater than 5:1, and preferably greater than 10:1, so as to avoid lateral erosion of the upper ILD 6 when the ILD 3 is subsequently etched, so that the gate can be improved. Extreme line accuracy to avoid grid line breakage or distortion. Preferably, the thickness of the ILD 6 is less than or equal to the height of the gate metal layer 5, for example, 65%-45% of the height of the layer 5, so as to reduce the aspect ratio of the subsequent contact hole filling and improve the metal filling rate.

As shown in FIG. 3 , a mask pattern 7 is formed on the second ILD 6 . The mask pattern 7 can be a photoresist pattern, for example, a photoresist layer is formed by spin coating, spray coating, or screen printing process, and then the photoresist mask pattern 7 is formed by exposure and development. In addition, the mask pattern 7 can also be a hard mask with a different material from the ILD 6, such as silicon oxide formed by LPCVD, PECVD, oxidation, etc., or an ONO structure (oxide-nitride-oxide stack structure), As a result, the accuracy of mask transfer can be further improved. The width of the mask pattern 7 is larger than the width of the metal gate conductive layer 5 . And specifically, for example, the width of the mask pattern 7 is equal to or close to the sum of twice the width of the gate spacer 2 and the width of the metal gate 5, that is, the width of the layer 7=the width of the layer 5+2×the width of the spacer 2. , where close means that it can be slightly larger or smaller, for example, the difference between the width of the mask pattern 7 and the sum of twice the width of the spacer 2 plus the width of the gate 5 is less than or equal to 3 nm and preferably less than or equal to 1 nm. Thus, the mask pattern 7 completely covers the top of the gate and exceeds the gate line width, so that the critical dimension of the whole process can allow proper fluctuation and proper overlay, even when the gate line deviates or the contact hole deviates, due to the ILD 6 , The insulating isolation of the gate sidewall 2, the gate 5 will not be short-circuited with the metal plug in the subsequent contact hole. Therefore, device reliability is improved, and device cost is reduced.

As shown in FIG. 4 , using the mask pattern 7 as a mask, an anisotropic etching process is used to sequentially etch the ILD 6 and ILD 3 until the source and drain regions 1L and 1H in the substrate 1 are exposed, and contact holes are formed. The etching process can be one-step etching (when ILD3 is silicon nitride with a different stress than ILD6, due to different stress and different etching rates, a relatively vertical etching sidewall can be achieved) or two-step etching (for example, when The materials of ILD6 and ILD3 are different, that is, when ILD6 is silicon nitride and ILD3 is silicon oxide or low-k material), the etching process can be dry etching (for example, adjusting the ratio of carbon-fluorine-based etching gas to obtain different etching rate) can also be wet etching (eg, hot phosphoric acid for silicon nitride, HF-based etching solution for silicon oxide). Due to the combined protection of the second ILD 6 and the gate spacer 2, the top and side walls of the metal gate 5 will not be laterally eroded during the etching of the contact hole, thereby obtaining fine and highly reliable gate lines Contact with source and drain improves device performance and reliability. It is worth noting that this source-drain contact hole directly exposes the sidewall of the gate spacer 2 , so it is called a self-aligned source-drain contact hole, which is beneficial to reduce the source-drain contact resistance. After that, metal silicide can be formed in the contact hole to reduce the contact resistance, and then an adhesion layer such as Ti, TiN, Ta, TaN and the like can be deposited and formed, and finally the contact hole is filled with metal W, Mo, etc. to form a contact plug.

According to the self-aligned contact manufacturing method of the present invention, a protective layer is directly formed on the top of the metal gate instead of a recess, which can effectively and properly relax the restrictions on the critical dimension and the overlap size, and improve the stability against process fluctuations and device reliability. , reducing the manufacturing cost and process difficulty.

Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structure without departing from the scope of the invention. In addition, many modifications, as may be adapted to a particular situation or material, may be made from the disclosed teachings without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structures and methods of making the same are to include all embodiments that fall within the scope of the present invention .

Claims (8)

1. a kind of self-aligned contacts manufacturing method, comprising:

Gate openings are formed in the first interlayer dielectric layer on substrate, the side wall of gate openings has grid curb wall；

Metal gates are formed in gate openings, are flushed with the first interlayer dielectric layer top；

The second interlayer dielectric layer is formed on metal gates and the first interlayer dielectric layer, the second interlayer dielectric layer directly contacts gold Belong to the top of grid and the first interlayer dielectric layer；

The mask graph being located above metal gates is formed on the second interlayer dielectric layer, perpendicular to mask graph on substrate direction Side wall flushed with the lateral wall of grid curb wall；

Using mask graph as mask, it is sequentially etched the second interlayer dielectric layer and the first interlayer dielectric layer, until the source of exposure device Drain region forms the self aligned source and drain contact hole of directly exposure grid curb wall side wall, mask graph, the second inter-level dielectric Layer, grid curb wall three's lateral wall flush.

2. the step of the method for claim 1, wherein forming gate openings further comprises: vacation is formed on the substrate Gate stack；It is stacked in the substrate of two sides in false grid and forms source-drain electrode；It is formed on the substrate and covers the first of false grid stacking Interlayer dielectric layer；Interlayer dielectric layer is planarized until exposure false grid stacks；Selective etch removes false grid and stacks, first Gate openings are left in interlayer dielectric layer.

3. the method for claim 1, wherein the material of the material of the second interlayer dielectric layer and the first interlayer dielectric layer is not Together.

4. the method for claim 1, wherein the compactness of the second interlayer dielectric layer and/or grid curb wall is greater than first Interlayer dielectric layer.

5. the method for claim 1, wherein the thickness of the second interlayer dielectric layer is less than the height of metal gates.

6. the method for claim 1, wherein the width of mask graph is equal or close in the two of grid curb wall width Times the sum of with the width of metal gates.

7. the method for claim 1, wherein etching is step etching or two steps etching；Or etching be dry etching, Wet etching and combinations thereof.

8. the method for claim 1, wherein mask graph is photoresist, silica or ONO structure.