CN103853666B - Memory, its storage controller and data writing method - Google Patents

Abstract

The invention provides a memory, a memory controller and a data writing method thereof; the data writing method is used for a memory comprising a buffer memory and a rewritable nonvolatile memory module. The method includes receiving a plurality of sets of data, wherein the plurality of sets of data include a first type of data and at least a second type of data, wherein a capacity of the first type of data is less than a data size threshold. The method also includes temporarily storing the plurality of sets of data in a buffer memory, and programming the first type of data and at least a portion of the second type of data temporarily stored in the buffer memory to a set of physical programming units at the same time when the plurality of sets of data are determined to meet a predetermined condition, the set of physical programming units being composed of n physical programming units, n being a positive integer. The method further includes simultaneously obtaining the writing status of the first type data and at least a portion of the second type data.

Description

Memory, its storage controller and data writing method

technical field

The present invention relates to a data writing method, and in particular to a memory for a rewritable non-volatile memory module, its storage controller and a data writing method.

Background technique

Rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size and no mechanical structure, so it is widely used in digital cameras, mobile phones and MP3 etc. Portable Electronic Devices. A solid state drive is a storage device that uses flash memory as a storage medium.

Generally speaking, the flash memory module of the flash memory is divided into multiple physical blocks, wherein the physical block is further divided into multiple physical pages, and the physical block is the erasing unit of the flash memory and the physical page is the writing unit of the flash memory. Since only one-way programming (that is, the value of the memory cell can only be programmed from 1 to 0) can be performed when programming the memory cells of the flash memory, it is impossible to program the programmed entity pages (that is, the pages with old data) ) to write directly, but this physical page must be erased before reprogramming. In particular, since the flash memory is erased in units of physical blocks, when it is desired to perform an erase operation on a physical page storing old data, the entire physical block to which the physical page belongs must be erased. Therefore, the physical blocks of the flash memory module can be divided into data areas and idle areas, wherein the physical blocks in the data area are physical blocks that have been used to store data, and the physical blocks in the spare area are unused physical blocks, wherein When the host system intends to write data to the flash memory, the control circuit of the flash memory extracts a physical block from the spare area to write data, and associates the extracted physical block as a data area. Moreover, when the physical blocks in the data area are erased, the erased physical blocks will be associated as spare areas.

Based on the above architecture, for applications that use flash memory as a storage medium and need to ensure safe data writing, when processing each write command from the host system, in order to align the written data with the physical page, it is often necessary to read from the flash memory. The old valid data is read out to fill the written data, and after the data is programmed into the flash memory, the information indicating whether the writing operation is completed or not is sent back to the host system. Furthermore, for applications that need to ensure safe writing of data, it is necessary to return information on the programming result so that the host system can grasp the status of data writing. It is not difficult to imagine that if the host system continuously issues several write commands, the above program must be executed for each write command, and since each write command consumes a considerable amount of programming time, it is difficult to write data in the data The writing speed is improved under the safe writing mechanism.

Contents of the invention

In view of this, the present invention provides a memory, its storage controller and a data writing method, which can ensure that data is safely written into the memory while increasing the writing speed.

The present invention proposes a data writing method, which is used in a memory, and the memory includes a buffer memory and a rewritable non-volatile memory module, and the rewritable non-volatile memory module has a plurality of physical erasing units, and each The physical erasing unit has multiple physical programming units. The method includes receiving multiple sets of data, wherein the multiple sets of data include a first type of data and at least one second type of data, wherein the capacity of the first type of data is less than the critical value of data volume. The method also includes temporarily storing the multiple sets of data in the buffer memory, and programming the first type of data and at least part of the second type of data temporarily stored in the buffer memory into the physical programming unit at the same time after judging that the multiple sets of data meet the predetermined conditions Group, this physical programming unit group is composed of n physical programming units, where n is a positive integer. The method also includes knowing the writing status of the first type of data and at least part of the second type of data at the same time.

In an embodiment of the present invention, when the amount of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit set, it is determined that the multiple sets of data meet the predetermined condition.

In an embodiment of the present invention, when the memory does not receive other data for more than a time threshold, it is determined that the multiple sets of data meet the predetermined condition.

In an embodiment of the present invention, each physical programming unit includes a data recording area and an available redundant area, and the first type of data and at least part of the second type of data temporarily stored in the buffer memory are programmed to the physical programming unit group at the same time The step includes writing the first type of data and at least part of the second type of data into the data recording area of n physical programming units constituting the physical programming unit group, and individually corresponding the first type of data and at least part of the second type of data The logical access address and the number of sectors are written into the available redundant area of the n physical programming units constituting the physical programming unit group.

In an embodiment of the present invention, the data writing method further includes maintaining a correspondence table to record the respective logical access addresses and The corresponding relationship between the number of sectors and the physical programming unit group, and writing the corresponding table to a specific physical erasing unit among all the physical erasing units, wherein none of the physical programming units of the specific physical erasing unit belongs to physical programming unit group.

In an embodiment of the present invention, the write statuses of the first type of data and at least part of the second type of data are collectively returned to the host system that sent multiple sets of data.

The present invention proposes a storage controller to manage rewritable non-volatile memory modules. The storage controller includes a host system interface, a memory interface, a buffer memory, and a memory management circuit. The host system interface is used to electrically connect the host system. The memory interface is used to electrically connect the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and each physical erasing unit has a plurality of physical programming units. The memory management circuit is electrically connected to the host system interface, the memory interface and the buffer memory. Wherein the memory management circuit receives multiple sets of data, the multiple sets of data include a first type of data and at least one second type of data, wherein the capacity of the first type of data is less than the critical value of data volume. The memory management circuit temporarily stores the multiple sets of data in the buffer memory, and when judging that the multiple sets of data meet the predetermined conditions, simultaneously programs the first type of data temporarily stored in the buffer memory and at least part of the second type of data into the physical programming unit group , the physical programming unit group is composed of n physical programming units, where n is a positive integer. The memory management circuit simultaneously knows the writing status of the first type of data and at least part of the second type of data.

In an embodiment of the present invention, when the amount of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit set, the memory management circuit determines that the multiple sets of data meet a predetermined condition.

In an embodiment of the present invention, when the memory management circuit does not receive other data for a time exceeding a time threshold, the memory management circuit determines that multiple sets of data meet a predetermined condition.

In an embodiment of the present invention, each physical programming unit includes a data recording area and an available redundant area, and when the memory management circuit simultaneously programs the first type of data and at least part of the second type of data into the physical programming unit group, Writing the first type of data and at least part of the second type of data into the data recording areas of the n physical programming units that make up the physical programming unit group, and individually corresponding to the logic storage of the first type of data and at least part of the second type of data The address and the number of sectors are taken and written into the available redundant area of the n physical programming units constituting the physical programming unit group.

In an embodiment of the present invention, the memory management circuit is also used to maintain a correspondence table to record the respective logical access addresses and The corresponding relationship between the number of sectors and the physical programming unit group, and write the corresponding table to a specific physical erasing unit in all physical erasing units, wherein the physical programming units of the specific physical erasing unit do not belong to physical programming unit group.

In an embodiment of the present invention, the write statuses of the first type of data and at least part of the second type of data are collectively returned to the host system that sent multiple sets of data.

The invention provides a memory, including a rewritable non-volatile memory module, a connector, and a memory controller. Wherein the rewritable non-volatile memory module includes a plurality of physical erasing units, and each physical erasing unit has a plurality of physical programming units. The connector is used to electrically connect the host system. The storage controller is electrically connected to the rewritable non-volatile memory module and the connector, and the storage controller includes a buffer memory. The storage controller receives multiple sets of data, and the multiple sets of data include a first type of data and at least one second type of data, wherein the capacity of the first type of data is less than the critical value of data volume. The storage controller temporarily stores the multiple sets of data in the buffer memory, and when judging that the multiple sets of data meet the predetermined conditions, simultaneously programs the first type of data temporarily stored in the buffer memory and at least part of the second type of data into the physical programming unit group , the physical programming unit group is composed of n physical programming units, where n is a positive integer. The storage controller simultaneously learns the writing status of the first type of data and at least part of the second type of data.

In an embodiment of the present invention, when the amount of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit set, the storage controller determines that the multiple sets of data meet the predetermined condition.

In an embodiment of the present invention, when the storage controller does not receive other data for more than a time threshold, the storage controller determines that the multiple sets of data meet the predetermined condition.

In an embodiment of the present invention, each physical programming unit includes a data recording area and an available redundant area, and when the storage controller simultaneously programs the first type of data and at least part of the second type of data into the physical programming unit group, Writing the first type of data and at least part of the second type of data into the data recording areas of the n physical programming units that make up the physical programming unit group, and individually corresponding to the logic storage of the first type of data and at least part of the second type of data The address and the number of sectors are taken and written into the available redundant area of the n physical programming units constituting the physical programming unit group.

In an embodiment of the present invention, the memory controller is also used to maintain a correspondence table to record the logical access addresses and corresponding logical access addresses and The corresponding relationship between the number of sectors and the physical programming unit group, and write the corresponding table to a specific physical erasing unit in all physical erasing units, wherein the physical programming units of the specific physical erasing unit do not belong to physical programming unit group.

In an embodiment of the present invention, the write statuses of the first type of data and at least part of the second type of data are collectively returned to the host system that sent multiple sets of data.

Based on the above, the present invention first accumulates a small amount of data to be written by multiple sets of host systems, and after the above data are successfully programmed into the rewritable non-volatile memory module, several write completion messages are simultaneously returned Respond to the host system with several write commands corresponding to the above data. Accordingly, the purpose of writing data into the memory quickly and safely is achieved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of a host system using a memory according to an embodiment of the present invention;

FIG. 1B is a schematic diagram of a computer, an input/output device and a memory according to an embodiment of the present invention;

FIG. 1C is a schematic diagram of a host system and a memory according to another embodiment of the present invention;

FIG. 2 is a schematic block diagram showing the memory shown in FIG. 1A;

FIG. 3 is a schematic block diagram of a storage controller according to an embodiment of the present invention;

4 and 5 are schematic diagrams of a management rewritable non-volatile memory module shown according to an embodiment of the present invention;

Fig. 6 is a schematic diagram of a physical unit shown according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a physical programming unit shown according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of programming data into a physical programming unit group according to an embodiment of the present invention;

Fig. 9 is a flowchart of a data writing method according to an embodiment of the present invention.

Explanation of reference signs:

1000: host system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: U disk;

1214: memory card;

1216: SSD;

1310: digital camera;

1312: SD card;

1314: MMC card;

1316: memory stick;

1318: CF card;

1320: embedded storage device;

100: memory;

102: connector;

104: storage controller;

106: a rewritable non-volatile memory module;

1041: host system interface;

1043: memory management circuit;

1045: memory interface;

1047: buffer memory;

3002: error checking and correction circuit;

3006: power management circuit;

410(0)～410(N): entity erasing unit;

502: data area;

504: idle area;

506: system area;

508: Replacement area;

610(0)～610(L): logic unit;

710(0)～710(C), 710(D)～710(E): entity unit;

_PF (0)～ _PF (127), _PF+1 (0)～ _PF+1 (127), _PF+2 (0)～ _PF+2 (127), _PF+3 (0 )～ _PF+3 (127): Entity programming unit;

FP(0), FP(1), FP(2), FP(127): entity programming unit group;

WD ₁ : first data;

WD _{2_1} , WD _{2_2} , WD _{2_3} : second data;

WD ₃ : third data;

DD ₁ , DD ₂ , DD ₃ , DD ₄ : padding data;

S910-S930: steps.

detailed description

Generally speaking, a memory (also called a storage system) includes a rewritable non-volatile memory module and a storage controller (also called a control circuit). Typically memory is used with a host system so that the host system can write data to and read data from the memory.

FIG. 1A is a schematic diagram of a host system using a memory according to an embodiment of the present invention.

The host system 1000 includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (Random Access Memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Through the operations of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 , the host system 1000 can write data into the memory 100 or read data from the memory 100 . For example, the memory 100 may be a memory card 1214, a USB disk 1212, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

In general, host system 1000 is any system that can store data. Although the host system 1000 is described as a computer system in this embodiment, in another embodiment of the present invention, the host system 1000 can also be a mobile phone, a digital camera, a camcorder, a communication device, an audio player or a video player devices and other systems. For example, when the host system is a digital camera 1310, the storage is a Secure Digital (Secure Digital, SD) card 1312, a Multimedia Card (MMC) card 1314, a memory stick (Memory Stick) 1316, a compact A flash memory (CompactFlash, CF) card 1318 or an embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (EmbeddedMMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram showing the memory shown in FIG. 1A. Referring to FIG. 2 , the memory 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

The connector 102 is electrically connected to the storage controller 104 and used for electrically connecting the host system 1000 . In this embodiment, the type of transmission interface supported by the connector 102 is a Universal Serial Bus (USB) interface. However, in other embodiments, the transmission interface type of the connector 102 may also be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) interface, a multimedia card (Multimedia Card, MMC) interface, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA ) interface, Institute of Electrical and Electronic Engineers (IEEE) 1394 interface, Peripheral Component Interconnect Express (PCI Express) interface, Secure Digital (SecureDigital, SD) interface, Memory Stick (Memory Stick , MS) interface, CompactFlash (CompactFlash, CF) interface, or any applicable interface such as Integrated Drive Electronics (Integrated Drive Electronics, IDE) interface, which is not limited here.

The storage controller 104 executes a plurality of logic gates or control instructions implemented in hardware or firmware, and writes, reads, and writes data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000. Erase etc. Wherein, the storage controller 104 is also specially used for processing the data to be written into the rewritable non-volatile memory module 106 by the host system 1000 according to the data writing method of this embodiment. The data writing method of this embodiment will be described later with the illustrations.

The rewritable non-volatile memory module 106 is electrically connected to the storage controller 104 . The rewritable nonvolatile memory module 106 is a multi-level storage unit (Multi Level Cell, MLC) NAND flash memory module, but the present invention is not limited thereto, and the rewritable nonvolatile memory module 106 can also be a single-level storage unit (Single Level Cell, SLC) NAND flash memory modules, other flash memory modules, or any memory module with the same characteristics. Further, the rewritable non-volatile memory module 106 includes a plurality of physical erasing units, and each physical erasing unit has a plurality of physical programming units. Physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. That is to say, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. The entity programming unit is the smallest unit of programming. That is, the physical programming unit is the minimum unit for writing data. In this embodiment, the physical erasing unit is a physical block, and the physical programming unit is a physical page, but the invention is not limited thereto.

FIG. 3 is a schematic block diagram of a storage controller according to an embodiment of the present invention. Referring to FIG. 3 , the storage controller 104 includes a host system interface 1041 , a memory management circuit 1043 , a memory interface 1045 , and a buffer memory 1047 .

The host system interface 1041 is electrically connected to the memory management circuit 1043 and electrically connected to the host system 1000 through the connector 102 . The host system interface 1041 is used for receiving and identifying commands and data transmitted by the host system 1000 . Accordingly, the commands and data sent by the host system 1000 are sent to the memory management circuit 1043 through the host system interface 1041 . In this embodiment, the host system interface 1041 is a USB interface corresponding to the connector 102, and in other embodiments, the host system interface 1041 can also be a SATA interface, an MMC interface, a PATA interface, an IEEE 1394 interface, a PCI Express interface, SD interface, MS interface, CF interface, IDE interface or interfaces that meet other interface standards.

The memory management circuit 1043 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 1043 has a plurality of control instructions, and when the memory 100 is powered on, the above control instructions will be executed to implement the data writing method of this embodiment.

In one embodiment, the control commands of the memory management circuit 1043 are implemented in firmware. For example, the memory management circuit 1043 has a microprocessor unit (not shown) and a read-only memory (not shown), and the above-mentioned control instructions are recorded in the read-only memory. When the memory 100 is in operation, the above control instructions will be executed by the microprocessor unit to complete the data writing method of this embodiment.

In another embodiment of the present invention, the control instructions of the memory management circuit 1043 can also be stored in a specific area of the rewritable non-volatile memory module 106 in code form (for example, the special area in the rewritable non-volatile memory module 106 in the system area where system data is stored). In addition, the memory management circuit 1043 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). Wherein, the read-only memory has a driving code segment, and when the storage controller 104 is enabled, the microprocessor unit will first execute the driving code segment to store the control instructions in the rewritable non-volatile memory module 106 Loaded into the random access memory of the memory management circuit 1043. Afterwards, the microprocessor unit executes the above control instructions to execute the data writing method of this embodiment.

In addition, in another embodiment of the present invention, the control instructions of the memory management circuit 1043 can also be implemented in a hardware form. For example, the memory management circuit 1043 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are electrically connected to the microcontroller. Wherein, the memory management unit is used for managing physical erasing units in the rewritable non-volatile memory module 106 . The memory writing unit is used for issuing a write command to the rewritable non-volatile memory module 106 to write data into the rewritable non-volatile memory module 106 . The memory reading unit is used for issuing a read command to the rewritable non-volatile memory module 106 to read data from the rewritable non-volatile memory module 106 . The memory erasing unit is used for issuing an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106 . The data processing unit is used for processing data to be written into the rewritable non-volatile memory module 106 and data read from the rewritable non-volatile memory module 106 .

The memory interface 1045 is electrically connected to the memory management circuit 1043 to electrically connect the memory controller 104 to the rewritable non-volatile memory module 106 . Accordingly, the storage controller 104 can perform related operations on the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 through the memory interface 1045 .

The buffer memory 1047 may be a static random access memory (Static Random Access Memory, SRAM), or a dynamic random access memory (Dynamic Random Access Memory, DRAM), etc., which is not limited in the present invention. The buffer memory 1047 is electrically connected to the memory management circuit 1043 for temporarily storing instructions and data from the host system 1000 or temporarily storing data from the rewritable non-volatile memory module 106 .

In another embodiment of the present invention, the storage controller 104 further includes an error checking and correction circuit 3002 . The error checking and correcting circuit 3002 is electrically connected to the memory management circuit 1043 for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 1043 receives a write command from the host system 1000, the error checking and correcting circuit 3002 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command. , ECC Code), and the memory management circuit 1043 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 1043 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 3002 will read the error checking and correction code according to the error checking and correction code. The correction code executes error checking and correction procedures on the read data to identify whether there is an error byte in the set of data.

In yet another embodiment of the present invention, the storage controller 104 further includes a power management circuit 3006 . The power management circuit 3006 is electrically connected to the memory management circuit 1043 for controlling the power of the memory 100 .

4 and 5 are schematic diagrams of managing a rewritable non-volatile memory module according to an embodiment of the present invention.

When describing the operation of the entity erasing unit of the rewritable non-volatile memory module 106 below, it is logical to operate the entity erasing unit with words such as "extract", "exchange", "group", and "rotate". the concept of. That is to say, the actual location of the physical erasing unit of the rewritable non-volatile memory module 106 is not changed, but the above operations are logically performed on the physical erasing unit of the rewritable non-volatile memory module 106 .

Referring to FIG. 4 , the rewritable non-volatile memory module 106 of this embodiment includes physical erasing units 410 ( 0 )˜410 (N). The memory management circuit 1043 in the storage controller 104 logically groups the physical erasing units 410 ( 0 )˜ 410 (N) into a data area 502 , an idle area 504 , a system area 506 and a replacement area 508 . Wherein, F, S, R and N shown in FIG. 4 are positive integers, representing the number of entity erasing units configured in each region, which can be determined by the manufacturer of the memory 100 according to the used rewritable non-volatile memory module 106. capacity to set.

The physical erase units logically belonging to the data area 502 and the free area 504 are used to store data from the host system 1000 . For example, the physical erasing unit of the data area 502 is regarded as the physical erasing unit of stored data, and the physical erasing unit of the spare area 504 is used for writing new data. In other words, the physical erasing unit of the spare area 504 is an empty or usable physical erasing unit (no recorded data or invalid data marked as useless). When receiving the write command and the data to be written from the host system 1000, the memory management circuit 1043 will extract the physical erasing unit from the spare area 504, and write the data into the extracted physical erasing unit, so as to The physical erase unit of the data area 502 is replaced. Or, when it is necessary to perform a data merging program on a logical erasing unit, the memory management circuit 1043 will extract the physical erasing unit from the spare area 504 and write data therein to replace the physical erasing unit previously mapped to this logical erasing unit. unit.

The physical erase units logically belonging to the system area 506 are used to record system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module 106, the number of physically erased units of the rewritable nonvolatile memory module 106, and the physical programming of each physically erased unit. number of units and so on.

The physical erasing units logically belonging to the replacement area 508 are used to replace the damaged physical erasing units when the physical erasing units in the data area 502 , spare area 504 or system area 506 are damaged. Specifically, during the operation of the memory 100, if there are still normal physical erasing units in the replacement area 508 and the physical erasing units in the data area 502 are damaged, the memory management circuit 1043 will extract the normal physical erasing units from the replacement area 508. Erase units to replace damaged physically erased units in the data area 502 . If there is no normal physically erased unit in the replacement area 508 and the physically erased unit is damaged, the memory management circuit 1043 declares the entire memory 100 to be in a write protect state, and data cannot be written any more.

Therefore, during the operation of the memory 100 , the physical erase units of the data area 502 , the idle area 504 , the system area 506 and the replacement area 508 will change dynamically. For example, the physical erasing unit used to alternately store data may belong to the data area 502 or the idle area 504 .

Please refer to FIG. 5, the memory management circuit 1043 groups the physical blocks 410(0)-410(F-1) of the data area 502 and the physical blocks 420(F)-420(S-1) of the spare area 504 into multiple entities Units 710(0)～710(C), 710(D)～710(E), and manage the rewritable non-volatile memory module 106 in units of physical units, wherein each physical unit includes n physical erasable Unit, n is a positive integer. C, D, and E are also positive integers, and their values are related to the values of n, F, and S. In one embodiment, each physical unit is composed of two physical erasable units. If the rewritable non-volatile memory module 106 includes two or more memory dies, the two The physical erase units may respectively belong to different memory dies. However, it must be understood that the present invention is not limited thereto. In another embodiment, each physical unit may consist of a physical erasing unit. Alternatively, in yet another embodiment, each physical unit may also be composed of at least one physical erasing unit in the same memory die or different memory dies.

In order for the host system 1000 to access the rewritable non-volatile memory module 106, the memory management circuit 1043 configures several logical units 610(0)-610(L) to map the physical unit 710 in the data area 502 (0) ~ 710 (C). Wherein, each logical unit is composed of n logical erasing units, and each logical erasing unit includes several logical programming units. Further, the logical programming units in the logical units 610(0)˜610(L) are sequentially mapped to the physical programming units in the physical units 710(0)˜710(C).

The memory management circuit 1043 provides the configured logical units 610(0)-610(L) to the host system 1000, and maintains a logical address-physical address mapping table to record the logical units 610(0)-610(L) and physical units The mapping relationship of 710(0) to 710(C). When the host system 1000 intends to access a logical access address, the memory management circuit 1043 will confirm the logical erasing unit and the logical programming unit corresponding to the logical access address, and then find the mapped logical address through the logical address-physical address mapping table The physical programming unit for access.

In this embodiment, when the host system 1000 intends to write array data into the memory 100 and issues multiple write commands continuously or intermittently, the memory management circuit 1043 receives multiple sets of data corresponding to the multiple write commands, and These multiple sets of data are temporarily stored in buffer memory 1047, wherein these multiple sets of data include a set of first type data and at least one set of second type data, and the capacity of the first type of data must be less than the critical value of data volume (for example, 16 kilobytes) section group, but the present invention is not limited thereto), and whether the capacity of the second type of data exceeds the critical value of data volume is not limited. After judging that the sets of data meet the predetermined conditions, the memory management circuit 1043 simultaneously programs the first type of data temporarily stored in the buffer memory 1047 and at least part of the second type of data into the rewritable non-volatile memory module 106 A physical programming unit group, the physical programming unit group is composed of n physical programming units, n is a positive integer, that is, the physical programming unit group can have 1 physical programming unit or a plurality of physical programming units. And the memory management circuit 1043 will simultaneously know the writing status of the first type of data and at least part of the second type of data programmed into the rewritable non-volatile memory module 106 .

For example, assume that each physical unit is composed of 4 physical erase units (ie, n is equal to 4), and the capacity of a physical program unit is 4 kilobytes. Then one physical programming unit group includes 4 physical programming units, and the capacity of one physical programming unit is 16 kilobytes. In addition, in this embodiment, it is assumed that the memory management circuit 1043 determines that the multiple sets of data are only determined when the data amount of the multiple sets of data temporarily stored in the buffer memory 1047 reaches the capacity of the physical programming unit group (that is, 4 physical programming units). Meet the predetermined conditions.

If the host system 1000 wants to write three sets of data, the data volume of the first data is 9 kilobytes, the data volume of the second data is 20 kilobytes, and the data volume of the third data is 11 kilobytes . When the host system 1000 intends to write the first data and issues the first write command, if the buffer memory 1047 has not stored any data, the memory management circuit 1043 will not program the first write data to be rewritable at this time. Instead, the first data is temporarily stored in the buffer memory 1047 instead of the non-volatile memory module 106 . In addition, the memory management circuit 1043 also records the logical access address and the number of sectors corresponding to the first data in the buffer memory 1047 .

Afterwards, the host system 1000 issues write commands corresponding to the second and third data. When the memory management circuit 1043 receives the above two write commands, it temporarily stores the corresponding second and third data in the buffer memory 1047, and stores the corresponding logical access addresses and sectors of the second and third data respectively. The number is recorded in the buffer memory 1047. Since the data volume of the multiple sets of data temporarily stored in the buffer memory 1047 has reached the capacity of the physical programming unit set, the memory management circuit 1043 judges that the multiple sets of data meet the predetermined conditions, and thus begins to actually program the data into the physical programming unit set .

As shown in FIG. 6 , in one embodiment, the memory management circuit 1043 extracts a physical unit 710 (D) from the spare area 504, assuming that the physical unit 710 (D) includes physical erasing units 410 (F), 410 (F +1), 410(F+2), 410(F+3), and each physical erasing unit includes 128 physical programming units (that is, physical programming units PF (0)～ _PF (127), _{P F+1} (0) to P _F+1 (127), P _F+2 (0) to P _F+2 (127), P _F+3 (0) to P _F+3 (127)). Since in this embodiment, the memory management circuit 1043 manages the rewritable non-volatile memory module 106 in units of physical units, the physical erasing units 410 (F), 410 (F+1), and 410 The physical programming units with corresponding positions in (F+2), 410 (F+3) will be paired to form a physical programming unit group. For example, the physical programming units PF (0), PF ₊₁ (0), PF ₊₂ (0) and PF ₊₃ (0) form the physical programming unit group FP ( 0 ), the physical programming unit _{P F} (1), PF+ ₁ (1), PF ₊₂ (1) and PF ₊₃ (1) form the physical programming unit group FP (1), and so on. In other words, when the physical unit is composed of n physical erasing units, the physical programming unit group is composed of n physical programming units among the above n physical erasing units. In this embodiment, as shown in FIG. 7 , each physical programming unit includes a data recording area D and an available redundant area RS, and their usages will be described later. The memory management circuit 1043 will sequentially obtain the physical programming unit group from the physical unit 710(D) to write data, and all the physical programming units belonging to the same physical programming unit group will be written with data together. However, since the capacity of each physical programming unit is 4 kilobytes, the data to be written must be a multiple of 4 kilobytes.

Continuing the foregoing embodiments, the memory management circuit 1043 issues a programming command to start programming operation after determining that multiple sets of data temporarily stored in the buffer memory 1047 meet predetermined conditions. As shown in FIG. 8, first, since the complete first data WD ₁ has only 9 kilobyte groups, in order to complement it as a multiple of 4 kilobyte groups, the memory management circuit 1043 additionally fills in 3 kilobyte groups Fill the data DD ₁ , and then program the complete first data WD ₁ , the additional filling data DD ₁ , and the first part of the second data WD _{2_1} (the data volume is 4 kilobytes) to the physical programming unit group FP ( 0).

Next, the memory management circuit 1043 programs the second part of the second data WD _{2_2} (the data volume is 14 kilobytes) and the padding data DD ₂ of 2 kilobytes into the physical programming unit group FP(1), and writes the second part Three parts of the second data WD _{2_3} (data size is 2 kilobytes) and 2 kilobytes of padding data DD ₃ , and the complete third data WD ₃ (data size is 11 kilobytes) and 1 kilobytes The padding data DD ₄ of the byte group is programmed into the physical programming unit group FP(2).

After completing the programming operation of the physical programming unit group FP( 2 ), the memory management circuit 1043 obtains three write states indicating that the three sets of data are normally written into the rewritable non-volatile memory module 106 . In one embodiment, the memory management circuit 1043 sends three write completion messages to the host system 1000 at this time in response to the three write commands previously received. In another embodiment, if at least one of the three sets of data is not normally written into the rewritable non-volatile memory module 106, the memory management circuit 1043 will combine the three write error messages Reply to the host system 1000, so that the host system 1000 re-issues several write commands to write the above three sets of data. In yet another embodiment, since the storage controller 104 can still receive data from the host system 1000 when the rewritable non-volatile memory module 106 is controlled to perform a programming operation, in order to prevent the host system 1000 from waiting for a response Delay the transmission of data, the memory management circuit 1043 will send out the information indicating that the writing is successful in advance, and after obtaining the writing status of multiple sets of data at the same time, when the writing status indicates that there is an error, the error information of the array will be written together. sent to the host system 1000. That is to say, the memory management circuit 1043 will reply to the host system 1000 together with several pieces of information indicating the writing states of the several write commands, but the present invention does not limit the time point of replying the information.

In the above-mentioned process of programming data into the entity programming unit group, the memory management circuit 1043 programs the actual data (that is, the first to third data in the above-mentioned embodiment) and the padding data into the entity programming unit constituting the entity programming unit group. The data recording area of the unit, and write the logical access address and the number of sectors corresponding to the actual data into the available redundant area of the physical programming unit constituting the physical programming unit group. Taking the physical programming unit group FP (0) as an example, the data recording area of the physical programming unit _PF (0) is used to write the first data of 4 kilobytes, and the logic corresponding to this part of the first data The access address and the number of sectors are then written into the available redundant area of the physical programming unit _PF (0). The data recording area of the physical programming unit _PF+1 (0) is used to write the first data of another 4 kilobyte group, and the logical access address and the number of sectors corresponding to the first data of this part can be written into the available redundant area in the physical programming unit _PF+1 (0). The data recording area of the physical programming unit _PF+2 (0) is used to write the first data of the remaining 1 kilobyte group and the padding data of the 3 kilobyte group, and the first data of this part corresponds to The logical access address and the number of sectors are written into the available redundant area in the physical programming unit _PF+2 (0). The data recording area of the physical programming unit _PF+3 (0) is used to write the second data of 4 kilobytes, and the logical access address and the number of sectors corresponding to the second data of this part are written In the available redundant area of the physical programming unit _PF+3 (0).

In addition, the memory management circuit 1043 also maintains a correspondence table to record the logical access addresses and sector numbers of the first type of data and at least part of the second type of data programmed into a certain physical programming unit group. The corresponding relationship of the physical programming unit group, and write the corresponding table to a specific physical erasing unit in the physical erasing unit 410 (0) ~ 410 (N), wherein the physical programming unit of the specific physical erasing unit is Not part of the entity programming unit group. Continuing the embodiment of FIG. 8, the memory management circuit 1043 will record the complete logical access address and sector number of the first data and the logical access address and sector of the second data of the first 4 kilobytes in the corresponding table The number corresponds to the physical programming unit group FP(0). In addition, the logical access address and the number of sectors of the second data of the 14-kilobyte group correspond to the physical programming unit group FP(1). The logical access address and sector number of the second data of the last 2 kilobyte group and the logical access address and sector number of the complete third data correspond to the physical programming unit group FP(2). Afterwards, when the physical unit 710(D) is full of data, or the memory 100 satisfies certain conditions, the memory management circuit 1043 can execute the data merging procedure according to the corresponding table.

It is worth mentioning that, if the memory management circuit 1043 has no time to record the above-mentioned correspondence in the correspondence table due to factors such as power failure of the memory 100, the memory management circuit 1043 can also read the physical unit 710 (D) when the memory 100 is powered on again. The available redundant area of the physical programming unit of each physical programming unit group in order to obtain the corresponding relationship and write it into the corresponding table.

In the above embodiment, regardless of the number of write instructions received, if at least one set of data has been received and belongs to the first type of data (that is, the capacity is less than the critical value of data volume), when temporarily stored in the buffer memory When the data volume of multiple sets of data in 1047 does not reach the capacity of one physical programming unit group (that is, the capacity of n physical programming units), the memory management circuit 1043 will continue to temporarily store the write data from the host system 1000 into the buffer The memory 1047 does not formally program the first type of data and at least part of other temporarily stored data into the physical programming unit group until the data volume of the temporarily stored multiple sets of data reaches the capacity of one physical programming unit group. Compared with programming the corresponding write data to the rewritable non-volatile memory module 106 every time a write command is received, the method adopted in this embodiment can improve the efficiency of the overall system programming procedure (program process), Accordingly, the speed of writing data in the whole system is improved and the rewritable non-volatile memory module 106 is used more efficiently. Furthermore, the memory management circuit 1043 can simultaneously know the writing status of the first type of data and at least part of other temporarily stored data, and can reply several writing completion messages to the host system 1000 at an appropriate time point to respond According to the previously received write commands, the purpose of ensuring that the data is safely written into the memory 100 is achieved.

In another embodiment, if the memory management circuit 1043 has received a set of first-type data and received one or more sets of second-type data. The memory management circuit 1043 determines that the multiple sets of data temporarily stored in the buffer memory 1047 meet a predetermined condition when the time without receiving other data exceeds a time threshold. At this time, no matter whether the data amount of the multiple sets of data temporarily stored in the buffer memory 1047 is close to the capacity of a physical programming unit group, the memory management circuit 1043 will issue programming instructions to program the first type of data and at least part of the second type of data into the entity group of programming units. Likewise, the memory management circuit 1043 will simultaneously know the writing status of the first type of data and at least part of the second type of data, and several pieces of information corresponding to the writing status of the above data will be returned to the host system 1000 together.

In the above embodiment, the memory management circuit 1043 extracts a dedicated physical unit from the idle area 504, and uses several physical programming units in it to form a physical programming unit group. Under this management framework, if the data to be written by the host system 1000 is to modify a certain set of existing data, the memory management circuit 1043 will not use the above mechanism to program the data into the physical programming unit group.

In another embodiment, the memory management circuit 1043 does not logically group the physical erasing units 410 ( 0 )˜ 410 (N) in the rewritable non-volatile memory module 106 as shown in FIG. 4 . Thus, the memory management circuit 1043 can obtain any n physical erasing units from the rewritable non-volatile memory module 106 , and use n physical programming units among them to form a physical programming unit group. However, when multiple sets of data including a first type of data and at least one second type of data are received, the above data is temporarily stored in the buffer memory 1047, and the first The detailed operation of simultaneously programming the type data and at least part of the second type data into the physical programming unit group and knowing the writing status of the actually programmed data is the same as or similar to the above-mentioned embodiment, so it will not be repeated here.

FIG. 9 is a flowchart of a data writing method according to an embodiment of the present invention, please refer to FIG. 9 .

First, as shown in step S910 , the memory management circuit 1043 receives multiple sets of data from the host system 1000 . The multiple sets of data include a first type of data and at least one second type of data, wherein the capacity of the first type of data is less than the critical value of data volume, and the capacity of the second type of data is not limited.

Then in step S920, the memory management circuit 1043 temporarily stores the multiple sets of data in the buffer memory 1047, and when it is judged that the multiple sets of data meet the predetermined conditions, the first type of data and at least part of the first type of data temporarily stored in the buffer memory 1047 The second type of data is simultaneously programmed into the physical programming unit group, which is composed of n physical programming units. Wherein, the predetermined condition is, for example, when the data amount of the multiple sets of data reaches the capacity of the physical programming unit group and/or when the memory management circuit 1043 does not receive other data for a time exceeding a time threshold.

Finally, as shown in step S930 , the memory management circuit 1043 simultaneously obtains the write status of the programmed first type data and at least part of the second type data.

To sum up, the memory, its storage controller and data writing method described in the present invention can first write the above-mentioned data when the host system wants to write a set of first-type data and at least one set of second-type data. Temporarily stored in the buffer memory, until it is determined that the temporarily stored data meets the predetermined conditions, the first type of data and at least part of the second type of data are programmed into the rewritable non-volatile memory module, thereby improving the overall Data writing efficiency. Moreover, the memory, its storage controller and data writing method described in the present invention can know the writing status of programmed data at the same time, and send corresponding pieces of information to the host system at an appropriate time in response to the received Several write instructions, so as to ensure that the data can be safely written into the memory, achieving the effect of high efficiency and data reliability.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (18)

1. A data writing method, used for a memory, the memory includes a buffer memory and a rewritable non-volatile memory module, and the rewritable non-volatile memory module has a plurality of physical erasing units , and each of these physical erasing units has a plurality of physical programming units, characterized in that, including: receiving multiple sets of data, wherein the multiple sets of data include a set of first-type data and at least one set of second-type data, wherein the capacity of the first-type data is less than a data volume threshold; Temporarily storing the multiple sets of data in the buffer memory, and programming the first type of data temporarily stored in the buffer memory and at least part of the second type of data into an entity when it is judged that the multiple sets of data meet a predetermined condition A programming unit group, wherein the physical programming unit group is composed of n physical programming units, where n is a positive integer; and At the same time, the writing status of the first type of data and the at least part of the second type of data is obtained. 2. The data writing method according to claim 1, characterized in that, when the data volume of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit set, it is determined that the multiple sets of data meet the predetermined condition. 3. The data writing method according to claim 1, wherein when the memory does not receive other data for a time exceeding a time threshold, it is determined that the multiple sets of data meet the predetermined condition. 4. The data writing method according to claim 1, wherein each of the physical programming units includes a data recording area and an available redundant area, and the first type of data temporarily stored in the buffer memory And the step of simultaneously programming at least part of the second type of data into the physical programming unit group includes: writing the first type of data and the at least part of the second type of data into the data recording area of the n physical programming units constituting the physical programming unit group; and Writing a logical access address and a sector number respectively corresponding to the first type of data and the at least part of the second type of data into the available redundant area of the n physical programming units constituting the physical programming unit group . 5. The data writing method according to claim 4, further comprising: maintaining a correspondence table to record the logical access address and the number of sectors respectively corresponding to the first type of data programmed into the physical programming unit group and the at least part of the second type of data and the physical programming unit group one-to-one correspondence; and The correspondence table is written into a specific physical erasing unit among the physical erasing units, wherein none of the physical programming units of the specific physical erasing unit belongs to the physical programming unit group. 6 . The data writing method according to claim 1 , wherein the writing states of the first type of data and the at least part of the second type of data are collectively returned to a host system that sends out the multiple sets of data. 7 . 7. A storage controller, to manage a rewritable non-volatile memory module, is characterized in that, comprising: a host system interface for electrically connecting a host system; A memory interface for electrically connecting the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical erasing units programming unit; a buffer memory; and a memory management circuit electrically connected to the host system interface, the memory interface, and the buffer memory, Wherein the memory management circuit receives multiple sets of data, wherein the multiple sets of data include a set of first type data and at least one set of second type data, wherein the capacity of the first type of data is less than a data volume threshold, The memory management circuit temporarily stores the multiple sets of data in the buffer memory, and when judging that the multiple sets of data meet a predetermined condition, simultaneously stores the first type of data and at least part of the second type of data temporarily stored in the buffer memory Programming to a physical programming unit group, wherein the physical programming unit group is composed of n physical programming units, n is a positive integer, The memory management circuit simultaneously knows the writing status of the first type of data and the at least part of the second type of data. 8. The storage controller according to claim 7, wherein when the data amount of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit group, the memory management circuit determines that the multiple sets of data meet the predetermined conditions. 9. The memory controller according to claim 7, wherein when the memory management circuit does not receive other data for a time exceeding a time threshold, the memory management circuit determines that the multiple sets of data meet the predetermined condition . 10. The storage controller according to claim 7, wherein each of the physical programming units includes a data recording area and an available redundant area, and the memory management circuit temporarily stores the data in the buffer memory When the first type of data and the at least part of the second type of data are programmed into the physical programming unit group at the same time, the first type of data and the at least part of the second type of data are written into the n pieces of the physical programming unit group the data recording area of the physical programming unit, and write a logical access address and a sector number respectively corresponding to the first type of data and the at least part of the second type of data into the n of the physical programming unit group The available redundant area of a physical programming unit. 11. The memory controller according to claim 10, wherein the memory management circuit is further used to maintain a correspondence table to record the first type of data and at least part of the first type of data programmed into the physical programming unit group A corresponding relationship between the logical access address and the number of sectors corresponding to the two types of data and the physical programming unit group, and writing the correspondence table into a specific physical erasing unit among the physical erasing units , wherein none of the physical programming units of the specific physical erasing unit belongs to the physical programming unit group. 12 . The storage controller according to claim 7 , wherein the writing statuses of the first type of data and the at least part of the second type of data are collectively returned to the host system that sent the multiple sets of data. 13 . 13. A memory, characterized in that it comprises: A rewritable non-volatile memory module, including a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units; a connector for electrically connecting to a host system; and a storage controller electrically connected to the rewritable non-volatile memory module and the connector, the storage controller includes a buffer memory, The storage controller receives multiple sets of data, wherein the multiple sets of data include a set of first-type data and at least one set of second-type data, wherein the capacity of the first-type data is less than a data volume threshold, The storage controller temporarily stores the multiple sets of data in the buffer memory, and when judging that the multiple sets of data meet a predetermined condition, simultaneously stores the first type of data and at least part of the second type of data temporarily stored in the buffer memory Programming to a physical programming unit group, wherein the physical programming unit group is composed of n physical programming units, n is a positive integer, The storage controller simultaneously knows the writing status of the first type of data and the at least part of the second type of data. 14. The memory according to claim 13, wherein when the amount of the multiple sets of data temporarily stored in the buffer memory reaches the capacity of the physical programming unit set, the storage controller determines that the multiple sets of data conform to the Booking conditions. 15. The memory according to claim 13, wherein when the memory controller does not receive other data for a time exceeding a time threshold, the memory controller determines that the sets of data meet the predetermined condition. 16. The memory according to claim 13, wherein each of the physical programming units includes a data recording area and an available redundant area, and the memory controller will temporarily store the first memory in the buffer memory When the type data and the at least part of the second type data are programmed into the physical programming unit group at the same time, the first type of data and the at least part of the second type of data are written into the n physical programming units constituting the physical programming unit group the data recording area, and write a logical access address and a sector number respectively corresponding to the first type of data and the at least part of the second type of data into the n physical programming units that make up the physical programming unit group The usable redundancy area of the unit. 17. The memory according to claim 16, wherein the memory controller is further used to maintain a correspondence table to record the first type of data and the at least part of the second type of data programmed into the physical programming unit group A corresponding relationship between the logical access address and the number of sectors corresponding to the data and the physical programming unit group, and writing the correspondence table into a specific physical erasing unit among the physical erasing units, wherein None of the physical programming units of the specific physical erasing unit belongs to the physical programming unit group. 18. The memory according to claim 13, wherein the write statuses of the first type of data and the at least part of the second type of data are collectively returned to the host system that sent the multiple sets of data.