CN103839867A - Method for improving shallow trench isolation dielectric material etching morphology - Google Patents

Abstract

The invention discloses a method for improving the etching morphology of a shallow trench isolation dielectric material, comprising: 1) using a hard mask layer as a stop layer to planarize a substrate with a shallow trench isolation structure; 2) using Carbon atoms dope the planarized surface with shallow trench isolation structure; 3) Anneal the substrate doped with carbon atoms; 4) Etch with HF to remove part of the oxidation in the shallow trench isolation structure Object surface, adjust the oxide height in the shallow trench isolation structure; 5) Remove the hard mask layer. The invention improves the shallow trench isolation morphology, eliminates the difference in the thickness of the shallow trench isolation dielectrics of different sizes, well solves the problem of shallow trench isolation corner depressions, and has obvious effects on improving the performance and stability of the device. Effect.

Description

Method for Improving Etched Topography of Shallow Trench Isolation Dielectric Material

technical field

The invention relates to a method for improving the etching appearance in the manufacture of semiconductor devices, in particular to a method for improving the etching appearance of shallow trench isolation dielectric materials.

Background technique

Shallow trench isolation (STI) is mainly used to isolate the active area from other areas on the semiconductor wafer. The trench can be etched, and the trench can be overfilled with a dielectric such as oxide, and then chemical mechanical slicing or The etching process removes excess dielectric and forms STI.

In the existing shallow trench isolation process, after CMP (chemical mechanical polishing) planarization (as shown in Figure 1), it is usually necessary to perform a step of wet etching to adjust the height of the dielectric material in the STI (as shown in Figure 2 ), and finally remove the hard mask and sacrificial oxide layer (as shown in Figure 3), usually using diluted HF to achieve the purpose of removing oxide and adjusting the dielectric height in STI. In the process of HF etching oxide, the removal rate of dielectric in different sizes of STI is different, and the oxide removal rate of narrow shallow trench isolation is higher than that of wide shallow trench isolation, resulting in different thickness of STI dielectric ( D1, D2 as shown in Figure 2). In addition, for the corner of the wide STI, due to the influence of the local high etching rate, a V depression will be formed, which is also called the STI defect (A shown in Figure 3). The defects of these STI structures will affect the subsequent patterning of polysilicon and the performance of devices, increasing the difficulty of process control.

At the same time, the existing research results show that: 1) Doping carbon atoms in the oxide can reduce the etching rate; 2) For carbon atoms, silicon nitride is more difficult to dope than silicon oxide.

Therefore, it is urgent to solve the defects of the STI dielectric layer structure caused by the different etching rates of the narrow STI structure, the wide STI structure and the corner of the STI structure.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for improving the etching morphology of the shallow trench isolation dielectric material. In the method, the surface oxide layer of the shallow trench isolation (STI) structure on the substrate is doped to eliminate the shape defect of the STI structure dielectric caused by the difference in etching rate.

In order to solve the above-mentioned technical problems, the method for improving the etching morphology of the shallow trench isolation dielectric material of the present invention includes the steps of:

1) Using the hard mask layer as a stop layer, planarize the substrate with a shallow trench isolation (STI) structure, and remove the oxide outside the area of the shallow trench isolation structure;

2) Doping the planarized surface with shallow trench isolation structure with carbon atoms;

3) Annealing the substrate doped with carbon atoms, so that the carbon atoms are evenly distributed on the oxide surface in the shallow trench isolation structure;

4) Etching with diluted HF to remove part of the oxide surface in the shallow trench isolation structure to adjust the height of the oxide in the shallow trench isolation structure;

5) Remove the hard mask layer.

平坦化的方法为化学机械研磨(CMP)。In the step 1), the hard mask layer includes: silicon nitride and silicon oxynitride; the thickness of the hard mask layer is 500-5000 Angstroms

The method of planarization is chemical mechanical polishing (CMP).

In the step 2), the depth of the doped region is 500-8000 angstroms, the doping energy is 2-65 keV, the doping dose is 1×10 ¹² to 1×10 ¹⁷ , and the doping temperature is -150-100°C; During the doping process, the hard mask layer is used as a barrier layer for ion implantation.

In the step 3), the annealing temperature is 900-1350° C., the annealing time is 50 μs-300 min, and the annealing methods include: rapid annealing (RTA), furnace annealing or laser annealing.

In the present invention, by doping the surface oxide layer of the shallow trench isolation (STI) structure on the substrate, the oxide doped with carbon atoms on the flat surface of the STI structure is in the narrow STI structure, wide STI structure and STI structure. The etch rate at the corner of the structure is basically the same, eliminating the shape defects of the STI structure dielectric caused by the difference in the etch rate, so that the STI structure achieves an ideal effect, and the process is easier to control.

Therefore, the present invention improves the STI morphology, eliminates the difference in thickness of STI dielectrics of different sizes, well solves the problem of STI corner depressions, and has obvious effects on improving the performance and stability of devices.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

FIG. 1 is a schematic diagram of a planarized shallow trench isolation structure in an existing process;

Fig. 2 is a schematic diagram of the dielectric material in the wet etching STI in the existing process, wherein, D1 is a narrow shallow trench, and D2 is a wide shallow trench;

FIG. 3 is a schematic diagram of the STI structure in which the hard mask and the sacrificial oxide layer are removed in the existing process, where A is a missing corner of the STI;

Fig. 4 is a schematic diagram of the planarized trench structure after doping in the present invention, wherein the diagram shows that the hard mask is fully doped;

Fig. 5 is a schematic diagram of removing the oxide surface in part of the STI structure by HF etching in the present invention;

Fig. 6 is a schematic diagram of the improved STI morphology of the present invention.

The reference signs in the figure are explained as follows:

1 is a hard mask layer, 2 is a sacrificial oxide layer, and 3 is a doped hard mask layer.

Detailed ways

The method for improving the etching morphology of the shallow trench isolation dielectric material of the present invention comprises the steps of:

1) Using the hard mask layer 1 as a stop layer, the substrate with the shallow trench isolation (STI) structure is planarized by chemical mechanical polishing (CMP), and the oxides outside the area of the shallow trench isolation structure are removed;

This step is like the traditional process, as shown in Figure 1;

Wherein, the material of the hard mask layer is silicon nitride or silicon oxynitride, and the thickness is

2) Doping the planarized surface with shallow trench isolation structure with carbon atoms;

Wherein, the depth of the doped region is 500-8000 angstroms, the doping energy is 2-65 keV, the doping dose is 1×10 ¹² ～1×10 ¹⁷ , and the doping temperature is -150-100°C; during the doping process, The hard mask layer 1 is used as a barrier layer for carbon ion implantation. Wherein, a schematic diagram of doping the planarized trench structure is shown in FIG. 4 .

3) Anneal the substrate doped with carbon atoms, so that the carbon atoms are uniformly distributed on the surface of the oxide (dielectric material) in the STI structure; the annealing temperature is 900-1350°C, and the annealing time is 50μs-300min , the annealing method can be rapid annealing (RTA), furnace annealing or laser annealing.

），以调整STI结构中的氧化物高度（如图5所示）；4) Use diluted HF (volume concentration of 1% to 10%) to etch and remove the oxide surface in part of the STI structure (the thickness of the removed oxide is

) to adjust the oxide height in the STI structure (as shown in Figure 5);

5) The doped hard mask layer 3 above the sacrificial oxide layer 2 is removed.

According to the above steps, the etching morphology of the shallow trench isolation dielectric material can be significantly improved, wherein the improved STI morphology can be shown in FIG. 6 . Therefore, by adopting the present invention, the difference in thickness of STI dielectrics with different sizes can be eliminated, the problem of STI corner depressions can be solved, and the performance and stability of devices can be improved.

Claims (5)

1. A method for improving the etching morphology of shallow trench isolation dielectric materials, characterized in that it comprises the steps: 1) Using the hard mask layer as a stop layer to planarize the substrate with the shallow trench isolation structure; 2) Doping the planarized surface with shallow trench isolation structure with carbon atoms; 3) Annealing the substrate doped with carbon atoms; 4) Etching with HF to remove part of the oxide surface in the shallow trench isolation structure, and adjust the height of the oxide in the shallow trench isolation structure; 5) Remove the hard mask layer. 2. The method according to claim 1, characterized in that: in the step 1), the hard mask layer includes: silicon nitride and silicon oxynitride; the thickness of the hard mask layer is 500-5000 angstroms; The method of polishing is chemical mechanical polishing. 3. The method according to claim 1, characterized in that: in the step 2), the depth of the doped region is 500-8000 Angstroms, the doping energy is 2-65 keV, and the doping dose is 1×10 ¹² - 1×10 ¹⁷ , the doping temperature is -150-100°C; during the doping process, the hard mask layer is used as a barrier layer for ion implantation. 4 . The method according to claim 1 , wherein in step 3), the annealing temperature is 900-1350° C., the annealing time is 50 μs-300 min, and the annealing methods include: rapid annealing, furnace annealing or laser annealing. 5. The method according to claim 1, characterized in that: in step 4), the volume concentration of HF is 1% to 10%; In removing part of the oxide surface in the shallow trench isolation structure, the thickness of the removed oxide is 10-1000 angstroms.

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