CN103811491A - Adjustable constant current source integrated chip and manufacturing method - Google Patents
Adjustable constant current source integrated chip and manufacturing method Download PDFInfo
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- CN103811491A CN103811491A CN201410064490.1A CN201410064490A CN103811491A CN 103811491 A CN103811491 A CN 103811491A CN 201410064490 A CN201410064490 A CN 201410064490A CN 103811491 A CN103811491 A CN 103811491A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 229920005591 polysilicon Polymers 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 16
- 239000010410 layer Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
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- 229910052719 titanium Inorganic materials 0.000 description 2
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Abstract
The invention relates to an adjustable constant current source integrated chip and a manufacturing method. The adjustable constant current source integrated chip comprises a monocrystalline silicon N-type polished wafer which serves as an N-doped region, an N+ heavily doped region is arranged on the back of the N-doped region, a triode Q2, a current regulative diode (CRD), a triode Q1 and a resistor R are arranged on the front of the N-doped region, one end of an N+ doped region of the resistor R is connected with an N+ doped region of the triode Q2, meanwhile, the N+ doped region of the resistor R serves as the cathode of the constant current source integrated chip, the other end of the N+ doped region of the resistor R is respectively connected with an N+ doped region of the triode Q1 and a P doped region of the triode Q2, a P doped region of the triode Q1 is respectively connected with a P doped region of the CRD, the P doped region of the triode Q2 and an N doped region of the triode Q2, an N doped region of the CRD is respectively connected with the P doped region and a second N+ doped region of the CRD, and the N+ heavily doped region serves as the anode of the constant current source integrated chip.
Description
Technical field
The present invention relates to a kind of integrated chip, particularly a kind of adjustable constant-flow source integrated chip and manufacture method.Belong to integrated chip technical field.
Background technology
Constant-current source is the power supply that constant current can be provided to load, is widely used in electronic circuit, and the rise of LED in recent years illumination particularly, its constant current drive scheme has promoted low cost, highly reliable constant-current source device development especially.According to the difference of constant-current source circuit chief component device, can be divided three classes: transistor constant current source (referring to Figure 14), technotron constant-current source (referring to Figure 15), integrated operational amplifier constant current source at present.Three kinds of schemes have different separately pluses and minuses, and transistor constant current source continuous current is adjustable, but dynamic electric resistor is relatively little, constant current poor-performing; Field effect constant current tube constant current better performances, but chip area utilance low (continuous current size and chip area ratio), continuous current is non-adjustable, chip yield low (technological level to manufacturing process is had relatively high expectations); Although integrated operational amplifier constant current source better performances, manufacturing process complexity, cost is higher, and transistor constant current source and integrated operational amplifier constant current source be generally the circuit of independent entry device composition, and reliability is relatively low.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of adjustable constant-flow source integrated chip and manufacture method are provided, improve constant current performance, realize the linearity adjustment of continuous current size, manufacturing process is relatively simple simultaneously, and because each assembly is all integrated on one piece of chip, high reliability, low cost are therefore realized.
The object of the present invention is achieved like this: a kind of adjustable constant-flow source integrated chip, it comprises as N
-the silicon substrate monocrystalline N of doped region
-type polished silicon wafer; At described N
-the back side of doped region is provided with N
+heavily doped region; At described N
-the front of doped region is provided with a P of triode Q2
-the 2nd P of doped region and current regulator diode CRD
-doped region; At a described P
-on doped region, doping forms a N doped region, at described the 2nd P
-on doped region, doping forms and states the 2nd N doped region; On a described N doped region, form a P doped region, at a P
-on doped region, form the 2nd P doped region, at described the 2nd P
-on doped region, form the 3rd P doped region and the 4th P doped region, at the N of silicon substrate
-on doped region, form respectively the 5th P doped region of triode Q1 and the 6th P doped region of resistance R; On a described P doped region, form a N
+doped region, at the N of silicon substrate
-on doped region, form the 2nd N
+doped region forms the 3rd N on the 5th P doped region
+doped region forms the 4th N on the 6th P doped region of resistance R
+doped region; The 4th N of described resistance R
+one end of doped region and a N
+doped region is connected, and the while is as the negative electrode of constant-current source integrated chip; Described the 4th N
+the other end of doped region respectively with the 3rd N
+doped region, a P doped region are connected; Described the 5th P doped region is connected with the 4th P doped region, the 2nd P doped region, a N doped region respectively; Described the 2nd N doped region respectively with the 3rd P doped region, the 2nd N
+doped region is connected; Described N
+heavily doped region is as the anode of constant-current source integrated chip.
Doping type N, P type to doped region exchange, and N-type becomes P type, and P type becomes N-type, and described silicon substrate front is anode, and the back side is negative electrode.
At the positive SiO of described resistance R
2on film, be provided with a polysilicon strip, make polysilicon strip form resistance R, adopt polysilicon resistance can regulate easily the temperature characterisitic of its resistance.
A manufacture method for above-mentioned adjustable constant-flow source integrated chip, said method comprising the steps of:
Between step 6 and step 7, add a step, at the SiO in described resistance R front
2deposit one deck polysilicon membrane adulterating on film, then etching forms the polysilicon strip needing, and then deposit one deck SiO
2film, as the insulating medium layer between polysilicon and lower single metal line, finally makes polysilicon strip form resistance R, adopts polysilicon resistance can regulate easily the temperature characterisitic of its resistance.
Compared with prior art, the present invention has following beneficial effect:
In circuit design:
1, conventional transistor constant current source, its triode Q1 base drive adopts resistance drive scheme, due to the linear relationship of resistor current and voltage, make the voltage clamping poor effect on continuous current adjusting resistance R1, make constant-current characteristics poor, the resistor current in the base drive resistance R 2 of triode Q1 further makes constant-current characteristics variation on the other hand; And in the present invention, triode Q1 base drive has adopted the current regulator diode CRD that electric current is less to drive, because the electric current of current regulator diode own immobilizes, therefore the voltage clamping effect on electric current adjusting resistance R1 is better, the continuous current of current regulator diode self also can not have a negative impact to total constant current dynamic electric resistor, therefore the circuit arrangement that the present invention adopts has larger constant current dynamic electric resistor, and constant-current characteristics is better.
2, continuous current size of the present invention is determined by the resistance size of resistance R substantially, therefore can adjust continuous current size by the size of adjusting resistance, and can change resistance size by the outer meeting resistance mode in parallel with resistance R, thereby realize the linearity adjustment to continuous current size, this is the not available ability of conventional junction field current regulator diode.
On integrated technique:
1, current regulator diode CRD has adopted junction type fet structure, and on process structure with bipolarity triode process compatible, simplified greatly technical process, and can by reduce P
-its operating voltage of surface doping concentration of doped region, and then improve voltage power supply scope of the present invention;
2, the design of whole chip is all the N at same silicon substrate
-on doped region, form, processing step is simple, less demanding to the working ability of manufacturing process, and 4,5 inch silicon production-line technique abilities can meet batch production requirements;
3, as long as constant-current source circuit principle of the present invention, the continuous current of current regulator diode CRD is only greater than the base current of triode Q1, and circuit can normally be worked, therefore the h of triode Q1
fEenough large, the chip area of current regulator diode CRD can be less.And conventional junction field tubular construction current regulator diode, owing to will obtaining preferably continuous current temperature coefficient, the thickness of raceway groove can not be excessive, under identical continuous current, junction field tubular construction current regulator diode chip area is much larger than chip area of the present invention, and actual flow experimental data is more than two or three times.And the ability of continuous current size of the present invention is mainly determined by triode Q1, constant current temperature coefficient can be that the emitter of negative temperature coefficient and triode Q2 and the negative temperature coefficient of base stage forward conduction voltage match by adjusting resistance R1, thereby reduces constant current temperature coefficient.Therefore the present invention, much smaller than conventional junction field current regulator diode on chip area, greatly reduces chip cost;
4, the present invention can directly adopt silicon single-crystal polishing plate processing, the field effect current regulator diode structure (silicon epitaxial material price is generally 2 ~ 3 times of silicon single-crystal polishing plate) of significantly manufacturing lower than employing epitaxy technique on silicon sheet material cost;
5, the continuous current size of conventional junction field current regulator diode is by channel thickness control, and channel thickness is seriously limited by epitaxy layer thickness uniformity, grid region junction depth uniformity, require very high to the technological ability of manufacturing, under the technological level of the silicon production line of 4,5 inch, the general less than 60% of rate of finished products, and continuous current size of the present invention is determined by the resistance size of resistance R substantially, technology controlling and process is comparatively simple, and under identical manufacturing technology level, rate of finished products can easily reach more than 90%.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of adjustable constant-flow source integrated chip that in the present invention, embodiment mono-relates to.
Fig. 2 ~ Fig. 8 is the manufacturing process flow diagram of a kind of adjustable constant-flow source integrated chip that in the present invention, embodiment mono-relates to.
Fig. 9 is the application schematic diagram of a kind of adjustable constant-flow source integrated chip that in the present invention, embodiment mono-relates to.
Figure 10 is the structural representation of a kind of adjustable constant-flow source integrated chip that in the present invention, embodiment bis-relates to.
Figure 11 ~ Figure 12 is the manufacturing process flow diagram of a kind of adjustable constant-flow source integrated chip that in the present invention, embodiment tri-relates to.
Figure 13 is the circuit theory diagrams of a kind of adjustable constant-flow of the present invention source integrated chip.
Figure 14 is typical transistors constant-current source circuit schematic diagram.
Figure 15 is typical junction field constant-current source sectional structure chart.
Wherein:
N
-doped region 1
N
+heavily doped region 2
The one P
-doped region 3
The 2nd P
-doped region 4
The one N doped region 5
The 2nd N doped region 6
The one P doped region 7
The 2nd P doped region 8
The 3rd P doped region 9
The 4th P doped region 10
The 5th P doped region 11
The 6th P doped region 12
The one N
+doped region 13
The 2nd N
+doped region 14
The 3rd N
+doped region 15
The 4th N
+doped region 16
Polysilicon strip 17.
Embodiment
The adjustable constant-flow source integrated chip and the manufacture method thereof that the present invention are proposed below in conjunction with concrete example are described in further detail.And it should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-accurate ratio, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Embodiment mono-:
Referring to Fig. 1, the present invention relates to a kind of adjustable constant-flow source integrated chip, it comprises as N
-the monocrystalline silicon N of doped region 1
-type polished silicon wafer; At described N
-the back side of doped region 1 is provided with N
+heavily doped region 2; At described N
-the front of doped region 1 is provided with a P of triode Q2
-the 2nd P of doped region 3 and current regulator diode CRD
-doped region 4; At a described P
-on doped region 3, doping forms a N doped region 5, at described the 2nd P
-on doped region 4, doping forms and states the 2nd N doped region 6; On a described N doped region 5, form a P doped region 7, at a P
-on doped region 3, form the 2nd P doped region 8, at described the 2nd P
-on doped region 4, form the 3rd P doped region 9 and the 4th P doped region 10, at the N of silicon substrate
-on doped region 1, form respectively the 5th P doped region 11 of triode Q1 and the 6th P doped region 12 of resistance R; On a described P doped region 7, form a N
+doped region 13, at the N of silicon substrate
-on doped region 1, form the 2nd N
+doped region 14 forms the 3rd N on the 5th P doped region 11
+doped region 15 forms the 4th N on the 6th P doped region 12 of resistance R
+doped region 16; The 4th N of described resistance R
+one end of doped region 16 and a N
+ doped region 13 is connected, and the while is as the negative electrode of constant-current source integrated chip; Described the 4th N
+the other end of doped region 16 respectively with the 3rd N
+doped region 15, a P doped region 7 are connected; Described the 5th P doped region 11 is connected with the 4th P doped region 10, the 2nd P doped region 8, a N doped region 5 respectively; Described the 2nd N doped region 6 respectively with the 3rd P doped region 9, the 2nd N
+doped region 14 is connected; Described N
+heavily doped region 2 is as the anode of constant-current source integrated chip.
The present invention relates to a kind of manufacture method of constant-current source integrated chip, described method comprises the steps:
Step 7, as shown in Figure 8, at a N doped region 5, the 2nd N doped region 6, a P doped region 7, the 2nd P doped region 8, the 3rd P doped region 9, the 4th P doped region 10, the 5th P doped region 11, a N
+doped region 13, the 2nd N
+doped region 14, the 3rd N
+the SiO of doped region 15
2the upper fairlead window that etches respectively, at the 4th N of resistance R
+the SiO of doped region 16
2on etch two ports of two fairlead windows as resistance R, then adopt the mode depositing metal Al of electron beam evaporation Al or sputter Al, last chemical wet etching metal A l forms the metal connecting line of each assembly, concrete annexation is: the 4th N of resistance R
+a N of one of them fairlead of doped region 16 and triode Q2
+doped region 13 is connected, and the while is as the negative electrode of constant-current source integrated chip; The 4th N of resistance R
+the 3rd N of another fairlead of doped region 16 and triode Q1
+a P doped region 7 of doped region 15, triode Q2 is connected; The 5th P doped region 11 of triode Q1 is connected with the 2nd P doped region 8 of the 4th P doped region 10 of current regulator diode CRD, triode Q2, a N doped region 5 of triode Q2; The 2nd N doped region 6 of current regulator diode CRD and the 2nd P doped region 9, the 2nd N of current regulator diode CRD
+doped region 14 is connected; N
-the back side N of doped region 1 silicon substrate
+the last mode deposit backplate metal that adopts electron beam evaporation or sputter in heavily doped region 2, as titanium, nickel, silver etc. adopt the anode of multi-layer metal structure as constant-current source integrated chip.So far, the chip manufacturing proces of the present embodiment one constant-current source integrated chip finishes.
Be illustrated in figure 9 the typical chip plane figure of the present invention application schematic diagram.For the present invention, after chip package, can carry out independent package lead pin to the two end electrodes of resistance R, at outside outer meeting resistance, form in parallel with resistance R in logic, thereby by adjusting the size of outer meeting resistance, realize the linear regulation of constant-current source integrated chip continuous current.
Embodiment bis-, as shown in figure 10, the difference of the present embodiment and embodiment mono-is, doped region doping type N, P type are exchanged, be that N-type becomes P type, P type becomes N-type, still identical in structure, the final function realizing is also identical, be that corresponding polarity of electrode is contrary, the front of silicon substrate is anode, and the back side is negative electrode.Corresponding to manufacture method, be only also that impurity type and embodiment mono-exchange, technological requirement is identical.
The main distinction of embodiment tri-, this example and example one and example two is, what assembly resistance R was wherein adopted is polysilicon resistance, silicon N trap or P trap resistance and example one and example three adopt, adopt polysilicon resistance, can regulate easily the temperature characterisitic of its resistance, thereby finally obtain satisfactory constant-current source constant current temperature characterisitic.This kind of situation ought to be the equivalent feature of the claims in the present invention.Corresponding to manufacture method, this example is identical with the front step 1 ~ step 6 of example one, and difference is:
Step 8, as shown in figure 12, at a N doped region 5, the 2nd N doped region 6, a P doped region 7, the 2nd P doped region 8, the 3rd P doped region 9, the 4th P doped region 10, the 5th P doped region 11, a N
+doped region 13, the 2nd N
+doped region 14, the 3rd N
+the SiO of doped region 15
2the upper fairlead window that etches respectively, at the SiO of polysilicon strip 17
2on etch two ports of two fairleads as resistance R, then adopt the mode depositing metal Al of electron beam evaporation Al or sputter Al, last chemical wet etching Al forms the metal connecting line of each assembly, and concrete annexation is: a N of one of them fairlead of the polysilicon strip 17 of resistance R and triode Q2
+doped region 13 is connected, and the while is as the negative electrode of constant-current source integrated chip; The 3rd N of another fairlead of the polysilicon strip 17 of resistance R and triode Q1
+a P doped region 7 of doped region 15, triode Q2 is connected; The 5th P doped region 11 of triode Q1 is connected with the 2nd P doped region 8 of the 4th P doped region 10 of current regulator diode CRD, triode Q2, a N doped region 5 of triode Q2; The 2nd N doped region 6 of current regulator diode CRD and the 2nd P doped region 9, the 2nd N of current regulator diode CRD
+doped region 14 is connected; The back side N of silicon substrate
+the last mode deposit backplate metal that adopts electron beam evaporation or sputter in heavily doped region 2, as titanium, nickel, silver etc. adopt the anode of multi-layer metal structure as constant-current source integrated chip.So far, the chip manufacturing proces of the present embodiment three constant-current source integrated chips finishes.
Claims (5)
1. an adjustable constant-flow source integrated chip, is characterized in that it comprises as N
-the monocrystalline silicon N of doped region (1)
-type polished silicon wafer, at described N
-the back side of doped region (1) is provided with N
+heavily doped region (2), at described N
-the front of doped region (1) is provided with a P of triode Q2
-the 2nd P of doped region (3) and current regulator diode CRD
-doped region (4), at a described P
-the upper doping in doped region (3) forms a N doped region (5), at described the 2nd P
-the upper doping in doped region (4) forms states the 2nd N doped region (6), and the upper P doped region (7) that forms in a described N doped region (5), at a P
-upper the 2nd P doped region (8) that forms, doped region (3), at described the 2nd P
-upper the 3rd P doped region (9) and the 4th P doped region (10) of forming, doped region (4), at the N of silicon substrate
-on doped region (1), form respectively the 5th P doped region (11) of triode (Q1) and the 6th P doped region (12) of resistance R, the upper N that forms in a described P doped region (7)
+doped region (13); At the N of silicon substrate
-upper the 2nd N that forms in doped region (1)
+doped region (14); Upper the 3rd N that forms in the 5th P doped region (11)
+doped region (15); At upper the 4th N that forms in the 6th P doped region (12) of resistance R
+doped region (16), the 4th N of described resistance R
+one end of doped region (16) and a N
+doped region (13) is connected, and the while is as the negative electrode of constant-current source integrated chip; Described the 4th N
+the other end of doped region (16) respectively with the 3rd N
+doped region (15), a P doped region (7) are connected; Described the 5th P doped region (11) is connected with the 4th P doped region (1210), the 2nd P doped region (8), a N doped region (5) respectively; Described the 2nd N doped region (6) respectively with the 3rd P doped region (9), the 2nd N
+doped region (14) is connected; Described N
+heavily doped region (2) is as the anode of constant-current source integrated chip.
2. a kind of adjustable constant-flow according to claim 1 source integrated chip, is characterized in that doped region doping type N, P type to exchange, and N-type becomes P type, and P type becomes N-type, and the front of described silicon substrate is anode, and the back side is negative electrode.
3. a kind of adjustable constant-flow according to claim 1 and 2 source integrated chip, is characterized in that the SiO in described resistance R front
2on film, be provided with a polysilicon strip (17), make polysilicon strip form resistance R, adopt polysilicon resistance can regulate easily the temperature characterisitic of its resistance.
4. a manufacture method for adjustable constant-flow as claimed in claim 1 source integrated chip, is characterized in that said method comprising the steps of:
Step 1, get a slice monocrystalline silicon N
-type polished silicon wafer, as N
-doped region silicon substrate;
Step 2, at N
-the back side heavy doping of doped region silicon substrate forms N
+heavily doped region;
Step 3, at N
-a synchronous P who forms triode Q2 on doped region
-the 2nd P of doped region and current regulator diode CRD
-doped region;
Step 4, at a P of triode Q2
-on doped region, doping forms a N doped region, at the 2nd P of current regulator diode CRD
-on doped region, doping forms the 2nd N doped region;
Step 5, on a N doped region of triode Q2, form a P doped region, at a P
-on doped region, form the 2nd P doped region; At the 2nd P of current regulator diode CRD
-on doped region, form the 3rd P doped region and the 4th P doped region, at the N of silicon substrate
-on doped region, form respectively the 5th P doped region of triode Q1 and the 6th P doped region of resistance R;
Step 6, on a P doped region of triode Q2, form a N
+doped region, at the N of silicon substrate
-on doped region, form the 2nd N
+doped region; On the 5th P doped region of triode Q1, form the 3rd N
+doped region; On the 6th P doped region of resistance R, form the 4th N
+doped region;
Step 7, in a N doped region, the 2nd N doped region, a P doped region, the 2nd P doped region, the 3rd P doped region, the 4th P doped region, the 5th P doped region, a N
+doped region, the 2nd N
+doped region, the 3rd N
+the SiO of doped region
2on etch fairlead window, wherein the 4th N of resistance R
+doped region etches two ports of two fairlead windows as resistance R, the 4th N of resistance R
+a N of one of them fairlead of doped region and triode Q2
+doped region is connected, and the while is as the negative electrode of constant-current source integrated chip; The 4th N of resistance R
+the 3rd N of another fairlead of doped region and triode Q1
+a P doped region of doped region, triode Q2 is connected; The 5th P doped region of triode Q1 is connected with the 2nd P doped region of the 4th P doped region of current regulator diode CRD, triode Q2, a N doped region of triode Q2; The 2nd N doped region of current regulator diode CRD and the 2nd P doped region of current regulator diode CRD, the 2nd N
+doped region is connected; N
-the back side N of doped region silicon substrate
+heavily doped region is as the anode of constant-current source integrated chip.
5. the manufacture method of a kind of adjustable constant-flow according to claim 4 source integrated chip, is characterized in that between step 6 and step 7, adding a step, at the SiO in described resistance R front
2on film, etch the polysilicon strip needing, then deposit one deck SiO
2film, as the insulating medium layer between polysilicon and lower single metal line, makes polysilicon strip form resistance R, adopts polysilicon resistance can regulate easily the temperature characterisitic of its resistance.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473871A (en) * | 2019-09-05 | 2019-11-19 | 成都矽能科技有限公司 | A kind of constant current device and its manufacturing method |
| CN110957352A (en) * | 2019-12-30 | 2020-04-03 | 南京融芯微电子有限公司 | A grooved power transistor GD terminal clamping structure and preparation method thereof |
| CN111725327A (en) * | 2020-08-10 | 2020-09-29 | 江苏明芯微电子股份有限公司 | An axially packaged constant current diode |
| CN113114196A (en) * | 2021-04-29 | 2021-07-13 | 全球能源互联网研究院有限公司 | Photoelectric amplification integrated triode chip |
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| CN110473871A (en) * | 2019-09-05 | 2019-11-19 | 成都矽能科技有限公司 | A kind of constant current device and its manufacturing method |
| CN110473871B (en) * | 2019-09-05 | 2024-03-26 | 成都矽能科技有限公司 | A constant current device and its manufacturing method |
| CN110957352A (en) * | 2019-12-30 | 2020-04-03 | 南京融芯微电子有限公司 | A grooved power transistor GD terminal clamping structure and preparation method thereof |
| CN111725327A (en) * | 2020-08-10 | 2020-09-29 | 江苏明芯微电子股份有限公司 | An axially packaged constant current diode |
| CN111725327B (en) * | 2020-08-10 | 2023-03-17 | 江苏明芯微电子股份有限公司 | Axially packaged constant current diode |
| CN113114196A (en) * | 2021-04-29 | 2021-07-13 | 全球能源互联网研究院有限公司 | Photoelectric amplification integrated triode chip |
| CN113114196B (en) * | 2021-04-29 | 2023-10-13 | 全球能源互联网研究院有限公司 | A photoelectric amplification integrated triode chip |
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