CN103810127B - USB low-speed devices data transfer control method and controller - Google Patents

Abstract

The invention discloses a USB low-speed device data transmission control method and a controller. The method includes: at the beginning of transmission, detecting the D+ signal line and the D-signal line of the USB low-speed device, and if the D+ signal line and the D-signal line are in an idle state, then pulling the D+ signal line high; After the line is pulled low, it directly enters the reset state and pulls up the D+ signal line; after the reset on the host side is completed, it controls the data transmission channel EP and performs data transmission with the host side. All lines are set to idle state. With the help of the technical solution of the present invention, the original USB low-speed compatible USB device only supports the USB low-speed peripheral function, the area of the controller is reduced by 50%, and the interface communication between the physical layers is correctly realized according to the USB protocol requirements Detection handshaking of transmissions and in-transit channels.

Description

USB low-speed device data transmission control method and controller

technical field

The present invention relates to the field of mobile communication, in particular to a universal serial bus (Intel Universal Serial Bus, referred to as USB) low-speed device data transmission control method and controller.

Background technique

USB is a well-known data transmission interface. Since the first draft was born in November 1994, the USB interface has become the The standard configuration of electronic equipment that requires data transmission; the application field includes fast synchronous and instant transmission of personal computers, consumer and mobile products; USB2.0 and USB3.0 are the most widely used versions of the USB interface today. .0 is backward compatible with USB2.0, and the performance comparison between the two is shown in Table 1:

Table 1

In the prior art, USB device classes (device classes) all exhibit some basic characteristics of USB, but USB devices can still be divided into some common types, and devices of the same type can have some common behavioral characteristics and working protocols, which are represented by 2 Classify some basic USB device types.

Table 2

Device type (device class) Equipment example Audio (audio) speaker communication MODEM Human Interface Device (HID) keyboard, mouse image cameras, scanners show monitor physical response device Power feedback joystick power supply uninterruptible power supply Printer device class printer Bulk memory hard disk storage device class CD_ROM, mobile hard disk

It can be seen from Table 2 that the USB Human Interface Device (Human Interface Device, HID for short) class is a relatively large class, and the HID class is mainly used in some aspects of computer operation, such as: USB mouse, USB keyboard, USB Game joystick, USB touchpad, USB trackball, telephone dialing equipment, analog tape recorder (Video Cassette Recorder, referred to as VCR) remote control and other equipment; HID exchange data storage exists in a structure called report. The host sends and requests reports in control transfers and interrupt transfers, thereby sending and receiving data. The report format is very flexible and can handle any type of data; the device can send information to the host at unexpected times, such as: keyboard keys Or the movement of the mouse, so the host will regularly poll the device to obtain the latest data; for HID devices, the transmission speed is 1.5Mbps, which belongs to low-speed peripherals; in most USB2.0 devices, low-speed peripherals Devices exist as compatible devices, but for HID devices, only low-speed device devices are required, so the low-speed peripheral parts of USB are extracted on the basis of USB2.0, and USB high-speed, full-speed, and functions are removed. The limited host (OTG) function makes the USB low-speed peripheral device smaller and more efficient; designing a low-speed (LS) transmission peripheral device is an ideal solution.

The specific application goals of the USB LS transmission peripheral device include: realizing the transmission control of the LS peripheral device at the protocol layer, controlling and detecting errors during data transmission through the UTMI (USB2.0 Transceiver Macrocell Interface) interface and the physical layer, and performing physical The data exchange between layers and internal buffer registers (buffers) communicates with the core controller through the Advanced High Performance Bus (AHB) interface of the Advanced Microcontroller Bus Architecture (AMBA) , so as to complete the basic bulk IN/OUT, control transmission, and interrupt transmission.

Figure 1 is a schematic diagram of the module of the USB LS in the prior art, as shown in Figure 1, mainly including UTM data synchronization, packet decoding and decoding, RAM control, data transmission channel (EP) control, CPU interface four parts; because usually The clock of the physical layer and the clock of the controller do not belong to the same clock domain, so the data is first synchronized by UTM, and then the decoding/decoding module processes the transmission packet, including the processing of the packet header, data transmission and CRC check; EP is USB The data transmission pipeline in the EP control module is divided into two parts: general EP control and EP0 control, and EP control during data transmission; the CPU interface allows the CPU to access the internal control and status registers of the device through the bus, as well as the FIFO of each EP , CPU interface can support 32bit data; RAM control module controls the access of single-port RAM between USB and CPU.

The USB2.0 controller in the prior art can support high-speed, full-speed/low-speed, and can be used as a host (HOST) and a device (DEVICE), or a function-limited host (OTG), such a controller can complete USB2.0 The main functions stipulated by the protocol, and its basic control state machine steps are as follows (exceptions are not listed):

Step 1. When the transmission starts, detect the D+/D- signal line. If the two are in an idle state, detect its own ID. According to the data provided by the physical layer (Physical Layer, PHY), you can judge whether the controller itself is a DEVICE or a HOST, if it is HOST, go to step 2; otherwise, go to step 5; wherein, D+ signal line and D- signal line are differential lines for USB user data transmission.

Step 2. HOST controls the UTMI signal line and pulls up and down the D+/D- line through the PHY to connect with DEVICE; go to step 3;

Step 3. Perform a reset operation after the connection is successful. During the reset process, you can judge which speed the DEVICE is through the operation on the D+/D- line of the DEVICE terminal; go to step 4;

Step 4. After the reset is completed, the controller transmits the control information and data packets according to the determined speed; after the transmission is completed, it returns to the IDLE state and waits for the next transmission;

Step 5. If it detects that the controller is DEVICE, it will enter OTG mode, initiate SRP (the wake-up part in the OTG protocol of USB2.0), and perform a wake-up operation on the HOST. When the host is successfully woken up, the controller exits OTG mode, connect to the HOST side; go to step 6;

Step 6. The host is connected to DEVICE. DEVICE resets according to the speed configured by the register. If it is high speed, then DEVCIE will first pull up the D- line, indicating high-speed reset. If it is full speed and low speed, then DEVICE will first pull up the D+ line. , means full speed/low speed reset; go to step 7;

Step 7. After the reset is completed, HOST transmits the control information and data packets according to the determined speed; the DEVIE controller receives the command token packet and responds according to the command packet, for example, transmitting data packets or handshaking and other information, and at the same time The judgment of the correct transmission of the data packet includes: CRC check, whether the transmitted data packet meets the requirements of the transmission type in the protocol, etc.; after the transmission is completed, return to the IDLE state and wait for the next transmission.

It can be seen from the above processing that in the prior art, the control of USB LS is completed together with the full-speed state machine, which wastes a lot of design resources for devices that only require LS, and for LS that only needs to use USB As far as the peripherals are concerned, full-speed and high-speed functions are not required.

Contents of the invention

The present invention provides a USB low-speed device data transmission control method and controller to solve the problem of wasting a lot of design resources for USB LS devices caused by the completion of USB LS control and full-speed and high-speed control together in the prior art question.

The present invention provides a USB low-speed device data transmission control method, including: at the beginning of the transmission, detect the D+ signal line and the D- signal line of the USB low-speed device, and if the D+ signal line and the D- signal line are both in an idle state, pull High D+ signal line; after pulling down the D+ signal line on the host side, it will directly enter the reset state and pull up the D+ signal line; after the host side reset is completed, control the data transmission channel EP and perform data transmission with the host side. After finishing, set both D+ signal line and D- signal line to idle state.

Preferably, controlling the EP specifically includes: step 1, judging whether the EP is ready to receive the token packet, if it is judged to be yes, then performing step 2, if it is judged to be no, then setting the EP to an idle state; step 2, updating the EP's The data stored in the first-in-first-out queue FIFO receives the token packet, and decodes and analyzes the token packet; step 3, judges whether the token packet carries a data packet, if it is judged to be yes, execute step 4, otherwise execute step 5; Step 4, process the token packet, return the correct response, and set the EP to the idle state; Step 5, process the token packet, if the token packet is an IN transaction transfer token, then set the EP to the sending state; If the token package transmits a token for an OUT transaction, set the EP to receive state.

Preferably, when the EP is in the sending state, the data transmission with the host side specifically includes: judging whether the EP is ready to send a data packet, if it is judged to be yes, then receiving the OUT token packet, and sending the data packet, and generating a data sending interruption at the same time to the host side, otherwise, end sending and notify the host side.

Preferably, when the EP is in the receiving state, performing data transmission with the host side specifically includes: when the EP is in the receiving state, judging whether the EP is ready to receive data packets, and if it is judged to be yes, then receiving the IN token packet and sending the data Packet, at the same time generate a send data interrupt to the host side, otherwise, end receiving, and notify the host side.

Preferably, the above method also includes: pre-configuring the number of EPs and the size of the first-in-first-out queue of each EP; automatically detecting errors in the data transmission process, notifying the host side and generating an interruption; after the data transmission stops for a predetermined time, generating Suspend interrupt, enter the suspend mode, and notify the physical layer to enter the suspend mode through the suspend signal, and exit the suspend mode after detecting the wake-up signal or reset signal, and notify the physical layer to exit the suspend mode.

The present invention also provides a controller for controlling the data transmission of the USB low-speed device, including: a detection module for detecting the D+ signal line and the D- signal line of the USB low-speed device when the transmission starts, if the D+ signal line and D- signal lines are both in the idle state, then pull up the D+ signal line; the reset module is used to directly enter the reset state after the D+ signal line is pulled down on the host side, and pull up the D+ signal line; the transmission module is used for After the reset of the host side is completed, control the data transmission channel EP and perform data transmission with the host side. After the transmission is completed, both the D+ signal line and the D- signal line are set to an idle state.

Preferably, the transmission module specifically includes: a first judging submodule, used to judge whether the EP is ready to receive the token packet, if it is judged to be yes, then call the update submodule, if it is judged to be no, then the EP is set to an idle state; The update submodule is used to update the data stored in the first-in-first-out queue FIFO of the EP; the receiving submodule is used to receive the token packet; the first processing submodule is used to decode and analyze the token packet; the second judgment The submodule is used to judge whether the token packet carries a data packet according to the processing result of the first processing submodule, if it is judged to be yes, call the second processing submodule, otherwise, call the third processing submodule; the second processing submodule , for processing the token packet, returning a correct response, and setting the EP to an idle state; the third processing submodule is used for processing the token packet, if the token packet is an IN transaction transfer token, then the EP is set to Send state; if the token packet transmits tokens for OUT transactions, set the EP to receive state.

Preferably, the transmission module specifically includes: a third judging submodule, which is used to judge whether the EP is ready to send a data packet when the EP is in the sending state, and if it is judged to be yes, then call the first sending submodule, otherwise, end the sending, And notify the host side; the first sending sub-module is used to receive the OUT token packet, send the data packet, and generate a data sending interrupt to the host side at the same time.

Preferably, the transmission module specifically includes: a fourth judging submodule, which is used to judge whether the EP is ready to receive data packets when the EP is in the receiving state, and if it is judged to be yes, then call the second sending submodule, otherwise, end the reception, And notify the host side; the second sending sub-module is used to receive the IN token packet, send the data packet, and generate a data sending interrupt to the host side at the same time.

Preferably, the above-mentioned controller further includes: a configuration module, configured to configure the number of EPs, and the size of the first-in-first-out queue of each EP; an error correction module, configured to automatically detect errors in the data transmission process, notify the host side and generate Interrupt; the suspend module is used to generate a suspend interrupt after the data transmission stops for a predetermined time, enter the suspend mode, and notify the physical layer to enter the suspend mode through the suspend signal, and exit the suspend mode after detecting the wake-up signal or reset signal, and notify The physical layer exits suspend mode.

The beneficial effects of the present invention are as follows:

By removing the control of full speed and high speed in the controller, the problem of wasting a lot of design resources in USB LS devices due to the completion of USB LS control and full speed and high speed control in the prior art is solved, making the original Compatible USB low-speed USB devices only support USB low-speed peripheral functions, the area of the controller is reduced by 50%, and the interface communication transmission between the physical layers and the detection handshake of the transmission channel are correctly realized according to the USB protocol requirements.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same parts. In the attached picture:

FIG. 1 is a schematic diagram of a module of a USB LS in the prior art;

2 is a flowchart of a USB low-speed device data transmission control method according to an embodiment of the present invention;

Fig. 3 is a connection schematic diagram of a reference scheme when the USB2.0 LS peripheral verification environment is set up according to the embodiment of the present invention;

Fig. 4 is the flowchart of the control main state transfer of the EPO of the embodiment of the present invention;

Fig. 5 is the control flowchart when EPO of the embodiment of the present invention is IDLE mode;

Fig. 6 is the control flowchart after the EPO of the embodiment of the present invention enters the sending mode;

Fig. 7 is the control flowchart after EPO of the embodiment of the present invention enters receiving mode;

FIG. 8 is a schematic diagram of a waveform reset during initialization according to an embodiment of the present invention;

9 is a schematic diagram of waveforms when EPO performs control IN control transmission according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of waveforms when EP4 performs OUT transmission according to an embodiment of the present invention;

Fig. 11 is a schematic structural diagram of a controller according to an embodiment of the present invention.

detailed description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In order to solve the problem in the prior art that USB LS equipment wastes a lot of design resources because the USB LS control is completed together with full-speed and high-speed control, the present invention provides a USB low-speed device data transmission control method and In the embodiment of the present invention, the controller, based on the structure and principle of USB2.0, is improved on the original basis, so that the original USB2.0 device compatible with USB low-speed only supports the device function of USB low-speed, so that the original USB2.0 The device can only complete the USB low-speed device (peripheral) function, which reduces the area by 50%, and correctly realizes the interface communication transmission between the physical layers and the detection handshake of the transmission channel according to the USB protocol requirements. The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

method embodiment

According to an embodiment of the present invention, a USB low-speed device data transmission control method is provided. FIG. 2 is a flow chart of a USB low-speed device data transmission control method according to an embodiment of the present invention. As shown in FIG. 2 , according to an embodiment of the present invention The USB low-speed device data transmission control method includes the following processing:

Step 201, when the transmission starts, detect the D+ signal line and the D- signal line of the USB low-speed device, and if the D+ signal line and the D- signal line are both in an idle state, then pull the D+ signal line high;

Step 202, after pulling down the D+ signal line on the host side, directly enter the reset state, and pull up the D+ signal line;

Step 203 , after the reset of the host side is completed, control the data transmission channel EP and perform data transmission with the host side, and set the D+ signal line and the D− signal line to an idle state after the transmission is completed.

In step 203, controlling the EP specifically includes:

Step 1, judge whether the EP is ready to receive the token packet, if it is judged to be yes, then perform step 2, if it is judged to be no, then the EP is set to an idle state;

Step 2, update the data stored in the first-in-first-out queue FIFO of the EP, receive the token packet, and decode and analyze the token packet;

Step 3, judging whether the token packet carries a data packet, if it is judged to be yes, go to step 4, otherwise go to step 5;

Step 4, process the token packet, return a correct response, and set the EP to an idle state;

Step 5, process the token packet, if the token packet is an IN transaction transfer token, set the EP to the sending state; if the token packet is an OUT transaction transfer token, then set the EP to the receiving state.

When the EP is in the sending state, the data transmission with the host side specifically includes: judging whether the EP is ready to send a data packet, if it is judged to be yes, then receiving the OUT token packet, sending the data packet, and generating a data sending interrupt to the host side at the same time , otherwise, end sending and notify the host side.

When the EP is in the receiving state, data transmission with the host side specifically includes: when the EP is in the receiving state, judging whether the EP is ready to receive the data packet, if it is judged to be yes, then receiving the IN token packet and sending the data packet, at the same time Generate a sending data interrupt to the host side, otherwise, end receiving and notify the host side.

Preferably, in the embodiment of the present invention, the number of EPs and the size of the first-in-first-out queue of each EP can be pre-configured; errors in the data transmission process can also be automatically detected, and the host side is notified and interrupted; when the data transmission stops After a predetermined time, generate a suspend interrupt, enter the suspend mode, and notify the physical layer to enter the suspend mode through the suspend signal, and exit the suspend mode after detecting the wake-up signal or reset signal, and notify the physical layer to exit the suspend mode.

As can be seen from the above processing, in the embodiment of the present invention, the controller performs data exchange through the UTMI interface and the physical layer, and synchronizes the clock domain of the PHY of the controller, so that the inside of the controller can work under the bus clock without the need to It is consistent with the PHY; Fig. 3 is a connection schematic diagram of a reference scheme when the USB2.0LS peripheral verification environment of the embodiment of the present invention is set up, as shown in Fig. Replace the MiniAB interface in 3 with the VIP interface of HOST, and connect it to the CPU through the bus interface (AHB interface) on the controller side.

The controller device in the embodiment of the present invention can encode, decode, correct errors and control all sent and received USB data packets. The control data flow transmitted by IN is carried out through the sending FIFO of the peripheral device, and the control data flow transmitted by OUT is carried out by the external device. The receiving FIFO is set; the controller of the embodiment of the present invention supports dynamic FIFO.

In addition, the embodiment of the present invention supports a configurable number of EPs. The number of EPs is 0~4, which can be configured according to the transmission requirements. For example, for BULK OUT operation, EP can be set as RX endpoint, and for BULKIN operation, EP can be set as TXendpoint; in addition , EP's FIFO can be configured in different sizes to meet different transmission requirements, and the transmission capability is diversified; it can accept SOF packets sent by the host (HOST), and generate SOF interrupts; and generate corresponding control interrupts during data transmission .

The controller of the embodiment of the present invention also supports the suspend (SUSPEND) operation in DEVICE mode. For example, when there is no data transmission on the USB for 3ms, the controller can generate a SUSPEND interrupt and enter the SUSPEND mode. In this mode, the controller passes the SUSPEND signal Notify the PHY to enter the SUSPEND mode. At this time, the PHY clock is turned off until the wake-up or reset signal is detected on the bus. The controller exits SUSPEND and notifies the PHY through the SUSPEND signal, and the PHY exits the SUSPEND state.

The controller in the embodiment of the present invention also supports data cyclic redundancy check (Cyclic Redundancy Check, referred to as CRC), has data error correction capability, can automatically detect protocol errors in the USB transmission process, and returns STALL packets, and generates interrupts , when the CPU receives the interrupt, it can terminate the current transmission, clear the STALL interrupt bit, and the controller automatically returns to the IDLE state.

The above technical solution of the embodiment of the present invention will be described in detail below with reference to the accompanying drawings and taking the USB2.0 version as an example.

In the prior art, for low-speed devices, many functions in the USB controller are unnecessary, for example, HOST function, high-speed part, and OTG function; Transmission control retains the control part of the low-speed part DEVICE, and the part of CRC check and protocol judgment, removes the HOST function, high-speed part and some functions of OTG; the basic control state machine steps of the embodiment of the present invention are as follows (exception is not listed out):

Step 1. When the transmission starts, detect the D+/D- signal line. If the two are in an idle state, initiate an SRP operation, that is, pull the D+ line high; wait for the response from the HOST side;

Step 2. Pull the D+ line low on the HOST side, indicating that it is awakened. The DEVICE jumps out of the SRP state and enters the reset state directly, and pulls the D+ line high; enter step 3;

Step 3. In this state, the resets of FS and LS are consistent, and both pull the D+ line high. After HOST receives the reset signal, it starts the reset operation. After the reset is completed, HOST starts the transmission of data packets and command information; Go to step 4;

Step 4. During data transmission, the state judgment of the low-speed device for the D+/D- line is opposite to full speed and high speed. The traditional controller distinguishes between full speed and low speed by judging the state of the UTMI signal linstate. Embodiments of the present invention do not need to perform Speed judgment;

Step 5. After the transmission is completed, return to the IDLE state and wait for the next transmission.

Through the above description of the main state machine of the controller, it can be seen that most of the control state and judgment parts are removed in the embodiment of the present invention, and the purpose of reducing circuit resources is achieved.

The basic USB2.0 controller also needs to complete the control of the EP. According to the USB2.0 protocol, a connection is established between the EPs to form a data transmission pipeline; the embodiment of the present invention extracts the low-speed peripherals of the USB on the basis of the USB2.0 , and control the internal state machine: including the main state machine to control the overall work of the USB device and complete the control of the internal EP of the USB device. The embodiment of the present invention adopts a separate control state machine for the control of EP, and controls the data channel of a single EP. EP0 is a special one in EP, which is used to complete initialization operations such as LINK UP. The control transmission of EP0 is used as an example to illustrate this The control process of the device to EP;

Fig. 4 is the flow chart of the control main state transfer of EP0 of the embodiment of the present invention, traditional USB controller is that software reads EP0 status register, judges whether EP0 is idle, if so, can hang up, or sends SETUP token Then enter the IDLE state; the embodiment of the present invention can also read the state of EP0 by software, but can not initiate the SETUP token, because the command token can only be sent by HOST; the EP0 of the embodiment of the present invention is directly in the IDLE state; after that , the traditional USB controller can be configured by software to make EP0 enter the sending or receiving mode; the embodiment of the present invention will wait to receive the token packet from the HOST side. If it is an IN operation, EP will enter the sending state. If it is an OUT operation, then EP enters receiving state.

Fig. 5 is the control flowchart when EP0 of the embodiment of the present invention is IDLE mode, as shown in Fig. 5, in the embodiment of the present invention, when power-on and reset, EP enters IDLE mode; In main state machine, when Perform SETUP transmission, that is, when the USB is in the enumeration state, enter the IDLE mode; after entering the IDLE mode, perform the following steps:

Step 1, prepare to receive data packet or token packet, if not ready, return to IDLE state, after turning to standby, go to step 2;

Step 2, update the data stored in the FIFO and receive the command;

Step 3, after receiving the command, decode and analyze the command, and judge whether the command token has a data packet according to the protocol of USB2.0, if there is no data packet, go to step 4, otherwise go to step 5;

Step 4, process the token packet, set the data, and return the correct response, and return to the IDLE state;

Step 5, process the token packet and set the data; judge whether it is an IN transaction transfer token, if yes, enter the sending mode (Figure 6), if not, enter step 6;

Step 6, enter the OUT transaction transmission, and enter the receiving mode (Figure 7).

Fig. 6 is the control flowchart after EP0 enters the sending mode of the embodiment of the present invention, as shown in Fig. 6, if EP0 is TX mode, traditional USB controller can send and receive OUT token packet, the embodiment of the present invention can only receive OUT token packet; all received IN token packets will be treated as data. If the SETUP command or OUT token packet is received at this time, the SETUPEND condition will be generated, and EP0 will exit the TX mode. In addition, if the transmitted data packet The length of the EP0 is less than the maximum packet length configured by EP0, or the USB exits this state when an empty packet is received; the TX mode of other EPs is similar to this, and the processing steps are as follows:

Step 1: Judgment of the ready-to-send packet. If it is not ready, end the sending directly and return a STALL response, indicating that the data is not ready, otherwise go to step 2;

Step 2, receive the OUT token packet, send the DATA0 data packet, and generate a data sending interrupt to the CPU at the same time;

Step 3, the OUT transaction ends.

Fig. 7 is the control flow chart of the EPO of the embodiment of the present invention after entering the receiving mode, as shown in Fig. 7, when EPO is in the RX mode, the traditional USB controller can send and receive the IN token packet, but the embodiment of the present invention can only receive IN token packet; all received OUT token packets will be treated as data, if a SETUP or OUT token packet is received, a SETUPEND condition will be generated, and the RX mode will terminate; in addition, if the host sends an invalid token packet or an empty packet, or the length of the sent packet is less than the maximum packet length, the SETUPEND condition will also be generated; the TX mode of its EP is similar to this, and the processing steps are as follows:

Step 1: Judgment of ready to receive packets. If it is not turned to standby, stop sending directly and return a STALL response, indicating that the data is not ready, otherwise go to step 2;

Step 2, after receiving the IN token packet, send the data packet, and generate a data sending interrupt to the CPU at the same time;

Step 3, the IN transaction ends.

In the embodiment of the present invention, the state of the controller is mainly controlled by the physical layer interface signal DP/DM signal, which is expressed as two states, K state and J state; the state is represented by the linestate of the UTMI signal interface, specifically as follows : assign j = linestate[1] &~linestate[0]; assign k = ~linestate[1] & linestate[0]. Fig. 8 is a schematic diagram of the reset waveform during initialization of the embodiment of the present invention. As shown in Fig. 8, the dm signal is pulled high, and dp remains unchanged. After the SE0 state, the dm signal is pulled high; Fig. 9 is the control of EP0 in the embodiment of the present invention The schematic diagram of the waveform during IN control transmission is shown in Figure 9. One of the SETADDR data packets is as follows: the HOST end sets the address to 5b, the controller responds to the token packet as d2, and the CLK is 1.5Mbps; Figure 10 is an embodiment of the present invention The waveform diagram of EP4 performing OUT transmission is shown in Figure 10, and the data length is 64.

To sum up, with the help of the technical solution of the embodiment of the present invention, by removing the control of full speed and high speed in the controller, the problem caused by the completion of USB LS control and full speed and high speed control in the prior art is solved. USBLS equipment wastes a lot of design resources, so that the original USB low-speed compatible USB device only supports USB low-speed peripheral functions, the area of the controller is reduced by 50%, and the physical layer is correctly implemented according to the USB protocol requirements. Inter-interface communication transmission and channel detection handshake during transmission.

Device embodiment

According to an embodiment of the present invention, a controller is provided for controlling data transmission of a USB low-speed device. FIG. 11 is a schematic structural diagram of a controller according to an embodiment of the present invention. As shown in FIG. 11, the The controller includes: a detection module 110, a reset module 112, and a transmission module 114, each module of the embodiment of the present invention will be described in detail below.

The detection module 110 is used to detect the D+ signal line and the D-signal line of the USB low-speed device at the beginning of the transmission, and if the D+ signal line and the D-signal line are in an idle state, then pull the D+ signal line high;

The reset module 112 is used to directly enter the reset state after pulling the D+ signal line low on the host side, and pull the D+ signal line high;

The transmission module 114 is used to control the data transmission channel EP and perform data transmission with the host side after the reset of the host side is completed, and set the D+ signal line and the D- signal line to an idle state after the transmission is completed.

The transmission module 114 specifically includes:

The first judging submodule is used to judge whether the EP is ready to receive the token packet, if it is judged to be yes, then call the update submodule, if it is judged to be no, then the EP is set to idle state;

The update submodule is used to update the data stored in the first-in-first-out queue FIFO of the EP;

The receiving submodule is used to receive the token packet;

The first processing sub-module is used to decode and analyze the token packet;

The second judging submodule is used to judge whether the token packet carries a data packet according to the processing result of the first processing submodule, if it is judged to be yes, call the second processing submodule, otherwise, call the third processing submodule;

The second processing submodule is used to process the token packet, return a correct response, and set the EP to an idle state;

The third processing submodule is used to process the token package, if the token package is an IN transaction transmission token, the EP is set to the sending state; if the token package is an OUT transaction transmission token, the EP is set to the receiving state .

The third judging submodule is used to judge whether the EP is ready to send data packets when the EP is in the sending state, and if it is judged to be yes, then call the first sending submodule, otherwise, end sending and notify the host side;

The first sending sub-module is used to receive the OUT token packet, send the data packet, and generate a data sending interrupt to the host side at the same time.

The fourth judging submodule is used to judge whether the EP is ready to receive the data packet when the EP is in the receiving state, if it is judged to be yes, then call the second sending submodule, otherwise, end the receiving, and notify the host side;

The second sending sub-module is used to receive the IN token packet, send the data packet, and generate a data sending interrupt to the host side at the same time.

Preferably, in the embodiment of the present invention, the controller further includes:

The configuration module is used to configure the number of EPs and the size of the first-in-first-out queue of each EP;

An error correction module is used to automatically detect errors in the data transmission process, notify the host side and generate an interruption;

The suspend module is used to generate a suspend interrupt after the data transmission stops for a predetermined time, enter the suspend mode, and notify the physical layer to enter the suspend mode through the suspend signal, and exit the suspend mode after detecting the wake-up signal or reset signal, and notify the physical layer Exit suspend mode.

As can be seen from the above processing, in the embodiment of the present invention, the controller performs data exchange through the UTMI interface and the physical layer, and synchronizes the clock domain of the PHY of the controller, so that the inside of the controller can work under the bus clock without the need to It is consistent with the PHY; Fig. 3 is a connection schematic diagram of a reference scheme when the USB2.0 LS peripheral verification environment of the embodiment of the present invention is set up. As shown in Fig. 3, when the controller is connected to the PHY, only the The MiniAB interface in Figure 3 is replaced by the VIP interface of the HOST, and the controller can be connected to the CPU through the bus interface (AHB interface).

The controller device in the embodiment of the present invention can encode, decode, correct errors and control all sent and received USB data packets. The control data flow transmitted by IN is carried out through the sending FIFO of the peripheral device, and the control data flow transmitted by OUT is carried out by the external device. The receiving FIFO is set; the controller of the embodiment of the present invention supports dynamic FIFO.

In addition, the embodiment of the present invention supports a configurable number of EPs. The number of EPs is 0~4, which can be configured according to the transmission requirements. For example, for BULK OUT operation, EP can be set as RX endpoint, and for BULKIN operation, EP can be set as TXendpoint; in addition , EP's FIFO can be configured in different sizes to meet different transmission requirements, and the transmission capability is diversified; it can accept SOF packets sent by the host (HOST), and generate SOF interrupts; and generate corresponding control interrupts during data transmission .

The controller of the embodiment of the present invention also supports the suspend (SUSPEND) operation in DEVICE mode. For example, when there is no data transmission on the USB for 3ms, the controller can generate a SUSPEND interrupt and enter the SUSPEND mode. In this mode, the controller passes the SUSPEND signal Notify the PHY to enter the SUSPEND mode. At this time, the PHY clock is turned off until the wake-up or reset signal is detected on the bus. The controller exits SUSPEND and notifies the PHY through the SUSPEND signal, and the PHY exits the SUSPEND state.

The controller in the embodiment of the present invention also supports data cyclic redundancy check (Cyclic Redundancy Check, referred to as CRC), has data error correction capability, can automatically detect protocol errors in the USB transmission process, and returns STALL packets, and generates interrupts , when the CPU receives the interrupt, it can terminate the current transmission, clear the STALL interrupt bit, and the controller automatically returns to the IDLE state.

The above technical solution of the embodiment of the present invention will be described in detail below with reference to the accompanying drawings and taking the USB2.0 version as an example.

In the prior art, for low-speed devices, many functions in the USB controller are unnecessary, for example, HOST function, high-speed part, and OTG function; Transmission control retains the control part of the low-speed part DEVICE, and the part of CRC check and protocol judgment, removes the HOST function, high-speed part and some functions of OTG; the basic control state machine steps of the embodiment of the present invention are as follows (exception is not listed out):

Step 1. When the transmission starts, detect the D+/D- signal line. If the two are in an idle state, initiate an SRP operation, that is, pull the D+ line high; wait for the response from the HOST side;

Step 2. Pull the D+ line low on the HOST side, indicating that it is awakened. The DEVICE jumps out of the SRP state and enters the reset state directly, and pulls the D+ line high; enter step 3;

Step 3. In this state, the resets of FS and LS are consistent, and both pull the D+ line high. After HOST receives the reset signal, it starts the reset operation. After the reset is completed, HOST starts the transmission of data packets and command information; Go to step 4;

Step 4. During data transmission, the state judgment of the low-speed device for the D+/D- line is opposite to full speed and high speed. The traditional controller distinguishes between full speed and low speed by judging the state of the UTMI signal linstate. Embodiments of the present invention do not need to perform Speed judgment;

Step 5. After the transmission is completed, return to the IDLE state and wait for the next transmission.

Through the above description of the main state machine of the controller, it can be seen that most of the control state and judgment parts are removed in the embodiment of the present invention, and the purpose of reducing circuit resources is achieved.

The basic USB2.0 controller also needs to complete the control of the EP. According to the USB2.0 protocol, a connection is established between the EPs to form a data transmission pipeline; the embodiment of the present invention extracts the low-speed peripherals of the USB on the basis of the USB2.0 , and control the internal state machine: including the main state machine to control the overall work of the USB device and complete the control of the internal EP of the USB device. The embodiment of the present invention adopts a separate control state machine for the control of EP, and controls the data channel of a single EP. EP0 is a special one in EP, which is used to complete initialization operations such as LINK UP. The control transmission of EP0 is used as an example to illustrate this The control process of the device to EP;

Fig. 4 is the flow chart of the control main state transfer of EP0 of the embodiment of the present invention, traditional USB controller is that software reads EP0 status register, judges whether EP0 is idle, if so, can hang up, or sends SETUP token Then enter the IDLE state; the embodiment of the present invention can also read the state of EP0 by software, but can not initiate the SETUP token, because the command token can only be sent by HOST; the EP0 of the embodiment of the present invention is directly in the IDLE state; after that , the traditional USB controller can be configured by software to make EP0 enter the sending or receiving mode; the embodiment of the present invention will wait to receive the token packet from the HOST side. If it is an IN operation, EP will enter the sending state. If it is an OUT operation, then EP enters receiving state.

Fig. 5 is the control flowchart when EP0 of the embodiment of the present invention is IDLE mode, as shown in Fig. 5, in the embodiment of the present invention, when power-on and reset, EP enters IDLE mode; In main state machine, when Perform SETUP transmission, that is, when the USB is in the enumeration state, enter the IDLE mode; after entering the IDLE mode, perform the following steps:

Step 1, prepare to receive data packet or token packet, if not ready, return to IDLE state, after turning to standby, go to step 2;

Step 2, update the data stored in the FIFO and receive the command;

Step 3, after receiving the command, decode and analyze the command, and judge whether the command token has a data packet according to the protocol of USB2.0, if there is no data packet, go to step 4, otherwise go to step 5;

Step 4, process the token packet, set the data, and return the correct response, and return to the IDLE state;

Step 5, process the token packet and set the data; judge whether it is an IN transaction transfer token, if yes, enter the sending mode (Figure 6), if not, enter step 6;

Step 6, enter the OUT transaction transmission, and enter the receiving mode (Figure 7).

Fig. 6 is the control flowchart after EP0 enters the sending mode of the embodiment of the present invention, as shown in Fig. 6, if EP0 is TX mode, traditional USB controller can send and receive OUT token packet, the embodiment of the present invention can only receive OUT token packet; all received IN token packets will be treated as data. If the SETUP command or OUT token packet is received at this time, the SETUPEND condition will be generated, and EP0 will exit the TX mode. In addition, if the transmitted data packet The length of the EP0 is less than the maximum packet length configured by EP0, or the USB exits this state when an empty packet is received; the TX mode of other EPs is similar to this, and the processing steps are as follows:

Step 1: Judgment of the ready-to-send packet. If it is not ready, end the sending directly and return a STALL response, indicating that the data is not ready, otherwise go to step 2;

Step 2, receive the OUT token packet, send the DATA0 data packet, and generate a data sending interrupt to the CPU at the same time;

Step 3, the OUT transaction ends.

Fig. 7 is the control flow chart of the EPO of the embodiment of the present invention after entering the receiving mode, as shown in Fig. 7, when EPO is in the RX mode, the traditional USB controller can send and receive the IN token packet, but the embodiment of the present invention can only receive IN token packet; all received OUT token packets will be treated as data, if a SETUP or OUT token packet is received, a SETUPEND condition will be generated, and the RX mode will terminate; in addition, if the host sends an invalid token packet or an empty packet, or the length of the sent packet is less than the maximum packet length, the SETUPEND condition will also be generated; the TX mode of its EP is similar to this, and the processing steps are as follows:

Step 1: Judgment of ready to receive packets. If it is not turned to standby, stop sending directly and return a STALL response, indicating that the data is not ready, otherwise go to step 2;

Step 2, after receiving the IN token packet, send the data packet, and generate a data sending interrupt to the CPU at the same time;

Step 3, the IN transaction ends.

In the embodiment of the present invention, the state of the controller is mainly controlled by the physical layer interface signal DP/DM signal, which is expressed as two states, K state and J state; the state is represented by the linestate of the UTMI signal interface, specifically as follows : assign j=linestate[1] &~linestate[0]; assign k=~linestate[1]&linestate[0]. Fig. 8 is a schematic diagram of the reset waveform during initialization of the embodiment of the present invention. As shown in Fig. 8, the dm signal is pulled high, and dp remains unchanged. After the SE0 state, the dm signal is pulled high; Fig. 9 is the control of EP0 in the embodiment of the present invention The schematic diagram of the waveform during IN control transmission is shown in Figure 9. One of the SETADDR data packets is as follows: the HOST end sets the address to 5b, the controller responds to the token packet as d2, and the CLK is 1.5Mbps; Figure 10 is an embodiment of the present invention The waveform diagram of EP4 performing OUT transmission is shown in Figure 10, and the data length is 64.

To sum up, with the help of the technical solution of the embodiment of the present invention, by removing the control of full speed and high speed in the controller, the problem caused by the completion of USB LS control and full speed and high speed control in the prior art is solved. USBLS equipment wastes a lot of design resources, so that the original USB low-speed compatible USB device only supports USB low-speed peripheral functions, the area of the controller is reduced by 50%, and the physical layer is correctly implemented according to the USB protocol requirements. Inter-interface communication transmission and channel detection handshake during transmission.

The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other device. Various generic systems can also be used with the teachings based on this. The structure required to construct such a system is apparent from the above description. Furthermore, the present invention is not specific to any particular programming language. It should be understood that various programming languages can be used to implement the content of the present invention described herein, and the above description of specific languages is for disclosing the best mode of the present invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, in order to streamline this disclosure and to facilitate an understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings), as well as any method or method so disclosed, may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will understand that although some embodiments described herein include some features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention. and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all functions of some or all components in the controller according to the embodiments of the present invention. The present invention can also be implemented as an apparatus or an apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program for realizing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet site, or provided on a carrier signal, or provided in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims (10)

1. a kind of USB low-speed devices data transfer control method, it is characterised in that including：

When transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices are detected, if the D+ signal wires and the D- Signal wire is in idle condition, then draws high D+ signal wires；

After host computer side drags down the D+ signal wires, reset state is directly entered, and draw high D+ signal wires；

After the completion of host computer side reset, control data transmission channel EP simultaneously carries out data transmission with the host computer side, is passing After defeated end, the D+ signal wires and the D- signal wires are disposed as idle condition；

Methods described, in addition to：Pre-set EP First Input First Output FIFO size；

After data transfer stops the scheduled time, produce pause and interrupt, physics is notified into park mode, and by halt signal Layer enters park mode, after wake-up signal or reset signal is detected, exits the park mode, and notify the physical layer Exit the park mode.

2. the method as described in claim 1, it is characterised in that the control EP is specifically included：

Step 1, judge whether EP is ready to receive token packet, if the judgment is Yes, then perform step 2, if the judgment is No, then The EP is set to idle condition；

Step 2, the data stored in the First Input First Output FIFO for updating the EP, receive the token packet, and to the order Board bag enters row decoding parsing；

Step 3, judge whether the token packet carries packet, if the judgment is Yes, perform step 4, otherwise perform step 5；

Step 4, the token packet is handled, correct response is returned to, and the EP is set to idle condition；

Step 5, the token packet is handled, if the token packet is IN business transmission tokens, the EP is set to send State；If the token packet, which is OUT transaction, transmits token, the EP is set to reception state.

3. method as claimed in claim 2, it is characterised in that when the EP is transmission state, carried out with the host computer side Data transfer is specifically included：

Judge whether the EP is ready for packet, if the judgment is Yes, then receive OUT token packets, and send packet, Produce simultaneously and send data outage to the host computer side, otherwise, terminate to send, and notify the host computer side.

4. method as claimed in claim 2, it is characterised in that when the EP is reception state, carried out with the host computer side Data transfer is specifically included：

When the EP is reception state, judges whether the EP gets out received data packet, if the judgment is Yes, then receive IN Token packet, and packet is sent, data outage is sent to the host computer side while producing, and otherwise, terminates to receive, and notify described Host computer side.

5. the method as described in claim 1, it is characterised in that methods described also includes：

It is pre-configured with EP number；

Mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption.

6. a kind of controller, it is characterised in that the data transfer for controlling USB low-speed devices, the controller is specifically included：

Detection module, for when transmitting beginning, the D+ signal wires and D- signal wires of USB low-speed devices being detected, if the D+ Signal wire and the D- signal wires are in idle condition, then draw high D+ signal wires；

Reseting module, for after host computer side drags down the D+ signal wires, being directly entered reset state, and draw high D+ signals Line；

Transport module, for after the completion of host computer side reset, control data transmission channel EP simultaneously to be carried out with the host computer side Data transfer, after the end of transmission, idle condition is disposed as by the D+ signal wires and the D- signal wires；

Configuration module, the size of the First Input First Output for pre-setting EP；

Suspend module, interrupted for after data transfer stops the scheduled time, producing pause, into park mode, and by temporary Stopping signal notifies physical layer to enter park mode, after wake-up signal or reset signal is detected, exits the park mode, and The physical layer is notified to exit the park mode.

7. controller as claimed in claim 6, it is characterised in that the transport module is specifically included：

First judging submodule, for judging whether EP is ready to receive token packet, if the judgment is Yes, then calls renewal submodule Block, if the judgment is No, is then set to idle condition by the EP；

Update the data stored in submodule, the First Input First Output FIFO for updating the EP；

Receiving submodule, for receiving the token packet；

First processing submodule, for entering row decoding parsing to the token packet；

Second judging submodule, for judging whether the token packet carries according to the result of the described first processing submodule There is packet, if the judgment is Yes, call second processing submodule, otherwise, call the 3rd processing submodule；

Second processing submodule, for handling the token packet, returns to correct response, and the EP is set into idle shape State；

3rd processing submodule,, will be described if the token packet is IN business transmission tokens for handling the token packet EP is set to transmission state；If the token packet, which is OUT transaction, transmits token, the EP is set to reception state.

8. controller as claimed in claim 7, it is characterised in that the transport module is specifically included：

3rd judging submodule, for when the EP is transmission state, judging whether the EP is ready for packet, such as Fruit is judged as YES, then calls the first sending submodule, otherwise, terminates to send, and notify the host computer side；

First sending submodule, for receiving OUT token packets, and sends packet, data outage is sent to described while producing Host computer side.

9. controller as claimed in claim 7, it is characterised in that the transport module is specifically included：

4th judging submodule, for when the EP is reception state, judging whether the EP gets out received data packet, such as Fruit is judged as YES, then calls the second sending submodule, otherwise, terminates to receive, and notify the host computer side；

Second sending submodule, for receiving IN token packets, and sends packet, data outage is sent to the master while producing Pusher side.

10. controller as claimed in claim 6, it is characterised in that the controller further comprises：

Configuration module, the number for configuring EP；

Correction module, for the mistake in automatic detection data transmitting procedure, notifies host computer side and produces interruption.