CN103777732A - Control method of connector, connector and memory storage device - Google Patents

Abstract

A control method of a connector, a memory storage device and the connector are provided. The control method comprises the following steps: receiving the first signal string with a squelch detector of the connector turned off; determining whether the first signal string comprises a burst signal at a first operating frequency; if the first signal string comprises a burst signal, the squelch detector is started, and the squelch detector judges whether a second signal string is a wake-up signal under a second operating frequency, wherein the second signal string is received after the first signal string, and the second operating frequency is greater than the first operating frequency. The control method further comprises: if the second signal string is a wake-up signal, the operation state of the connector is changed to a starting state. Therefore, the power consumption of the connector can be reduced.

Description

Connector control method, connector and memory storage device

technical field

The invention relates to a method for controlling a connector, a connector using the method and a memory storage device.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (such as flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable devices such as the above examples. in the multimedia device.

Generally, the rewritable non-volatile memory module is controlled by a memory controller, and the memory controller is coupled to a host system through a connector. Depending on the standard to which the connector complies, typically the operational states of the connector will include at least an enabled state and a non-enabled state. In the boot state, the host system can access the rewritable non-volatile memory module. In the inactive state, the memory controller can turn off some of its components or functions, thereby saving power consumption. However, in the inactive state, the connector must detect a signal from the host system to determine whether to return to the active state. That is to say, some components in the connector must continue to operate to detect the signal transmitted by the host system. Therefore, how to further save the power consumed by the connector in the non-activated state is an issue concerned by those skilled in the art.

Contents of the invention

An exemplary embodiment of the present invention provides a method for controlling a connector, a connector and a memory storage device, which can save power consumption of the connector in a non-activated state.

An exemplary embodiment of the invention provides a method for controlling a connector. The control method includes: receiving a first signal string when a squelch detector of the connector is turned off; judging whether the first signal string includes a burst signal at a first operating frequency; if the first signal string includes The burst signal starts the squelch detector, and the squelch detector judges whether the second signal string is a wake-up signal at the second operating frequency, wherein the second signal string is received after the first signal string, and the second The operating frequency is greater than the first operating frequency. The control method further includes: if the second signal string is a wake-up signal, changing the operation state of the connector to an activated state.

In an exemplary embodiment, the above control method further includes: if the second signal string is not a wake-up signal, turning off the squelch detector, receiving a third signal, and determining whether the third signal includes a burst signal.

In an exemplary embodiment, the above-mentioned step of judging whether the first signal string includes a burst signal at the first operating frequency includes: judging whether the first signal string includes a burst signal whose length is greater than or equal to n unit intervals at the first operating frequency signal, wherein n is a positive integer greater than or equal to 2; and if the first signal string includes the sub-signal, it is judged that the first signal string includes a burst signal.

In an exemplary embodiment, the positive integer n mentioned above is 5.

In an exemplary embodiment, the step of judging by the squelch detector whether the second signal string is a wake-up signal at the second operating frequency includes: judging by the squelch detector whether the second signal string includes m burst signals, Where m is a positive integer; if the second signal string includes m burst signals, the squelch detector determines that the second signal string is a wake-up signal.

An exemplary embodiment of the invention provides a memory storage device. The memory storage device includes a connector, a rewritable non-volatile memory module and a memory controller. The connector is used to couple to a host system. The rewritable non-volatile memory module includes multiple physical erasing units. The memory controller is coupled to the connector and the rewritable non-volatile memory module. The aforementioned connector includes a state controller, a squelch detector and a burst detector. The squelch detector is coupled to the state controller. The burst detector is coupled to the squelch detector, and is used for receiving the first signal string when the squelch detector is turned off, and judging whether the first signal string includes a burst signal at the first operating frequency. If the first signal string includes a burst signal, the burst detector is used to activate the squelch detector. After the squelch detector is woken up, the squelch detector is used to judge whether the second signal string is a wake-up signal at the second operating frequency, wherein the second signal string is received after the first signal string, and the second operation The frequency is greater than the first operating frequency. If the second signal string is a wake-up signal, the state controller is used to change the operation state of the connector to an activated state.

In an exemplary embodiment, if the second signal string is not a wake-up signal, the burst detector is also used to turn off the squelch detector, receive a third signal, and determine whether the third signal includes a burst signal.

In an exemplary embodiment, the operation of the above-mentioned burst detector judging whether the first signal string includes a burst signal at the first operating frequency includes: the burst detector judging whether the first signal string includes a length at the first operating frequency sub-signals greater than or equal to n unit intervals, wherein n is a positive integer greater than or equal to 2; if the first signal string includes sub-signals, the squelch detector will determine that the first signal string includes burst signals.

In an exemplary embodiment, the positive integer n mentioned above is 5.

In an exemplary embodiment, the operation of the squelch detector determining whether the second signal string is a wake-up signal includes: the squelch detector judging whether the second signal string includes m burst signals, wherein m is a positive integer; The two signal strings include m burst signals, and the squelch detector determines that the second signal string is a wake-up signal.

An exemplary embodiment of the invention provides a connector including a state controller, a squelch detector and a burst detector. The squelch detector is coupled to the state controller. The burst detector is coupled to the squelch detector for receiving the first signal string when the squelch detector is turned off, and judging whether the first signal string includes a burst signal at the first operating frequency. If the first signal string includes a burst signal, the burst detector activates the squelch detector. After the squelch detector is woken up, the squelch detector is used to judge whether the second signal string is a wake-up signal at the second operating frequency, wherein the second signal string is received after the first signal string, and the second operation The frequency is greater than the first operating frequency. If the second signal string is a wake-up signal, the state controller is used to change the operation state of the connector to an activated state.

In an exemplary embodiment, if the second signal string is not a wake-up signal, the burst detector is also used to turn off the squelch detector, receive a third signal, and determine whether the third signal includes a burst signal.

In an exemplary embodiment, the operation of the above-mentioned burst detector judging whether the first signal string includes a burst signal at the first operating frequency includes: the burst detector judging whether the first signal string includes a length at the first operating frequency A sub-signal greater than or equal to n unit intervals, wherein n is a positive integer greater than or equal to 2; if the first signal string includes a sub-signal, the squelch detector determines that the first signal string includes a burst signal.

In an exemplary embodiment, the positive integer n mentioned above is 5.

In an exemplary embodiment, the operation of the squelch detector determining whether the second signal string is a wake-up signal includes: the squelch detector judging whether the second signal string includes m burst signals, wherein m is a positive integer; The two signal strings include m burst signals, and the squelch detector determines that the second signal string is a wake-up signal.

In an exemplary embodiment, the aforementioned burst detector includes a low power squelch detector and a squelch detector control circuit. The above squelch detector includes a squelch detection circuit and an out-of-frequency signal judgment circuit. The squelch detector control circuit is coupled to the low power squelch detector. The squelch detection circuit is coupled to the squelch detector control circuit. The out-of-frequency signal judgment circuit is coupled to the squelch detection circuit and the state controller. The low-power squelch detector is used for receiving the first signal string when the squelch detection circuit is turned off, and judging whether the first signal string includes a burst signal under the first operating frequency. If the first signal string includes a burst signal, the squelch detector control circuit is used to activate the squelch detection circuit. After the squelch detection circuit is activated, the squelch detection circuit is used to detect the second burst signal and interval signal in the second signal string at the second operating frequency, and the out-of-frequency signal judgment circuit is used to detect the second burst signal and the interval signal according to the second burst The signal and interval signal determine whether the second signal string is a wake-up signal.

An exemplary embodiment of the present invention proposes a connector conforming to the Serial Advanced Accessory standard. The connector includes a low frequency signal detector, a signal detector control circuit, a high frequency detector, a high frequency signal judging circuit and a state controller. The signal detector control circuit is coupled to the low frequency signal detector. The high frequency detector is coupled to the signal detector control circuit. The high frequency signal judging circuit is coupled to the high frequency detector. The state controller is coupled to the signal detector control circuit and the high frequency signal judging circuit. The low-frequency signal detector is used for receiving the first signal string when the high-frequency detector is turned off, and judging whether the first signal string includes a first signal pattern under the first operating frequency. If the first signal string includes the first signal pattern, the signal detector control circuit is used to activate the high frequency detector. After the high frequency detector is activated, the high frequency detector is used to detect whether the second signal string includes a second signal pattern at the second operating frequency. Wherein the second signal string is received after the first signal string, the second operating frequency is greater than the first operating frequency, and the first signal model is different from the second signal model. If the second signal string includes a second signal pattern, the state controller is used to change the operation state of the connector to an enabled state.

In an exemplary embodiment, the above-mentioned first operating frequency is not greater than half of the second operating frequency.

Based on the above, in the control method proposed by the embodiment of the present invention, in the connector and the memory storage device, the squelch detector is closed because the connector is in the inactive state, and the burst detector detects the burst from the host system. Burst signals, thus reducing the power consumed by the connector.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment.

FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment.

FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment.

FIG. 4 is a circuit block diagram illustrating a connector according to an embodiment.

FIG. 5 is a flowchart illustrating a method for controlling a connector according to an exemplary embodiment.

FIG. 6 is a schematic diagram illustrating a wake-up signal, an alignment signal and a D24.3 characteristic signal according to an exemplary embodiment.

FIG. 7 is a circuit block diagram illustrating a connector according to a second exemplary embodiment.

FIG. 8 is a flow chart illustrating the connector switching between the active state and the partial/sleep state according to the second exemplary embodiment.

FIG. 9 is a circuit block diagram illustrating a connector according to a third exemplary embodiment.

[Description of main component labels]

Detailed ways

[First Exemplary Embodiment]

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1A shows a host system and a memory storage device according to an exemplary embodiment.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is coupled with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into the memory storage device 100 or read from the memory storage device 100 by the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a pen drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

In general, the host system 1000 is any system that can substantially cooperate with the memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is illustrated as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is an SD card 1312, an MMC card 1314, a storage stick (memory stick) 1316, a CF card 1318 or The embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A .

Referring to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also conform to the high-speed peripheral component interconnect express (PCI Express) standard or other suitable standards.

The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000. Fetch and erase operations.

The rewritable non-volatile memory module 106 is coupled to the memory controller 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 304 ( 0 )˜ 304 (R). For example, the physical erase units 304(0)˜304(R) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, and the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. For example, each physical erasing unit is composed of 128 physical programming units. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. The physical programming unit is the smallest unit of programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming unit generally includes a data bit field and a redundant bit field. The data bit area contains multiple physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data bit area of each physical programming unit includes 4 physical access addresses, and the size of one physical access address is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (Multi Level Cell, MLC) NAND flash memory module, that is, at least 2 bits of data can be stored in one memory cell. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 may also be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module, a multi-level storage unit (Trinary Level Cell, TLC) NAND flash memory modules, other flash modules, or other memory modules with the same characteristics.

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment.

Referring to FIG. 3 , the memory controller 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 202 has a plurality of control commands, and when the memory storage device 100 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has driver code, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to store the control code stored in the rewritable non-volatile memory module 106. The instructions are loaded into random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are coupled to the microcontroller. Wherein, the memory management unit is used to manage the physical block of the rewritable non-volatile memory module 106; the memory writing unit is used to issue a write command to the rewritable non-volatile memory module 106 to write data into In the rewritable non-volatile memory module 106; the memory reading unit is used to issue a read instruction to the rewritable non-volatile memory module 106 to read data from the rewritable non-volatile memory module 106; The memory erase unit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase data from the rewritable non-volatile memory module 106; and the data processing unit is used to process the The data of the rewritable nonvolatile memory module 106 and the data read from the rewritable nonvolatile memory module 106 .

The host interface 204 is coupled to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with the PCI Express standard or other suitable data transmission standards.

The memory interface 206 is coupled to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .

In an exemplary embodiment of the present invention, the memory controller 104 further includes a buffer memory 252 , a power management circuit 254 and an error checking and correction circuit 256 .

The buffer memory 252 is coupled to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

The power management circuit 254 is coupled to the memory management circuit 202 and used for controlling the power of the memory storage device 100 .

The error checking and correcting circuit 256 is coupled to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correcting circuit 256 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECC Code), and the memory management circuit 202 will write the data corresponding to the write command and the corresponding error checking and correction code into the rewritable non-volatile memory module 106. Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 256 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

FIG. 4 is a circuit block diagram illustrating a connector according to an embodiment.

Referring to FIG. 4 , the connector 102 includes a burst detector 410 (burst detector), a squelch detector 420 (squelch detector) and a state controller 430 .

The state controller 430 is used to control the operation state of the connector. When the host system 100 is accessing the memory storage device 100 , the operation state of the connector 102 is an active state. On the contrary, if the host system 100 does not want to access the memory storage device 100, the state controller 430 can control the connector 102 to enter a non-activated state. In the inactive state, the connector 102 or the memory controller 104 can turn off part of the circuit, thereby saving power consumption. On the other hand, when the connector 102 is in the inactive state, if the host system 100 sends a wake-up signal to the connector 102, the state controller 430 will change the operating state of the connector 102 to the active state. In other words, the connector 102 can be compatible with any standard that defines a wake-up signal. For example, if the connector 102 is compatible with the SATA standard, the operation state of the connector 102 includes an active state, a partial state and a sleep state. The partial state and the sleep state are also collectively referred to as a non-starting state. It takes a while for the connector 102 to return from the inactive state to the active state. In general, sleep states save more power than partial states, but going from sleep to active takes longer than partial to active.

The squelch detector 420 is used to detect the power level of the signal string 401 . Signal string 401 may include one or more signals. If the power level of the signal string 401 is lower than a predetermined level, the squelch detector 420 will shut down the unused circuits. For example, when the power level of the signal string 401 is lower than the preset level, the squelch detector 420 will send a message to the state controller 430, and the state controller 430 can set the operation state of the connector 102 as non- start state. On the other hand, if the power level of the signal string 401 is higher than the preset level (for example, the signal string 401 includes a wake-up signal), the squelch detector 420 will drive the state controller 430 to change the operation state of the connector 102 to enable state. In an exemplary embodiment, the signal string 401 is an out-of-band signaling (OOB-signaling). The out-of-frequency signal is a data pattern (data pattern), which defines a gap (gap) signal and a burst (burst) signal. The amplitude of the burst signal vibrates up and down at a frequency (for example, 1.5 GHz), while the amplitude of the interval signal remains constant. In other words, the signal string 401 includes one or more interval signals and burst signals. Among the out-of-band signals, the wake-up signal includes at least 6 interval signals and 6 burst signals. The squelch detector 420 detects these interval signals and burst signals, and determines whether the signal string 401 includes the wake-up signal.

The burst detector 410 is used to enable or disable the squelch detector 420 and detect whether the signal string 401 includes a burst signal. In particular, the burst detector 410 operates at a first operating frequency, while the squelch detector 420 operates at a second operating frequency, and the second operating frequency is greater than the first operating frequency. Under the second operating frequency, the squelch detector 420 can completely detect the interval signal and the burst signal. Under the first operating frequency, the burst detector 410 can detect part of the sub-signals in the interval signal and the burst signal. For example, the maximum frequency of interval signals and burst signals transmitted between the connector 102 and the host system 1000 is 1.5 GHz; the second operating frequency is 1.5 GHz; and the first operating frequency is 750 GHz. Therefore, the burst detector 410 can detect sub-signals whose frequency is less than 750 MHz in the interval signal and the burst signal.

FIG. 6 is a schematic diagram illustrating a wake-up signal, an alignment signal and a D24.3 characteristic signal according to an exemplary embodiment.

Referring to FIG. 6, the wake-up signal 510 includes burst signals 511a-511f and interval signals 512a-512f. Each burst signal can be composed of four align signals 520 or four D24.3 characteristic signals 530 . Here, one unit interval represents the length (ie, period) of the sub-signal with the highest frequency in the wake-up signal 510 . For example, the maximum frequency of the wake-up signal 510 is 1.5G Hz, so each unit interval (unit interval) is 1/1.5G second (for example, the unit interval 540). The beginning of the alignment signal 521 includes a sub-signal 521 with a length of 5 unit intervals, followed by a plurality of sub-signals with a length of 1 or 2 unit intervals. However, the D24.3 characteristic signal 530 is entirely composed of sub-signals with a length of 2 unit intervals (for example, the sub-signal 531 ). In this exemplary embodiment, the operating frequency of the squelch detector 420 is 1.5 GHz, so sub-signals of any length can be completely detected; the operating frequency of the burst detector 410 is 750 MHz, and can detect sub-signals with a length greater than or equal to 2 Sub-signals of unit intervals (that is, sub-signals with a frequency less than 750 MHz).

In this exemplary embodiment, when the operating state of the connector 102 is a partial state or a sleep state, the squelch detector 420 is turned off and the burst detector 410 is turned on. It should be noted that since the second operating frequency is lower than the first operating frequency, the burst detector 410 consumes less power than the squelch detector 420 when operating. When the burst detector 410 receives a first signal string 401 , it first determines whether the first signal string includes a burst signal. For example, the burst detector 410 will determine whether the first signal sequence 401 includes sub-signals with a length greater than or equal to n unit intervals, where n is a positive integer greater than or equal to 2. For example, n is a positive integer 2, so the burst detector 410 can detect the sub-signals 521 and 531 . If the first signal string includes sub-signals with a length greater than or equal to n unit intervals, the burst detector 410 determines that the first signal string includes a burst signal and activates the squelch detector 420 .

After the squelch detector 420 is woken up, the squelch detector 420 will continue to receive a second signal string, and determine whether the second signal string is a wake-up signal. The second signal string is a signal transmitted to the connector 102 following the first signal string. For example, the first signal string includes a burst signal 511a, and the second signal string includes burst signals 511b˜511f. In an exemplary embodiment, if the squelch detector 420 determines that the second signal string includes m burst signals, the squelch detector 420 will judge that the second signal string is a wake-up signal, where m is a positive integer (for example, m for 4). In other words, when the burst detector 410 detects the first burst signal 511a, it will activate the squelch detector 420, and the squelch detector 420 will detect the next burst signals 511b-511f. It should be noted that since the wake-up signal 510 includes 6 burst signals 511a-511f and 6 interval signals 512a-512f, and the burst detector 410 has received the burst signal 511a, so in an exemplary embodiment m will be set to less than 6.

If the squelch detector 420 determines that the second signal string is a wake-up signal, the squelch detector 420 will send a message to the state controller 430 . The state controller 430 changes the operation state of the connector 102 to the start state according to the message.

In other exemplary embodiments, the maximum frequency of the interval signal and the burst signal transmitted between the connector 102 and the host system 1000 may also be 3.0G Hz (at this time, a unit interval is 1/3G second) or other values, The present invention is not limited thereto. In an exemplary embodiment, when the maximum frequency of the interval signal and the burst signal is 3.0 GHz, the first operating frequency is 1.5 GHz, and the second operating frequency is 3.0 GHz. However, the first operating frequency and the second operating frequency may also be set to other values, and the present invention is not limited thereto.

In an exemplary embodiment, if the wake-up signal received by the connector 102 is only composed of alignment signals, the burst detector 410 may set n to 5. That is, when the first signal string includes a sub-signal (for example, the sub-signal 521 ) whose length is greater than or equal to 5 unit intervals, the burst detector 410 will determine that the first signal string includes a burst signal. In this way, the operating frequency of the burst detector 410 can be set lower (for example, 300 MHz), thereby further reducing the power consumed by the burst detector 410 during operation. However, in other exemplary embodiments, the burst detector 410 may set n to be 3, 4, or other values, and the invention is not limited thereto.

In an exemplary embodiment, if the burst detector 410 can detect whether the received signal includes a burst signal within the time of one burst signal, the squelch detector 420 can also set m to 5. Alternatively, the squelch detector 420 may also set m to be 3 or other values, and the present invention is not limited thereto.

FIG. 6 is a flowchart illustrating a method for controlling a connector according to an exemplary embodiment.

Please refer to FIG. 6 , in step S602 , when the squelch detector is turned off, the burst detector 410 receives a first signal string. In step S604, the burst detector 410 determines whether the first signal sequence includes a burst signal at the first operating frequency. If the first signal sequence does not include a burst signal, go back to step S602. If the first signal sequence includes a burst signal, in step S606 , the burst detector 410 activates the squelch detector 420 . In step S608 , the squelch detector 420 determines whether the second signal string is a wake-up signal at a second operating frequency, wherein the second operating frequency is greater than the first operating frequency. If the second signal string is a wake-up signal, in step S609 , the state controller 430 changes the operating state of the connector to an active state. However, the steps in FIG. 5 have been described above, and will not be repeated here.

[Second Exemplary Embodiment]

The second embodiment is partially similar to the first embodiment, and only the differences are described here.

FIG. 7 is a circuit block diagram illustrating a connector according to a second exemplary embodiment.

Please refer to FIG. 7 , in the second exemplary embodiment, the burst detector 410 includes a low power squelch detection circuit 411 and a squelch detector control circuit 412 . The squelch detector 420 includes a squelch detection circuit 421 and an out-of-frequency signal judgment circuit 422 . The low power squelch detection circuit 411 is used to detect a burst signal at the first operating frequency. The squelch detector control circuit 412 is used to control (eg, enable or disable) the squelch detection circuit 421 . The squelch detection circuit 421 is used to detect a burst signal in a signal at the second operating frequency, and the out-of-frequency signal judgment circuit 422 is used to judge whether a signal is a wake-up signal.

Specifically, when the connector 102 is in the partial/sleep state, the squelch detection circuit 421 is turned off. When the squelch detection circuit 421 is turned off, the low-power squelch detection circuit 411 receives the signal string 401 and determines whether the signal string 401 includes sub-signals with a length greater than or equal to n unit intervals. If the signal string 401 includes sub-signals with a length greater than or equal to n unit intervals, the squelch detector control circuit 412 activates the squelch detection circuit 421 . The squelch detection circuit 421 continues to receive the second signal string, and detects the burst signal and the interval signal in the second signal string. The out-of-frequency signal judging circuit 422 judges whether the second signal string is a wake-up signal according to the burst signal and the interval signal in the second signal string. For example, if the second signal string includes m burst signals, the out-of-frequency signal judging circuit 422 judges that the second signal string is a wake-up signal. On the other hand, if the out-of-frequency signal judgment circuit 422 judges that the second signal string is not a wake-up signal, the squelch detector control circuit 412 will turn off the squelch detector 421, and only the low-power squelch detection circuit 411 receives the next signal (also is called a third signal), and the low power squelch detection circuit 411 judges whether the third signal includes a burst signal.

FIG. 8 is a flow chart illustrating the connector switching between the active state and the partial/sleep state according to the second exemplary embodiment.

Please refer to FIG. 8 , in step S802 , the connector 102 enters an activated state.

In step S804, the state controller 430 determines whether to enter the partial/sleep state. For example, the state controller 430 may determine whether to enter the partial/sleep state according to the indication of the host system 1000 or the indication of the memory controller 104 . Alternatively, the state controller 430 may also determine whether to enter the partial/sleep state based on its own information (for example, standby time).

To enter the partial/sleep state, in step S806 , the state controller 430 sets the connector 102 to enter the partial/sleep state. At this time, the squelch detector control circuit 412 turns off the squelch detection circuit 421 .

In step S808, the low power squelch detection circuit 411 determines whether a burst signal is detected.

If the low power squelch detection circuit 411 detects a burst signal, in step S810 , the squelch detector control circuit 412 activates the squelch detection circuit 421 .

In step S812, the squelch detector 420 determines whether a wake-up signal is detected. Specifically, the squelch detection circuit 421 detects a burst signal in the second signal string, and the out-of-frequency signal judgment circuit 422 judges whether the second signal string is a wake-up signal.

If the squelch detector 420 determines that the second signal string is a wake-up signal, it will go back to step S802, wherein the state controller 430 will control the connector 102 to enter the start state. If the squelch detector 420 does not detect the wake-up signal, in step S814, the squelch detector control circuit 412 turns off the squelch detection circuit 421, and returns to step S808. However, each step in FIG. 8 has been described in detail above, and will not be repeated here.

[Third Exemplary Embodiment]

FIG. 9 is a circuit block diagram of a connector according to a third exemplary embodiment.

Referring to FIG. 9 , the connector 900 includes a low frequency signal detector 911 , a signal detector control circuit 912 , a high frequency signal detector 921 , a high frequency signal judging circuit 922 and a state controller 930 . Connector 900 is compliant with the serial advanced accessory standard, while signal string 901 is compliant with the definition of an out-of-band signal. The connector 900 can be installed on a host system, hard disk, pen drive, solid state drive, personal computer or server, the invention is not limited thereto.

When the connector 900 is in the partial state and sleep state, the high frequency signal detector 921 is turned off and the low frequency signal detector 911 is turned on. The low-frequency signal detector 911 is used to receive the signal string 901 (also called the first signal string) when the high-frequency signal detector 921 is turned off, and judge whether the first signal string includes a first signal string at the first operating frequency. signal model. For example, the low-frequency signal detector 911 determines whether the first signal sequence has a specific number of burst signals (referred to as the first burst signal), and if so, determines that the first signal sequence includes the first signal model. The first burst signal can be a pulse signal conforming to a specific frequency, for example, the frequency is not greater than 750 MHz. If the first signal string includes the first burst signal, the signal detector control circuit 912 activates the high frequency signal detector 921 . After being activated, the high-frequency signal detector 921 will continue to receive a second signal string, and detect whether a second signal pattern is included in the second signal string at the second operating frequency, wherein the first signal pattern is different from the first signal pattern Two-signal model. The second signal model is, for example, composed of several interval signals and several second burst signals. The second burst signal can be a pulse signal conforming to a specific frequency, and the frequency of the second burst signal can be the same as or different from that of the first burst signal. For example, the high-frequency signal judging circuit 922 judges whether the second signal string is a wake-up signal according to the second burst signal and the interval signal detected by the high-frequency signal detector 921 . For example, the wake-up signal in the out-of-band signal may at least be composed of 6 interval signals and 6 second burst signals. In particular, the first operating frequency is lower than the second operating frequency. For example, the first operating frequency is not greater than half of the second operating frequency, but the invention is not limited thereto. If the second signal string includes a second signal pattern (for example, a wake-up signal), the state controller 930 changes the operation state of the connector 900 to an active state.

To sum up, in the connector control method, the memory storage device and the connector proposed by the embodiments of the present invention, since the burst detector detects the burst signal at the first operating frequency, and when the burst is detected, The squelch detector, which consumes a lot of power, is only activated when the signal is activated, so the power consumption of the connector in the non-activated state can be reduced.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (19)

1. a control method for connector, wherein this connector comprises a squelch detector, it is characterized in that, this control method comprises:

In the pent situation of this squelch detector, receive a first signal string;

Whether comprise a burst at one first operating frequency this first signal string that judges;

If this first signal string comprises this burst, start this squelch detector, and whether be a wake-up signal by this squelch detector at the one second operating frequency secondary signal string that judges, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency; And

If this secondary signal string is this wake-up signal, change mode of operation to starting state of this connector.

2. control method according to claim 1, also comprises:

If this secondary signal string is not this wake-up signal, close this squelch detector, receive one the 3rd signal, and judge whether the 3rd signal comprises this burst.

3. whether control method according to claim 1, wherein comprise that at this first operating frequency this first signal string that judges the step of this burst comprises:

Whether comprise that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, wherein n is more than or equal to 2 positive integer; And

If this first signal string comprises this subsignal, judge that this first signal string comprises this burst.

4. control method according to claim 3, wherein this positive integer n is 5.

5. whether control method according to claim 1 is wherein that the step of this wake-up signal comprises by this squelch detector at this second operating frequency this secondary signal string that judges:

Judge by this squelch detector whether this secondary signal string comprises m burst, and wherein m is positive integer;

If this secondary signal string comprises this m burst, judge that by this squelch detector this secondary signal string is this wake-up signal.

6. a memorizer memory devices, is characterized in that, this memorizer memory devices comprises:

A connector, in order to be coupled to a host computer system;

One duplicative non-volatile memory module, comprises multiple physics unit of erasing; And

One Memory Controller, is coupled to this connector and this duplicative non-volatile memory module,

Wherein this connector comprises:

One state controller;

One squelch detector, is coupled to this state controller; And

One burst detector, is coupled to this squelch detector, in order to receive a first signal string in the pent situation of this squelch detector, and whether comprises a burst at one first operating frequency this first signal string that judges,

Wherein, if this first signal string comprises this burst, this burst detector is in order to start this squelch detector,

After this squelch detector is activated, whether this squelch detector is a wake-up signal in order to the secondary signal string that judges at one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency

If this secondary signal string is this wake-up signal, this state controller is in order to change mode of operation to starting state of this connector.

7. memorizer memory devices according to claim 6, if wherein this secondary signal string is not this wake-up signal, this burst detector, also in order to close this squelch detector, receives one the 3rd signal, and judges whether the 3rd signal comprises this burst.

8. memorizer memory devices according to claim 6, wherein whether this burst detector comprises that at this first operating frequency this first signal string that judges the operation of this burst comprises:

Whether this burst detector comprises that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer;

If this first signal string comprises this subsignal, this squelch detector judges that this first signal string comprises this burst.

9. memorizer memory devices according to claim 8, wherein this positive integer n is 5.

10. memorizer memory devices according to claim 6, wherein judges that in this squelch detector whether this secondary signal string is that the operation of this wake-up signal comprises:

This squelch detector judges whether this secondary signal string comprises m burst, and wherein m is positive integer;

If this secondary signal string comprises m burst, this squelch detector judges that this secondary signal string is this wake-up signal.

11. memorizer memory devices according to claim 6, wherein this burst detector comprises:

One low-power squelch detector; And

One squelch detector control circuit, is coupled to this low-power squelch detector,

This squelch detector comprises;

One squelch detecting circuit, is coupled to this squelch detector control circuit; And

One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,

Wherein, this low-power squelch detector is in order to receive this first signal string in the pent situation of this squelch detecting circuit, and whether comprises this burst at this first operating frequency this first signal string that judges,

If this first signal string comprises this burst, this squelch detector control circuit is in order to start this squelch detecting circuit,

After this squelch detecting circuit is activated, this squelch detecting circuit is in order to detect one second burst and the blank signal in this secondary signal string under this second operating frequency, and this frequency external signal decision circuitry is in order to judge according to this second burst and this blank signal whether this secondary signal string is this wake-up signal.

12. 1 kinds of connectors, is characterized in that, this connector comprises:

One state controller;

One squelch detector, is coupled to this state controller; And

One burst detector, is coupled to this squelch detector, in order to receive a first signal string in the pent situation of this squelch detector, and whether comprises a burst at one first operating frequency this first signal string that judges,

Wherein, if this first signal string comprises this burst, this burst detector starts this squelch detector,

After this squelch detector is activated, whether this squelch detector is a wake-up signal in order to the secondary signal string that judges at one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency

If this secondary signal string is this wake-up signal, this state controller is a starting state in order to change a mode of operation of this connector.

13. connectors according to claim 12, if wherein this secondary signal string is not this wake-up signal, this burst detector, also in order to close this squelch detector, receives one the 3rd signal, and judges whether the 3rd signal comprises this burst.

14. connectors according to claim 12, wherein whether this burst detector comprises that at this first operating frequency this first signal string that judges the operation of this burst comprises:

Whether this burst detector comprises that at this first operating frequency this first signal string that judges length is more than or equal to a subsignal of n unit interval, and wherein n is more than or equal to 2 positive integer;

If this first signal string comprises this subsignal, this squelch detector judges that this first signal string comprises this burst.

15. connectors according to claim 14, wherein this positive integer n is 5.

16. connectors according to claim 12, wherein judge that in this squelch detector whether this secondary signal string is that the operation of this wake-up signal comprises:

This squelch detector judges whether this secondary signal string comprises m burst, and wherein m is positive integer;

If this secondary signal string comprises m burst, this squelch detector judges that this secondary signal string is this wake-up signal.

17. connectors according to claim 12, wherein this burst detector comprises:

One low-power squelch detector; And

One squelch detector control circuit, is coupled to this low-power squelch detector,

This squelch detector comprises:

One squelch detecting circuit, is coupled to this squelch detector control circuit; And

One frequency external signal decision circuitry, is coupled to this squelch detecting circuit and this state controller,

Wherein, this low-power squelch detector is in order to receive this first signal string in the pent situation of this squelch detecting circuit, and whether comprises this burst at this first operating frequency this first signal string that judges,

If this first signal string comprises this burst, this squelch detector control circuit is in order to start this squelch detecting circuit,

After this squelch detecting circuit is activated, this squelch detecting circuit is in order to detect one second burst and the blank signal in this secondary signal string under this second operating frequency, and this frequency external signal decision circuitry is in order to judge according to this second burst and this blank signal whether this secondary signal string is this wake-up signal.

18. 1 kinds of connectors, meet the advanced annex standard of a sequence, it is characterized in that, this connector comprises:

One low frequency signal detecting device;

One signal detector control circuit, is coupled to this low frequency signal detecting device;

One high-frequency detector, is coupled to this signal detector control circuit;

One high-frequency signal decision circuitry, is coupled to this high-frequency detector;

One state controller, is coupled to this signal detector control circuit and this high-frequency signal decision circuitry,

Wherein, this low frequency signal detecting device is in order to receive a first signal string in the pent situation of this high-frequency detector, and whether comprises a first signal model at one first operating frequency this first signal string that judges,

If this first signal string comprises this first signal model, this signal detector control circuit is in order to start this high-frequency detector,

After this high-frequency detector is activated, whether this high-frequency detector comprises a secondary signal model in order to detect a secondary signal string under one second operating frequency, wherein this secondary signal string be received in this first signal string after, and this second operating frequency is greater than this first operating frequency, this first signal model is different from this secondary signal model

If this secondary signal string comprises this secondary signal model, this state controller is a starting state in order to change a mode of operation of this connector.

19. connectors according to claim 18, wherein this first operating frequency is not more than the half of this second operating frequency.

Images