CN103762962B - A kind of Preamplifier-latch comparator of low imbalance - Google Patents

Abstract

The invention discloses a low-offset pre-amplification latch comparator, which includes a basic pre-amplification latch comparator, an offset compensation pair, an offset calibration switch, and an offset calibration control circuit. The basic pre-amplification latch comparator includes a first The first-stage pre-amplifier, the second-stage latch, the offset compensation pair includes an offset adjustment tube, the offset adjustment tube is connected in parallel to the output terminal of the pre-amplifier, and the entire comparison is adjusted by changing the grid voltage of the offset adjustment tube. The offset voltage of the device; the offset calibration control circuit uses a digital bidirectional shifter to store offset information and controls the offset compensation circuit to perform offset calibration. The low offset pre-amplification latch comparator provided by the present invention adds an offset calibration control circuit based on digital storage and control on the basis of the existing pre-amplification latch comparator, which can reduce the offset of the pre-amplification latch comparator Reduced to the original 1/N, the calibrated comparator greatly reduces the offset.

Description

A Low Offset Preamplified Latched Comparator

technical field

The invention relates to a low offset pre-amplification latch comparator, which belongs to the comparator technology.

Background technique

The comparator converts the input analog signal into a digital signal, which is an important interface from analog to digital, and is widely used in circuits such as analog-to-digital converters and digital-to-analog converters. Among them, the pre-amplified latch comparator can amplify the input analog signal, isolate the influence of the output digital on the input signal, and the fast comparison latch of the latch. Compared with the amplifier-type comparator with high precision and slow speed, it can be very good Take advantage of the speed of the latch comparator and improve the accuracy to a certain extent. Therefore, the pre-amplified latch comparator is widely used in practical engineering practice. However, with the rapid development of digital circuits, the speed and precision requirements of analog-to-digital converters and digital-to-analog converters continue to increase. It is difficult to meet the high-precision requirements using traditional pre-amplified latch comparators. The offset calibration of the memory comparator plays an important role in high-speed and high-precision applications.

The traditional offset calibration technique is to use a capacitor to store the offset when the comparator is working, and then perform offset calibration on the pre-amplifier. This approach limits the speed of the comparator and only calibrates the offset of the preamplifier, not the latch.

Contents of the invention

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a low offset pre-amplified latch comparator to improve the accuracy of the comparator.

Technical scheme: in order to achieve the above object, the technical scheme adopted in the present invention is:

A low-offset pre-amplification latch comparator, including a basic pre-amplification latch comparator, an offset compensation pair, an offset calibration switch, and an offset calibration control circuit, the basic pre-amplification latch comparator includes a first-stage pre-amplification The amplifier and the latch of the second stage, the offset compensation pair includes an offset adjustment tube, and the offset adjustment tube is connected in parallel to the output terminal of the pre-amplifier as the carrier of the offset compensation of the comparator. By changing the differential gate of the offset adjustment tube voltage to compensate the offset voltage of the comparator; the offset calibration switch is used as an enable switch for whether the offset calibration control circuit performs an offset calibration operation; the offset calibration control circuit uses a bidirectional shift register for storing offset information and adjusting offset adjustment The gate voltage of the tube is used to compensate the offset of the comparator. The offset calibration control circuit uses active devices, which can ensure that the bias voltage V _{cal_L} /V _{cal_R} of the tube after calibration remains unchanged, avoiding the leakage current of the MOS in the circuit when the capacitor is used as a device for storing offsets. Case.

The offset calibration control circuit includes an offset compensation pair tube bias circuit, a bias adjustment circuit, a bias adjustment gating switch and a bias adjustment control module; the offset compensation pair tube bias circuit is used to convert the current generated by the current source It is converted into a bias voltage; the bias adjustment circuit is used to generate an adjustment current, and the grid voltage of the offset compensation pair tube is adjusted through the offset compensation bias circuit; the bias adjustment gate switch is used to adjust the bias adjustment circuit The generated adjustment current source is gated to offset compensation to bias the tube bias circuit; the bias adjustment control module is mainly composed of a bidirectional shift register, and controls the current source switch of the bias adjustment circuit.

The bias circuit for offset compensation is mainly composed of the twenty-first PMOS transistor M20, the twenty-first PMOS transistor M21, the twenty-second PMOS transistor M22, the twenty-fifth NMOS transistor M25, and the twenty-sixth NMOS transistor M26; The 20th PMOS transistor M20, the 21st PMOS transistor M21 and the 22nd PMOS transistor M22 form a current mirror; the 25th NMOS transistor M25 and the 26th NMOS transistor M26 are connected in a diode form as a MOS transistor resistor, The current I _r1 mirrored by the current source is superimposed on the compensation current I _CL /I _CR generated by the offset adjustment circuit to convert it into the offset compensation pair tube bias voltage V _{cal_L} /V _{cal_R} .

The bias adjustment circuit includes a group of parallel adjustment current sources, and each adjustment current source is connected in series with a current source switch; each adjustment current source is a PMOS transistor, and each current source switch is a PMOS transistor; the second The ten PMOS transistors M20 and the adjustment current source form a current mirror. The offset calibration method adopted by the present invention can reduce the offset voltage to 1/N before calibration, where N is the number of adjusted current sources. The number of adjustment current sources depends on the accuracy to be achieved. Increasing the number of adjustment current sources can improve the accuracy of offset calibration, and correspondingly reducing the number of adjustment current sources will reduce the effect of offset calibration; the state of the current source switch determines Whether the adjustment current source connected in series is effective. All PMOS transistors used as adjustment current sources are designed to have weights, and the weights are reflected in the width-to-length ratio of the PMOS transistors; adding weights can make the comparator offset voltage adjusted at each step the same, that is, the input offset voltage adjustment step size is the same.

The bias adjustment gating switch includes a gating switch control circuit and a gating switch main body; the gating switch control circuit includes a first SR flip-flop SR1, a second RS flip-flop SR2, a first inverter N1, a second Fifty-first NMOS transistor M51 and fifty-second NMOS transistor M52, the first SR flip-flop SR1 is composed of a first NOR gate NOR1 and a second NOR gate NOR2, and the second RS flip-flop SR2 is composed of a third NOR gate NOR3 and the fourth NOR gate NOR4; the main body of the strobe switch includes a data selector for choosing one of two, and the data selector is mainly composed of the fifty-third NMOS transistor M53 and the fifty-fifth NMOS transistor M55. The fifty-fourth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 are connected in series in the selector, and the fifty-fourth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 serve as a reset terminal of the data selector.

The bias adjustment control module is mainly composed of a bidirectional shift register and its control circuit. The number of the bidirectional shift register is equal to the number of current source switches in the bias adjustment circuit, indicating the accuracy of offset correction (assuming N bidirectional shift registers The calibrated offset of the comparator of the bit register is a, and the calibrated offset of the comparator with only one bidirectional shift register is b, a=1b/N), each bidirectional shift register controls a current source switch, and the bidirectional shift register The output signal of the bit register is connected to the gate of the current source switch; the bidirectional shift register is mainly triggered by a two-to-one data selector (which can be designed to have the same structure as the data selector in the bias adjustment strobe switch) and an edge D The first transmission gate TG1 and the second transmission gate TG2 are controlled by the bias adjustment output CONT of the strobe switch to select OP3 or ON3 as the selection signal of the two-to-one data selector. General design: the positive terminal (terminal 1) of the data selector at the lowest bit of the bidirectional shift register is connected to the closing level of the current source switch. Since the PMOS switch is used, the closing level is low; the data selection of the lowest bit of the bidirectional shift register The negative terminal (0 terminal) of the device is connected to the disconnection level of the current source switch, that is, the high level.

Beneficial effects: the low offset pre-amplification latch comparator provided by the present invention adds an offset calibration control circuit based on digital storage and control on the basis of the existing pre-amplification latch comparator, and can compare the pre-amplification latch The offset of the comparator is reduced to the original 1/N, and N is the number of bits of the shift register; the calibrated comparator greatly reduces the offset, and can flexibly adjust the number of calibration bits N according to the application; different from The traditional offset calibration control circuit, the present invention does not affect the speed of the comparator after adding the offset calibration control circuit, after the comparator calibration is completed, the adjustment control module composed of digital circuits does not generate static power consumption; the present invention The adjustment belongs to the reset type adjustment. When the comparator is working normally, the offset calibration control circuit maintains the state after offset calibration. Therefore, the present invention can also be compatible with the technology of offset calibration in the working process of the comparator, thereby further improving the accuracy of the comparator. .

Description of drawings

Fig. 1 is a kind of pre-amplification latch comparator offset calibration circuit topological structure diagram based on the present invention;

FIG. 2 is a topological structure diagram of a bias adjustment circuit based on the present invention;

Fig. 3 is a topological structure diagram of a bias adjustment gating switch based on the present invention;

Fig. 4 is a topological structure diagram of a bias adjustment control module based on the present invention;

FIG. 5 is an equivalent schematic diagram of comparator offset voltage;

Fig. 6 is a voltage waveform diagram of key nodes of the offset calibration circuit of the pre-amplified latch comparator.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 1, it is a low-offset pre-amplification latch comparator, including a basic pre-amplification latch comparator 1, an offset compensation pair tube 2, an offset calibration switch 3, and an offset calibration control circuit 4. The basic pre-amplification The latch comparator 1 includes a first-stage pre-amplifier and a second-stage latch, and the offset compensation pair tube 2 includes an offset adjustment tube, which is connected in parallel to the output terminal of the pre-amplifier as a comparator offset The compensation carrier adjusts the offset voltage of the comparator by changing the grid voltage of the offset adjustment tube; the offset calibration switch 3 is used as an enable switch for whether the offset calibration control circuit 4 performs offset calibration operations; the offset calibration control circuit 4 adopts The bidirectional shift register is used to store offset information and adjust the gate voltage of the offset adjustment transistor to compensate the offset of the comparator.

As shown in FIG. 1 , the basic pre-amplification latch comparator 1 belongs to an existing circuit, including a first-stage pre-amplifier, a second-stage latch and an inverter.

The pre-amplifier is mainly composed of a first NMOS transistor M1, a second NMOS transistor M2, a sixth NMOS transistor M6, and a seventh PMOS transistor MOS7 to a tenth PMOS transistor M10; wherein, the first NMOS transistor M1 and the second NMOS transistor M2 is the input pair tube of the pre-amplifier, the sixth NMOS tube M6 is the tail current of the pre-amplifier, the seventh PMOS tube M7 to the tenth PMOS tube M10 constitute the load of the pre-amplifier; the input pair tube of the pre-amplifier is also used as the basic pre-amplifier lock The differential input terminal of the comparator 1 is stored, the input signal of the first NMOS transistor M1 is IP1, the input signal of the second NMOS transistor M2 is IN1, and the output signals of the pre-amplifier are OP1 and ON1.

The latch is mainly composed of the eleventh NMOS transistor M11 to the fourteenth NMOS transistor M14, the fifteenth PMOS transistor M15 to the eighteenth PMOS transistor M18, and the nineteenth NMOS transistor M19; wherein, the eleventh NMOS The transistor M11 and the twelfth NMOS transistor M12 are the input terminals of the latch, the gate input signal of the eleventh NMOS transistor M11 is OP1, the gate input signal of the twelfth NMOS transistor M12 is ON1; the thirteenth NMOS transistor M12 M13, the fourteenth NMOS transistor M14, the fifteenth PMOS transistor M15 and the sixteenth PMOS transistor M16 form the positive feedback of the latch; the latch passes through the seventeenth PMOS transistor M17, the eighteenth PMOS transistor M18 and the tenth Nine NMOS transistors M19 are connected to the clock signal to realize reset; the output signals of the latch are OP2 and ON2.

The output signals OP2 and ON2 of said latch form the output signals OP3, ON3 of the large latch comparator 1 through the inverter. The drive capability of the output can be enhanced through the inverter, and the output signal can be converted into an output format whose reset level is 0.

As shown in FIG. 1, the offset compensation pair transistor 2 includes a third NMOS transistor M3, a fourth NMOS transistor M4, and a fifth NMOS transistor M5, and the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected in parallel at the output end of the preamplifier. , the input signal of the third NMOS transistor M3 is OP1, the input signal of the fourth NMOS transistor M4 is ON1; the fifth NMOS transistor M5 serves as the tail current of the third NMOS transistor M3 and the fourth NMOS transistor M4, and controls the flow through the third NMOS transistor M4 The total current of the tube M3 and the fourth NMOS tube M4, avoiding the normal operation of the pre-amplifier due to the excessive common mode level of the third NMOS tube M3 and the fourth NMOS tube M4 entering the deep linear region; the third NMOS tube M3 The gate is connected to the output signal V _{cal_L} of the calibration control circuit 4 , and the gate of the fourth NMOS transistor M4 is connected to the output signal V _{cal_R} of the calibration control circuit 4 .

As shown in FIG. 1 , the offset calibration switch 3 is mainly composed of a first AND gate AND1 and a second AND gate AND2. The input signal of the first AND gate AND1 is OP3, the offset calibration enable signal EN, and the output signal is OP4. The input signal of the second AND gate AND2 is ON3, the offset calibration enable signal EN, and the output signal is ON4. The function of the offset calibration switch 3 is to add an enable signal on the basis of the output result of the basic pre-amplification latch comparator 1: if the input EN is high level, the output signals OP4 and ON4 are the same as the input OP3 and ON3 respectively, and the offset calibration The control circuit 4 works; if the input EN is at low level, the output signals OP4 and ON4 are always at low level, and the offset calibration control circuit 4 does not work, and keeps the last adjusted state unchanged.

The offset calibration control circuit 4 includes an offset compensation pair tube bias circuit 4.1, a bias adjustment circuit 4.2, a bias adjustment gate switch 4.3, and a bias adjustment control module 4.4; the offset compensation pair tube bias circuit 4.1 is used for The current generated by the current source is converted into a bias voltage; the bias adjustment circuit 4.2 is used to generate an adjustment current, and the grid voltage of the offset compensation pair tube 2 is adjusted through the offset compensation pair bias circuit 4.1; the bias adjustment option The pass switch 4.3 is used to gate the adjustment current source generated by the bias adjustment circuit 4.2 to the offset compensation to bias the tube bias circuit 4.1; the bias adjustment control module 4.4 is mainly composed of a bidirectional shift register, and the bias Adjust the current source switch of circuit 4.2 for control.

As shown in FIG. 1, the offset compensation pair transistor bias circuit 4.1 is mainly composed of the 20th PMOS transistor M20, the 21st PMOS transistor M21, the 22nd PMOS transistor M22, the 23rd PMOS transistor M23, the second The fourteenth PMOS transistor M2, the twenty-fifth NMOS transistor M26, and the twenty-sixth NMOS transistor M26 are formed; the twenty-first PMOS transistor M20, the twenty-first PMOS transistor M21, and the twenty-second PMOS transistor M22 constitute a current mirror; The turned-on twenty-third PMOS transistor M23 and the twenty-fourth PMOS transistor M24 are used to adjust the structure of the offset compensation pair tube bias circuit 4.1, so that the structures of the offset compensation pair tube bias circuit 4.1 and the bias adjustment circuit 4.2 are consistent; The twenty-fifth NMOS transistor M25 and the twenty-sixth NMOS transistor M26 are connected in the form of a diode as a MOS transistor resistor, and the current I _r1 mirrored by the current source is superimposed on the compensation current I _CL /I _CR generated by the offset adjustment circuit 4.2 Converted to the bias voltage V _{cal_L} /V _{cal_R} of the offset compensation pair tube 2;

As shown in FIG. 2, the bias adjustment circuit 4.2 includes a thirty-first PMOS transistor M31 to a thirty-eighth PMOS transistor M38, a forty-first PMOS transistor M41 to a forty-eighth PMOS transistor M48, and the fourth The eleventh PMOS transistor M41 to the forty-eighth PMOS transistor M48 are respectively connected in series with the thirty-first PMOS transistor M31 to the thirty-eighth PMOS transistor M38, and the twentieth PMOS transistor M20 is connected to the thirty-first PMOS transistor M31 to The thirty-eighth PMOS transistor M38 constitutes a current mirror; the thirty-first PMOS transistor M31 to the thirty-eighth PMOS transistor M38 act as eight adjustment current sources to generate adjustment currents I1 to I8; the forty-first PMOS transistors M41 to the forty-eighth Eight PMOS transistors M48 are used as current source switches to control whether the current I1~I8 of the current mirror is effective, and the control bias current is connected to the offset compensation pair tube bias circuit 4.1; by adjusting the weight of the current source I1~I8, it can be connected one by one The offsets adjusted by the adjustment current sources I1˜I8 are the same, that is, the sizes of the thirty-first PMOS transistors M31 to the thirty-eighth PMOS transistors M38 are adjusted so that the adjustment steps of the input offset voltages are the same.

The existence of the bias adjustment strobe switch 4.3 is due to the use of only one group of adjustment current sources, and the bias that needs to be adjusted must be gated; as shown in Figure 3, the bias adjustment strobe switch 4.3 includes a strobe switch control circuit and the gate switch main body; the gate switch control circuit includes a first SR flip-flop SR1, a second RS flip-flop SR2, a first inverter N1, a fifty-first NMOS transistor M51 and a fifty-second NMOS transistor M52 , the first SR flip-flop SR1 is composed of the first NOR gate NOR1 and the second NOR gate NOR2, the second RS flip-flop SR2 is composed of the third NOR gate NOR3 and the fourth NOR gate NOR4, the first inverter N1, the fifty-first NMOS transistor M51 and the fifty-second NMOS transistor M52 are connected between the first SR flip-flop SR1 and the second SR flip-flop SR2; the main body of the strobe switch includes a two-to-one data selector, The data selector is mainly composed of the fifty-third NMOS transistor M53 and the fifty-fifth NMOS transistor M55, the fifty-fourth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 are connected in series in the data selector, and the fifth The fourteenth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 are used as the reset terminal of the data selector; since the control signal of the strobe switch is formed by the SR flip-flop, once the reset is completed, the bias adjustment strobe switch 4.3 will remain The strobe state until the next reset signal comes.

As shown in Figure 4, the bias adjustment control module 4.4 is mainly composed of bidirectional shift registers, and the number of the bidirectional shift registers is equal to the number of current source switches in the bias adjustment circuit 4.2, that is, equal to the number of bias adjustment The number of tail currents in circuit 4.2 is equal, indicating the accuracy of offset calibration; the output signals of the eight bidirectional shift registers are respectively Q1 to Q8, and the Q1 to Q8 are respectively connected to the forty-first PMOS transistor M41 to the forty-eighth PMOS The gate input of tube M48 is the current source switch that controls the bias adjustment circuit 4.2; the bidirectional shift register is mainly composed of a two-to-one data selector and an edge D flip-flop, and adjusts the output of the strobe switch 4.3 through the bias CONT controls the first transmission gate TG1 and the second transmission gate TG2 to select OP3 or ON3 as the control signal of the two-to-one data selector; the first data selector MUX1 to the eighth data selector MUX8 respectively correspond to the forty-first PMOS transistor M41 to the forty-eighth PMOS transistor M48. The chosen signal is used to control the bidirectional shift register to shift from low to high or from high to low: the positive input terminal of the lowest bit of the bidirectional shift register is fixed at the closed potential of the current source switch, that is, in Figure 4 The positive terminal (terminal 1) of the first data selector MUX1 is connected to a low level, which corresponds to the closing of the forty-first PMOS transistor M41 in Figure 2; the highest negative input terminal of the bidirectional shift register is fixed at the disconnection potential of the current source switch , that is, the negative terminal (0 terminal) of the eighth data selector MUX8 in Figure 4 is connected to a high level, corresponding to the forty-eighth PMOS transistor M48 in Figure 2 being disconnected; therefore, when the clock signal jumps from a low level is high level, if the bidirectional shift register shifts from low to high, the bias adjustment circuit 4.2 connects one more adjustment current source to the bias; if the bidirectional shift register shifts from high to low, the bias The adjustment circuit 4.2 will disconnect the closed current highest position adjustment current source switch, that is, the bias adjustment circuit 4.2 will reduce one adjustment circuit. OP4 and ON4 are used as the clock signal ck of the first D flip-flop DF1 to the eighth D flip-flop DF8 through the NOR gate.

As shown in Figure 5, at the beginning of offset calibration, the input enable signal EN and reset signal RST are both at high level, and the differential input signals IP and IN of the basic pre-amplification latch comparator 1 are connected to the basic The input common-mode level V _COM of the pre-amplified latch comparator 1 is equivalent to the offset voltage of the basic pre-amplified latch comparator 1 to the input terminal, expressed as an input offset voltage V _os , as shown in FIG. 5 .

Assuming that V _os is positive (the operation of the comparator calibration circuit when V _os is negative is similar to the case where V _os is positive, and will not be repeated), when the clock signal CLK is low, the basic preamplifier latches comparator 1 Reset, the output signals OP2 and ON2 are pulled to high level by the seventeenth PMOS tube M17 and the eighteenth PMOS tube M18, and the output signal is low level OP3 and ON3 after passing through the inverter, and the bias adjustment strobe switch 4.3 Disconnect from biases V _{cal_L} , V _{cal_R} and reset to supply voltage. When the clock signal CLK is high level, the offset voltage passes through the basic pre-amplification latch comparator 1, and the output result is: OP2 is high level, ON2 is low level; after passing through the inverter, the output signal is: OP3 is low level, ON3 is high level; since the enable signal EN is high level, the values of OP4 and ON4 are the same as OP3 and ON3 respectively; at this time, the reset signal is still high, and the first data selector MUX1 to the eighth The output of the data selector MUX8 is a reset output, that is, high level; the input terminals of the first D flip-flop DF1 to the eighth D flip-flop DF8 are all reset high level; the clock of the D flip-flop is passed through the fifth by ON4 and OP4 The NOR gate NOR5 is formed; therefore, after the high level of CLK ends, the first D flip-flop DF1 to the eighth D flip-flop DF8 are all reset, so that the forty-first PMOS transistor M41 to the forty-eighth PMOS transistor M48 are all turned off ; At this time, the adjustment circuit has completed the reset of the digital circuit part; when the reset input RST remains high, the circuit remains in the reset state.

When the reset signal RST transitions from high level to low level, and the enable signal EN remains high level. Until the next CLK clock transition from low to high, the comparator output keeps OP3 low and ON3 high. After the offset calibration switch 3, the values of OP4 and ON4 are the same as those of OP3 and ON3 respectively. In the bias adjustment strobe switch 4.3, since OP4 is at low level and ON4 is at high level, after the reset signal RST jumps to low level, the strobe control signal CONT is maintained at low level, and the corresponding second selection A data selector gates the V _JO- terminal, which is connected to the bias circuit corresponding to the gate voltage V _{cal_R} of the fourth NMOS transistor M4 . After selection, the bias adjustment selection switch 4.3 will maintain this selection state until the next reset signal RST is at high level.

When the CLK clock jumps from low level to high level, since the calibration has not been performed, the output of the basic prevention large latch comparator is still OP3 low level and ON3 high level. Therefore, OP4 and ON4 are low level and high level respectively. The data selector control terminal chosen of the bias adjustment control module 4.4 is at a high level through the first transmission gate TG1 and the second transmission gate TG2. The data selector in the bidirectional shift register selects the signal at terminal 1 and thus jumps on the rising edge of the clock ck of the shift register, and the bidirectional shift register shifts forward by one bit, that is, the first bidirectional shift register DF1 to the eighth bidirectional shift register The bit register DF8 shifts one bit from the status to the high level. Since the 1 input terminal of the data selector MUX1 is connected to low level, the output Q1 of the first register DF1 jumps to low level, while Q7~Q8 remain high level . Therefore, the forty-first PMOS transistor M41 of the switch controlled by Q1 is turned on, and the current flowing into the twenty-sixth NMOS transistor M26 is the current of the twenty-second PMOS transistor M22 plus the current of the thirty-first PMOS transistor M31. The voltage of V _{cal_R} is increased by multiplying the current of the thirty-first PMOS transistor M31 by the resistance of the twenty-sixth NMOS transistor M26 .

Thereafter, the clock CLK jumps from low level to high level, and the output of the basic pre-amplification latch comparator 1 may appear in two situations. The first case is OP3 low level, ON3 high level; the second case is OP3 high level, ON3 low level.

In the first case, assuming that the output of the bidirectional shift register Q1 to Qk-1 in the previous state is low level (k is between 1 and 8, when Q0 appears, all Q1 to Q8 are low level), then The bidirectional shift register of the bias adjustment control module 4.4 will shift again from low to high by one bit, and the lowest bit in the output high level of the bidirectional shift register will jump to low level, that is, Qk will jump to low level, and other The output of the bidirectional shift register maintains the previous state. At this time, Q1 to Qk are at low level, and Qk+1 to Q8 are at high level (when Q9 appears, all Q1 to Q8 are at high level). The PMOS (M40+k) of the fortieth plus k of the adjustment current source switch controlled by Qk is turned on, and the current flowing into the twenty-sixth NMOS transistor M26 is the current of the twenty-second PMOS transistor M22 plus the thirty-first The current of the PMOS transistor (M30+k) from the PMOS transistor M31 to the thirtieth plus k. Compared with the previous state, the voltage of V _{cal_R} is increased by the current of the thirtieth plus kPMOS transistor (M30+k) multiplied by the resistance of the twenty-sixth NMOS transistor M26.

In the second case, assuming that the bidirectional shift register outputs Q1 to Qk in the previous state are low level, then the bidirectional shift register of the bias adjustment control module 4.4 will shift one bit from high bit to low bit, and the bidirectional shift register The highest bit in the output low level jumps to high level, that is, Qk jumps to high level, and the output of other shift registers maintains the previous state. At this time, Q1 to Qk-1 (when Q0 appears, all Q1 ~Q8 are all high level) are low level, Qk to Q8 are high level. The PMOS (M40+k) of the fortieth plus k of the adjustment current source switch controlled by Qk ends, and the current flowing into the twenty-sixth NMOS transistor M26 is the current of the twenty-second PMOS transistor M22 plus the thirty-first PMOS The current of the PMOS transistor (M30+k-1) of k-1 is added from the tube M31 to the thirtieth. Therefore, compared to the previous state, the voltage of V _{cal_R} is reduced by the current of the thirtieth plus k PMOS transistor (M30+k) multiplied by the resistance of the twenty-sixth NMOS transistor M26.

When the input enable signal EN transitions to a low level, the offset calibration of the basic pre-amplification latch comparator 1 ends, and the offset calibration control circuit 4 will maintain the adjustment state when the enable terminal transitions to a low level, and the basic pre-amplification Amplifying Latch Comparator 1 begins normal operation.

FIG. 6 is a graph showing the variation curve of the voltage of each key node with time in the present invention. During the adjustment process, the input terminals IP1 and IN1 of the comparator are connected to the input common-mode voltage V _COM of the basic pre-amplification latch comparator 1 . It can be seen from the curve that the output signals OP3 and ON3 of the basic pre-amplification latch comparator 1 are maintained at a low level before calibration, respectively, and are at a high level until the comparator output OP3 and ON3 are interleaved and output at a high level after the calibration is completed. The offset of the basic pre-amplified latch comparator 1 is calibrated by offset compensation to the relative value change of the gate voltage (V _{cal_L} , V _{cal_R} ) of the transistor 2 .

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also possible. It should be regarded as the protection scope of the present invention.

Claims (6)

1. A low-offset pre-amplification latch comparator, comprising a basic pre-amplification latch comparator (1), an offset compensation pair tube (2), an offset calibration switch (3) and an offset calibration control circuit (4). The basic pre-amplification latch comparator (1) includes a first-stage pre-amplifier and a second-stage latch, and is characterized in that: the offset compensation pair tube (2) includes an offset adjustment tube, and the offset adjustment tube connected in parallel to the output terminal of the pre-amplifier, as a carrier for comparator offset compensation, the offset voltage of the comparator is compensated by changing the differential grid voltage of the offset adjustment tube; whether the offset calibration switch (3) is used as an offset calibration control circuit (4) An enabling switch for performing offset calibration operations; the offset calibration control circuit (4) adopts a bidirectional shift register for storing offset information and adjusting the gate voltage of the offset adjustment tube to compensate the offset of the comparator. 2. The low offset preamplified latch comparator according to claim 1, characterized in that: the offset calibration control circuit (4) comprises an offset compensation pair tube bias circuit (4.1), a bias adjustment circuit (4.2 ), a bias adjustment gating switch (4.3) and a bias adjustment control module (4.4); the offset compensation pair tube bias circuit (4.1) is used to convert the current generated by the current source into a bias voltage; the bias The adjustment circuit (4.2) is used to generate the adjustment current, and the offset compensation pair tube bias circuit (4.1) is used to adjust the grid voltage of the offset compensation pair tube (2); the bias adjustment gate switch (4.3) is used to set the bias The adjustment current source generated by the adjustment circuit (4.2) is gated to offset compensation to bias the tube bias circuit (4.1); the bias adjustment control module (4.4) is mainly composed of a bidirectional shift register, and adjusts the bias The current source switch of the circuit (4.2) is controlled. 3. The low offset pre-amplification latch comparator according to claim 2, characterized in that: the offset compensation pair tube bias circuit (4.1) is mainly composed of the twentieth PMOS transistor M20, the twenty-first PMOS transistor Composed of M21, twenty-second PMOS transistor M22, twenty-fifth NMOS transistor M25, and twenty-sixth NMOS transistor M26; twentieth PMOS transistor M20, twenty-first PMOS transistor M21, and twenty-second PMOS transistor M22 Current mirror; the twenty-fifth NMOS tube M25 and the twenty-sixth NMOS tube M26 are connected in a diode form as a MOS tube resistor, and the current I _r1 mirrored by the current source is superimposed on the compensation generated by the bias adjustment circuit (4.2) The current I _CL /I _CR is converted into a bias voltage V _{cal_L} /V _{cal_R} of the offset compensation pair (2). 4. The low offset preamplified latch comparator according to claim 3, characterized in that: the bias adjustment circuit (4.2) includes a group of parallel adjustment current sources, and each adjustment current source is connected in series with a current source switch; each adjustment current source is a PMOS transistor, and each current source switch is a PMOS transistor; the twentieth PMOS transistor M20 and the adjustment current source form a current mirror. 5. The low offset preamplified latch comparator according to claim 4, characterized in that: the bias adjustment gating switch (4.3) comprises a gating switch control circuit and a gating switch main body; the gating switch The switch control circuit includes a first SR flip-flop SR1, a second SR flip-flop SR2, a first inverter N1, a fifty-first NMOS transistor M51, and a fifty-second NMOS transistor M52. The first SR flip-flop SR1 is composed of a first The NOR gate NOR1 and the second NOR gate NOR2 are composed, and the second SR flip-flop SR2 is composed of the third NOR gate NOR3 and the fourth NOR gate NOR4; the main body of the gate switch includes a two-to-one data selector, The data selector is mainly composed of the fifty-third NMOS transistor M53 and the fifty-fifth NMOS transistor M55, the fifty-fourth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 are connected in series in the data selector, and the fifth The fourteenth NMOS transistor M54 and the fifty-sixth NMOS transistor M56 serve as reset terminals of the data selector. 6. The low offset preamplified latch comparator according to claim 5, characterized in that: in the bias adjustment control module (4.4), the number of bidirectional shift registers is the same as that in the bias adjustment circuit (4.2) The number of current source switches is equal, and each bidirectional shift register controls a current source switch, and the output signal of the bidirectional shift register is connected to the gate of the current source switch; the bidirectional shift register is mainly composed of two data selectors It is constituted with an edge D flip-flop, and the first transmission gate TG1 and the second transmission gate TG2 controlled by the output control of the bias adjustment strobe switch (4.3) CONT strobe the control signal of the one-of-two data selector.