CN103745973B - ESD protection device and ESD circuit suitable for battery management chip - Google Patents

Abstract

The invention relates to the technical field of ESD, and discloses an ESD protection device and an ESD circuit suitable for a battery management chip. Among them, the ESD protection device includes: substrate, buried layer, high-voltage N-well region, high-voltage P-well region, low-voltage P-well region and low-voltage NMOS transistor; the buried layer is on the substrate; the high-voltage P-well region is on the buried layer The low-voltage P well region is on the high-voltage P well region; the low-voltage NMOS transistor is in the low-voltage P well region; the high-voltage N well region is outside the high-voltage P well region and is in contact with the buried layer; the gate and source of the low-voltage NMOS transistor connected, and connected to the high-voltage P well region as the positive electrode of the protection device; the drain of the low-voltage NMOS transistor is connected to the high-voltage N well region as the negative electrode of the protection device. Both ends of the ESD protection device in the present invention can be connected to a high level, and the ESD protection devices in the ESD circuit are connected to the two ends of the battery in one-to-one correspondence, realizing the ESD protection of the battery management chip.

Description

An ESD protection device and an ESD circuit suitable for battery management chips

technical field

The invention relates to the technical field of ESD, and is mainly applicable to ESD protection devices and ESD circuits applicable to battery management chips.

Background technique

Electrostatic Discharge (Electrostatic Discharge, ESD) is one of the important factors causing chip damage. The generation of electrostatic discharge is mostly caused by human factors, but it is difficult to avoid. During the process of chip manufacturing, production, testing, storage and handling, static electricity will accumulate in the human body, instruments and storage equipment, and even the chip itself will accumulate static electricity. And people, without knowing it, make these objects touch each other, forming a discharge path, causing the chip to suffer from excessive electrical stress

(Electrical Overstress, EOS) and damaged. In order to prevent the chip from being damaged by electrostatic discharge, an ESD circuit must be added in the chip to provide a low-resistance path for the discharge of electrostatic charges.

The design of the ESD circuit needs to consider many factors. The basic requirement is to provide an effective charge discharge path without affecting the normal operation of the circuit. In addition, factors such as the area of the circuit, whether it is necessary to increase the process mask layer, the delay of the speed-sensitive pins, and latchup must also be considered.

Referring to FIG. 1 , the input pin (Inputpad) of the existing analog signal pin ESD circuit includes ESDpmos1, ESDnmos1 and a resistor R whose gate is connected to the source. The output pins (Outputpad) include ESDpmos2 and ESDnmos2 whose gate is connected to the source. The Powerclamp circuit connected between VDDrail and GNDrail will conduct a large amount of current when ESD occurs, and maintain the voltage between VDDrail and GNDrail within the maximum voltage value that the device can withstand. If electrostatic discharge occurs between the Inputpad and the Outputpad, the discharge path of the current is shown in the direction of the arrow in Figure 1, the Inputpad flows into the current, and the parasitic diode of ESDpmos1 conducts forward, showing low resistance characteristics. R usually uses a 1K resistor, so the current does not flow into the internal circuit, the current flows into the Powerclamp circuit along the VDDrail, and finally flows out of the Outputpad through the parasitic diode of ESDnmos2.

A battery management chip usually needs to manage multiple batteries. The connection between the chip pins and the battery is shown in Figure 2. The highest voltage of the battery in series is used as the power supply VH of the chip, and the lowest voltage of the battery in series is used as the ground of the chip. Since the voltage of each battery is to be detected, the positive and negative poles of each battery are connected to the pins of the chip. Calculated according to the 3V voltage drop of a battery, taking pin Ch2 as an example, if there are 6 batteries under the Ch2 pin, the voltage is 18V, and the voltage of the adjacent pin downward is 15V, and due to the existing high voltage An ESD device usually has one pin that can withstand high voltage; the other pin is grounded and cannot withstand high voltage. Therefore, it is necessary to design an ESD protection device that can withstand high voltage at both ends. In addition, when electrostatic discharge occurs, the voltage difference between any two adjacent battery pins cannot exceed the voltage that the internal circuits and devices of the chip can withstand.

To sum up, it is necessary to design an ESD structure suitable for battery management chips.

Contents of the invention

The technical problem to be solved by the present invention is to provide an ESD protection device and an ESD circuit suitable for a battery management chip, which can perform ESD protection on the battery management chip.

In order to solve the problems of the technologies described above, the present invention provides a kind of ESD protection device, comprising: substrate, buried layer, high-voltage N well region, high-voltage P well region, low-voltage P well region and low-voltage NMOS tube; On the substrate; the high-voltage P-well region is on the buried layer; the low-voltage P-well region is on the high-voltage P-well region; the low-voltage NMOS transistor is in the low-voltage P-well region; The high-voltage N-well region is outside the high-voltage P-well region and is in contact with the buried layer; the gate of the low-voltage NMOS transistor is connected to the source and connected to the high-voltage P-well region as a protection device The anode of the low voltage NMOS transistor is connected to the high voltage N well region as the negative electrode of the protection device.

The present invention also provides an ESD circuit suitable for battery management chips, comprising: at least one ESD protection device as claimed in claim 1; the positive poles of the ESD protection devices are respectively connected to the negative poles of the battery to be detected; the ESD protection device The negative poles of the battery are respectively connected to the positive poles of the battery to be detected; the ESD protection devices are connected in series to each other to form a series circuit; one end of the series circuit is connected to the power supply pin of the battery management chip; the other end of the series circuit One end is grounded and connected to the battery management chip.

Further, it also includes: a first diode and a second diode; the anode of the battery to be detected is connected to the first power supply pin and the detection pin of the battery management chip; the first diode The tube and the second diode are connected in antiparallel between the first power supply pin and the detection pin.

Further, it also includes: a first pmos tube, a second pmos tube, a first nmos tube, and a second nmos tube; the gate of the first pmos tube is connected to the source, and is connected to the first pmos tube of the battery management chip. The power supply pin is connected, the drain of the first pmos tube is connected to the second power supply pin of the battery management chip; the gate of the first nmos tube is connected to the source and grounded; the drain of the first nmos tube is connected to the source The drain is connected to the second power supply pin of the battery management chip; the gate of the second pmos tube is connected to the source and connected to the second power supply pin of the battery management chip, and the second pmos tube is connected to the second power supply pin of the battery management chip. The drain is connected to the low-voltage signal pin of the battery management chip; the gate of the second nmos tube is connected to the source and grounded, and the drain of the second nmos tube is connected to the low-voltage signal pin of the battery management chip connect.

The beneficial effects of the present invention are:

The ESD protection device and the ESD circuit suitable for the battery management chip provided by the present invention connect the N well area of the ESD protection device to high level, and connect the ESD protection devices in the ESD circuit to the two ends of the battery one by one. When the chip is working normally, the positive and negative terminals of the ESD protection device can reach a high voltage of tens of volts with the ground as the reference voltage; when electrostatic discharge occurs, the voltage difference between any adjacent two ports of the ESD protection device will not exceed the chip voltage. The voltage that the internal circuit and device can withstand realizes the ESD protection of the battery management chip.

Description of drawings

Fig. 1 is the circuit diagram of existing ESD circuit;

Figure 2 is a schematic diagram of the connection between the battery management chip and the battery;

Fig. 3 is the structural sectional view of the ESD protection device that the embodiment of the present invention provides;

4 is a schematic structural diagram of an NPN transistor parasitic by an ESD protection device provided by an embodiment of the present invention;

5 is a circuit diagram of an ESD circuit suitable for a battery management chip provided by an embodiment of the present invention;

6 is a path diagram of the discharge current when the positive and negative pulse test between the battery pin and the VH power supply is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention;

FIG. 7 is a path diagram of the discharge current when the positive and negative pulse test between the battery pin and the 5V power supply is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention;

FIG. 8 is a path diagram of the discharge current when the positive and negative pulse test between the battery pin and the ground is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention;

9 is a path diagram of the discharge current when the positive and negative pulse test between the battery pin and the low-voltage signal pin Bn is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention;

FIG. 10 is a path diagram of discharge current when positive and negative pulse tests between battery pins are performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention.

detailed description

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation of the ESD protection device proposed according to the present invention and the ESD circuit applicable to the battery management chip will be described below in conjunction with the accompanying drawings and preferred embodiments and the working principle in detail.

Referring to Figure 3, the ESD protection device provided by the embodiment of the present invention includes: P-type substrate (Psub), N-type buried layer (BN), high-voltage N-well region (HVnwell), high-voltage P-well region (HVpwell), low-voltage P well region (pwell) and low-voltage ESDNMOS tube; N-type buried layer is on P-type substrate; high-voltage P-well region is on N-type buried layer; low-voltage P-well region is on high-voltage P-well region; low-voltage ESDNMOS tube is on In the low-voltage P well region; the high-voltage N well region is outside the high-voltage P well region and is in contact with the N-type buried layer; the high-voltage N well region and the N-type buried layer completely isolate the P-type substrate from the high-voltage P well region. The gate (Gate) of the low-voltage ESDNMOS transistor in the low-voltage P-well region is connected to the source (Source), and connected to the high-voltage P-well region as the anode of the protection device; the drain of the low-voltage ESDNMOS transistor in the low-voltage P-well region ( drain) is connected to the high-voltage N well region as the negative pole of the protection device. In this embodiment, the high-voltage N-well region is connected to a high level of 23V, and the high-voltage P-well region and the low-voltage P-well region are connected to a level of 20V.

When the ESD protection device conducts forward, there is only a voltage drop of several hundred millivolts (the value of the voltage drop depends on the manufacturing process of the device, such as material, doping concentration, hierarchical structure, etc.); when the ESD protection device conducts reversely, The voltage across the ESD protection device is generally lower than the internal circuit of the chip and the voltage that the device can withstand (the voltage value depends on the manufacturing process of the device, such as material, doping concentration, hierarchical structure, etc.), and conducts a large amount of current at the same time. Because between the high-voltage N-well region and the ground, and between the high-voltage P-well region and the ground can withstand high voltage, the positive and negative ends of the ESD protection device can withstand high voltage with the ground as the reference level.

Specifically, when the negative electrode voltage of the ESD protection device remains constant and the positive electrode voltage increases, the pn junction formed by the pwell and the drain is forward-conducting, providing a low-resistance current path, and the voltage drop between the positive and negative electrodes is about several hundred millivolts. Processes are subject to change. When the anode voltage of the ESD protection device remains unchanged and the cathode voltage increases, see FIG. 4 , the ESD protection device parasitizes an NPN transistor. The diode between the collector and the base of the NPN tube conducts in reverse, and the current flowing through the base increases the base voltage. When the base voltage rises enough to open the pn junction between the base and emitter, the parasitic NPN transistor is turned on. If the negative electrode voltage is continuously increased, that is, the collector voltage of the parasitic NPN transistor is increased, the current flowing through the parasitic NPN transistor increases at this time. According to the design manual provided by the process manufacturer and the required ESD protection level, the length and width of the channel of the ESD protection device can be reasonably designed so that the ESD current can be fully released without causing damage to the ESD protection device. Since the parasitic NPN transistor is turned on, the collector does not need to maintain a high voltage to maintain the on-state of the device, so the collector voltage will drop. This snapback phenomenon (snapback) is often found in ESD devices, which also makes ESD protection When the device flows a large amount of current, the voltage is maintained at a low level, which protects the circuits inside the chip.

Referring to Fig. 5, the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention includes: at least one of the above-mentioned ESD protection devices A, the first diode, the second diode, the first HVESDpmos1 tube, and the second ESDpmos2 tube, the first ESDnmos1 tube and the second ESDnmos2 tube; the positive poles of the ESD protection device A are respectively connected to the negative poles of the single-section battery to be detected in one-to-one correspondence; the negative poles of the ESD protection device A are respectively connected to the single-section Positive connection of the battery to be tested. The ESD protection devices A are connected in series to form a series circuit; one end of the series circuit is connected to the first power supply pin (VH) of the battery management chip; the other end of the series circuit is grounded (GND) and connected to the battery management chip. In this embodiment, the battery to be detected is a series battery. The positive terminal (highest voltage) of the battery to be detected is connected to the first power supply pin (VH) and the detection pin (CH) of the battery management chip. Since all the current consumed by the chip flows through the first power pin VH, considering the existence of parasitic resistance, the voltage of the first power pin VH is usually slightly lower than the highest voltage of the battery in series. Therefore, in order to improve the detection accuracy, the CH pin of the chip is used as the detection pin. Since no current flows through the CH pin, the CH pin truly reflects the highest voltage of the battery in series, which improves the detection accuracy. The first diode and the second diode are connected in antiparallel between the first power supply pin VH and the detection pin CH; the negative pole (lowest voltage) of the battery to be tested is connected to the ground pin GND of the battery management chip. The gate and source of the first HVESDpmos1 transistor are connected together and connected to the first power supply pin (VH) of the battery management chip. The drain of the first HVESDpmos1 tube is connected to the second power supply pin (5V power supply pin) of the battery management chip; the gate and source of the first ESDnmos1 tube are connected together and connected to the ground GND; the first ESDnmos1 tube’s The drain is connected to the 5V power supply pin of the battery management chip. The gate and source of the second ESDpmos2 tube are connected together and connected to the 5V power supply pin of the battery management chip, and the drain of the second ESDpmos2 tube is connected to the low-voltage signal pin Bn of the battery management chip; the second ESDnmos2 tube's The gate and the source are connected together and connected to the ground GND, and the drain of the second ESDnmos2 transistor is connected to the low-voltage signal pin Bn of the battery management chip.

Due to the randomness of the electrostatic discharge phenomenon, there needs to be an ESD discharge path between any two pins of the battery management chip to ensure that the chip is not damaged during the process of manufacturing, production, testing, storage, and handling. In the actual ESD test, at least include the positive and negative pulse test between the battery pin and the power supply, the positive and negative pulse test between the battery pin and the ground, and the positive and negative pulse test between the battery pins.

Referring to FIG. 5 , the inside of the dotted box indicates the chip, and the outside of the dotted box indicates the peripheral circuit and pin information of the chip. There are two power supply pins, namely VH pin and 5V pin (5V is to provide power for the low-voltage analog circuit inside the chip, which is required by the system design and is also related to the selected low-voltage device). Since the VH voltage is the highest voltage of the battery in series, when the battery supplies power to the load or is charged and discharged, the VH voltage will have a large change, and the voltage value is high, which is not suitable for powering the analog circuit inside the chip. Therefore, the VH voltage is used Generate 5V voltage to power the analog circuit inside the chip. The Bn pin is a low-voltage signal pin with 5V as the ESD power supply. The chip pins connected on the series battery node are as described above.

Taking any pin CHn on the battery string node as an example, describe the discharge path of ESD current, including the following situations: positive and negative ESD pulses between the CHn pin and the power supply, positive and negative ESD pulses between the CHn pin and the ground Pulse, positive and negative ESD pulses between CHn pin and low voltage signal pin Bn, positive and negative ESD pulses between battery string node pins.

The positive and negative pulse test between the battery pin and the power supply VH is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention. As shown in FIG. 6, the current between any battery string node pin CHn and the power supply VH Evacuation pathway. The solid-line pulse on the CHn pin indicates that a positive ESD pulse is applied to the CHn pin, and the VH pin is grounded. The ESD current path is shown by the solid-line arrow. D flows out of the VH pin. The dotted line pulse on the CHn pin indicates that a negative ESD pulse is applied to the CHn pin, the VH pin is grounded, and the ESD current path is shown by the dotted arrow. Through the series ESD protection device A, it flows out from the CHn pin.

The positive and negative pulse test between the battery pin and the power supply 5V is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention. As shown in FIG. 7, it is between any battery string node pin CHn and the power supply 5V. ESD current discharge path. The solid-line pulse on the CHn pin indicates that a positive ESD pulse is applied to the CHn pin, and the 5V pin is grounded. The ESD current path is shown by the solid-line arrow. 5V flows out of the pin through the parasitic diode of the low voltage ESDnmos1 on the 5V pin. The dotted line pulse on the CHn pin indicates that a negative ESD pulse is applied to the CHn pin, the 5V pin is grounded, and the ESD current flows from the 5V pin to CHn. The ESD current path is shown by the dotted arrow. The ESD current flows from the 5V pin through the parasitic diode of the high-voltage ESD device HVESDpmos1 to the power line VH, flows through the forward diode D, and then flows in the reverse direction through the series ESD protection device A, and is passed by CHn pin out.

The positive and negative pulse test between the battery pin and the ground is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention, as shown in Figure 8, it is between any battery string node pin CHn and the ground (GND) ESD current discharge path. The solid-line pulse on the CHn pin indicates that a positive ESD pulse is applied to the CHn pin, the GND pin is grounded, and the ESD current flows from CHn to the ground. As shown by the solid line arrow in the figure, the ESD current flows reversely through the series ESD protection device A to the ground (GND); the dotted line pulse on the CHn pin indicates that the ESD negative pulse is added to the CHn pin, and the GND pin is grounded , the ESD current flows from GND to CHn. As shown by the dotted arrow in the figure, the ESD current flows forward through the series connected ESD protection device A from the GND pin, and flows out from the CHn pin.

The positive and negative pulse test between the battery pin and the low-voltage signal pin Bn is performed through the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention. As shown in FIG. 9, it is any battery string node pin CHn and the low-voltage signal ESD current discharge path between pins Bn. The solid-line pulse on the CHn pin indicates that a positive ESD pulse is added to the CHn pin, the Bn pin is grounded, and the ESD current flows from CHn to Bn. As shown by the solid arrow in the figure, the ESD current flows reversely from the CHn pin through the series ESD protection device A to ground (GND), and then flows out of the Bn pin through the ESDnmos2 parasitic diode in the ESD structure of the Bn pin. The dotted line pulse on the CHn pin indicates that a negative pulse is applied to the CHn pin, the Bn pin is grounded, and the ESD current flows from Bn to CHn. As shown by the dotted arrow in the figure, the ESD current flows from the Bn pin, flows through the ESDpmos2 parasitic diode in the Bn pin ESD structure, then flows through the HVESDpmos1 parasitic diode in the 5V pin ESD structure, reaches the VH power line, and then The reverse direction flows out from the CHn pin through the ESD protection device A connected in series.

As shown in Figure 10, it is the ESD current discharge path between any two battery string node pins. Any two pins are CHn1 and CHn2 respectively. When the positive ESD pulse is applied between CHn1 and CHn2, the ESD current flows from CHn1 to CHn2, as shown by the solid arrow path, it conducts the ESD protection device A in reverse, and the ESD current flows directly from CHn1 to CHn2. When a negative ESD pulse is applied between CHn1 and CHn2, the ESD current flows from CHn2 to CHn1. As shown by the dotted arrow in the figure, the ESD current flows forward through the series ESD protection device A from CHn2, and flows out from the CHn1 pin.

It should be noted here that although the ESD current will choose a low-impedance path to discharge when electrostatic discharge occurs, the discharge path is usually not the only one. The above content only describes a possible ESD current discharge path. The embodiment of the present invention There is no specific restriction on the discharge path of the ESD current.

It should also be noted that the embodiment of the present invention takes the battery management chip as an example, but it is not limited to the battery management chip, and it is also applicable in some circuits that require high common mode and differential signal detection. The specific circuit connection relationship is determined by each It is determined by the circuit structure and detection requirements, and no specific limitation is made here.

The ESD protection device and the ESD circuit suitable for the battery management chip provided by the embodiment of the present invention connect the N well area of the ESD protection device A to a high level, and connect the ESD protection device A in the ESD circuit to the single cell The two ends of the battery are connected. When the chip is working normally, the positive and negative terminals of the ESD protection device A can reach a high voltage of tens of volts with the ground as the reference voltage; when electrostatic discharge occurs, the voltage difference between any adjacent two ports of the ESD protection device A will not It exceeds the voltage that the internal circuits and devices of the chip can withstand, and realizes the ESD protection of the battery management chip.

Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.

Claims (3)

1. An ESD circuit suitable for a battery management chip, characterized in that it includes: at least one ESD protection device; the ESD protection device includes: a substrate, a buried layer, a high-voltage N well region, a high-voltage P well region, A low-voltage P-well region and a low-voltage NMOS transistor; the buried layer is on the substrate; the high-voltage P-well region is on the buried layer; the low-voltage P-well region is on the high-voltage P-well region; The low-voltage NMOS transistor is in the low-voltage P-well region; the high-voltage N-well region is outside the high-voltage P-well region and is in contact with the buried layer; the gate and source of the low-voltage NMOS transistor connected, and connected to the high-voltage P well region as the positive pole of the protection device; the drain of the low-voltage NMOS transistor is connected to the high-voltage N well region as the negative pole of the protection device; the positive poles of the ESD protection device are respectively connected to the The negative pole of the detected battery is connected; the negative poles of the ESD protection devices are respectively connected to the positive poles of the battery to be detected; the ESD protection devices are connected in series with each other to form a series circuit; one end of the series circuit is connected to the power supply of the battery management chip pin connection; the other end of the series circuit is grounded and connected to the battery management chip. 2. The ESD circuit applicable to battery management chips as claimed in claim 1, further comprising: a first diode and a second diode; the positive electrode of the battery to be detected is connected to the battery management chip. The first power supply pin of the chip is connected to the detection pin; the first diode and the second diode are antiparallel connected between the first power supply pin and the detection pin. 3. The ESD circuit suitable for battery management chips according to claim 2, further comprising: a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube; the first pmos tube The gate of the tube is connected to the source, and is connected to the first power supply pin of the battery management chip, and the drain of the first pmos tube is connected to the second power supply pin of the battery management chip; the first nmos The grid of the tube is connected to the source and grounded; the drain of the first nmos tube is connected to the second power supply pin of the battery management chip; the grid of the second pmos tube is connected to the source, and Connected to the second power supply pin of the battery management chip, the drain of the second pmos tube is connected to the low voltage signal pin of the battery management chip; the gate of the second nmos tube is connected to the source and grounded , the drain of the second nmos tube is connected to the low-voltage signal pin of the battery management chip.