CN103715185A - Diode and manufacturing method thereof - Google Patents
Diode and manufacturing method thereof Download PDFInfo
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- CN103715185A CN103715185A CN201310755008.4A CN201310755008A CN103715185A CN 103715185 A CN103715185 A CN 103715185A CN 201310755008 A CN201310755008 A CN 201310755008A CN 103715185 A CN103715185 A CN 103715185A
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Abstract
The invention provides a diode and a manufacturing method thereof. The diode comprises metal plates and one or more semiconductor diode chips. Each semiconductor diode chip is clamped between every two adjacent metal plates. Each semiconductor diode chip comprises a semiconductor substrate, a first electrode layer and a second electrode layer. Each semiconductor chip comprises an N doped layer and a P doped layer on the N doped layer, and PN junctions are formed between the P doped layers and the N doped layers. The first electrode layers cover the upper surfaces of the semiconductor substrates, the second electrode layers cover the lower surfaces of the semiconductor substrates, each first electrode layer makes contact with two metal plates adjacent to the corresponding first electrode layer, and each second electrode layer makes contact with two metal plates adjacent to the corresponding second electrode layer.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to diode and manufacturing and encapsulation method thereof.
Background technology
Diode has a wide range of applications at electronic applications as the simplest semiconductor device of structure, and high-voltage diode is wherein important Yi Ge branch, on current market, has widespread demand.Along with the development of electronic technology, the demand withstand voltage to diode is more and more higher, thereupon design and processing technology is also proposed to more and more higher requirement.Therefore, the cost of high-voltage diode is constantly soaring, and design and processes level has become to improve the withstand voltage bottleneck of diode.
Typically, semiconductor diode is the device consisting of a PN junction, and its P end lead-out wire is P end, and N end lead-out wire is negative pole.When semiconductor diode P termination high potential, N termination electronegative potential and both end voltage is poor while being greater than threshold voltage can forward conduction; When semiconductor diode N termination high potential, P termination electronegative potential, be reverse blocking, as poor in reverse voltage while surpassing certain numerical value, diode is by reverse breakdown likely damage, and corresponding reverse voltage is called reverse breakdown voltage.Therefore expectation improves the reverse breakdown voltage of diode, allows additional inverse peak voltage (oppositely withstand voltage) while improving thus diode long-term work.Conventional semiconductor diode has silicon diode, germanium diode etc.The reverse breakdown voltage value difference of the diode of different model is very not large, from tens volts to several kilovolts.In general, the reverse requirement of withstand voltage of diode is higher, and its designing requirement is also higher, and its manufacturing cost is also higher.
This area expects to have diode and manufacturing and encapsulation method thereof cheaply, especially cheaply high-voltage diode and manufacturing and encapsulation method thereof.
Summary of the invention
The technical problem to be solved in the present invention is to provide diode and manufacture method thereof, especially cheaply high-voltage diode and manufacture method thereof.
In one embodiment, a kind of diode can comprise: metallic plate; And one or more semiconductor diode chips, each semiconductor diode chip is clipped between two adjacent metallic plates, wherein each semiconductor diode chip comprises: Semiconductor substrate, described Semiconductor substrate comprises N doped layer and the P doped layer on described N doped layer, between described P doped layer and described N doped layer, forms PN junction; And covering the first electrode layer of described Semiconductor substrate upper surface and the second electrode lay of the described Semiconductor substrate lower surface of covering, described the first electrode layer contacts respectively two adjacent metallic plates with described the second electrode lay.
In one embodiment, described N doped layer comprises N+ type ground floor and the N-type second layer on described N+ type ground floor, described P doped layer comprises the 4th layer, the 3rd layer, P type and the P+ type on the 3rd layer, described P type, between the 3rd layer, wherein said P type and the described N-type second layer, forms PN junction.
In one embodiment, described the first electrode layer and described the second electrode lay are respectively welded to two adjacent metallic plates.
In one embodiment, a plurality of semiconductor diode chips are clipped in respectively between two adjacent metallic plates with identical PN junction direction, and a metallic plate for sharing between adjacent semiconductor diode chip.
In one embodiment, the size of described metallic plate is greater than the size of described semiconductor diode chip, and described diode also comprises: the passivating material of filling in the space between adjacent metal sheets.
In one embodiment, described diode also comprises: from the extended contact conductor of metallic plate at the two ends of described diode.
In one embodiment, described Semiconductor substrate is silicon substrate or germanium substrate.
In one embodiment, the thickness of described Semiconductor substrate is between 100um～500um, and resistivity is between 0.002 Ω cm～0.05 Ω cm.
In one embodiment, described diode also comprises: the thickness of described the first electrode layer and described the second electrode lay is respectively between 1um～5um.
In one embodiment, described the first electrode layer and described the second electrode lay are conductive metallic materials, and described conductive metallic material comprises aluminium, silver, copper, nickel or alloy material.
Diode fabricating method can comprise: step 1: form a Semiconductor substrate that comprises N doped layer and the P doped layer on described N doped layer, between described P doped layer and described N doped layer, form PN junction; Step 2: cover the first electrode layer and cover the second electrode lay to form semiconductor diode chip at described Semiconductor substrate lower surface at described Semiconductor substrate upper surface; And step 3: one or more semiconductor diode chips are clipped in respectively between two adjacent metallic plates, and wherein described first electrode layer of each semiconductor diode chip contacts respectively two adjacent metallic plates with described the second electrode lay.
In one embodiment, described step 1 also comprises: comprise the Semiconductor substrate of N doped layer and the P doped layer on described N doped layer in formation after, carry out high annealing knot.
In one embodiment, described step 1 also comprises: the Semiconductor substrate that comprises N doped layer is provided, and described N doped layer comprises N+ type ground floor and the N-type second layer on described N+ type ground floor; The described N-type second layer is carried out to the doping of P type to form the 3rd layer, P type; And the 3rd layer, described P type is carried out to P+ doping to form the 4th layer, P+ type, wherein said P doped layer comprises the 4th layer, the 3rd layer, described P type and described P+ type.
In another embodiment, described step 1 also comprises: the Semiconductor substrate that comprises P doped layer is provided, and described P doped layer comprises P+ type ground floor and the P-type second layer on described P+ type ground floor; The described P-type second layer is carried out to N-type doping to form the 3rd layer of N-type; And the 3rd layer of described N-type carried out to N+ doping to form the 4th layer, N+ type, wherein said N doped layer comprises the 4th layer, the 3rd layer of described N-type and described N+ type.
In one embodiment, described step 2 further comprises: to having covered the described Semiconductor substrate of described the first electrode layer and described the second electrode lay, carry out scribing to form semiconductor diode chip.
In one embodiment, described step 3 further comprises: described the first electrode layer and described the second electrode lay are respectively welded to two adjacent metallic plates.
In one embodiment, described step 3 further comprises: a plurality of semiconductor diode chips are clipped in respectively between two adjacent metallic plates with identical PN junction direction, and a metallic plate for sharing between adjacent semiconductor diode chip.
In one embodiment, the size of described metallic plate is greater than the size of described semiconductor diode chip, and described method also comprises: in the space between adjacent metal sheets, fill passivating material.
In one embodiment, described diode fabricating method also comprises: from the metallic plate at the two ends of described diode, extend contact conductor.
In one embodiment, described Semiconductor substrate is silicon substrate or germanium substrate.
In one embodiment, the thickness of described Semiconductor substrate is between 100um～500um, and resistivity is between 0.001 Ω cm～0.05 Ω cm.
In one embodiment, the thickness of described the first electrode layer and described the second electrode lay is respectively between 1um～5um.
In one embodiment, described the first electrode layer and described the second electrode lay are conductive metallic materials, and described conductive metallic material comprises silver, copper, nickel or alloy material.
The present invention combines chip manufacturing with chip package, greatly simplified manufacturing process, when greatly having reduced the production cost of high-voltage diode, the voltage endurance capability of diode can be accomplished to very high level.Because do not need photoetching, so diode fabricating method provided by the invention has the higher degree of freedom in application aspect.The method also can promote the use of the processing and manufacturing of other series semiconductor diodes, for traditional semiconductor diode manufacture provides new concept and model.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation of N type semiconductor substrate according to an embodiment of the invention.
Fig. 2 is the N type semiconductor substrate of Fig. 1 cross sectional representation after carrying out P doping.
Fig. 3 is that the Semiconductor substrate of Fig. 2 is further being carried out the cross sectional representation after P+ doping.
Fig. 4 is the Semiconductor substrate of Fig. 3 cross sectional representation after coated electrode.
Fig. 5 is the vertical view of Semiconductor substrate wafer according to an embodiment of the invention.
Fig. 6 is the cross sectional representation of diode according to an embodiment of the invention.
Fig. 7 is the cross sectional representation of diode after filling passivating material according to an embodiment of the invention.
Fig. 8 is the cross sectional representation of diode after encapsulation according to an embodiment of the invention.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.The invention provides a kind of diode and manufacture method thereof, below in conjunction with each step in the manufacture method of this diode, be elaborated.
Step 1: form the Semiconductor substrate that comprises N doped layer and P doped layer, form PN junction (referring to Fig. 1 to 3) between this P doped layer and N doped layer.
As example, Fig. 1 shows the process that forms PN junction with N type semiconductor substrate to Fig. 3.Fig. 1 is the cross sectional representation of N type semiconductor substrate 10 according to an embodiment of the invention.As shown in Figure 1, can provide N type semiconductor substrate 10, it comprises the ground floor 101 of heavy doping (N+) and the second layer 102 of light dope (N-).Semiconductor substrate 10 can be such as silicon substrate, germanium substrate etc., and N-type alloy is pentad, such as phosphorus, arsenic, antimony etc.In one embodiment, N type semiconductor substrate 10 can be integrally formed, for example, by carrying out N+ doping from lower surface and carrying out N-from upper surface and adulterate and form respectively ground floor 101 and the second layer 102.In another embodiment, can first provide N+ type ground floor 101, on N+ type ground floor 101, by epitaxial growth and N-, adulterate to form the N-type second layer 102.The thickness of the N-type second layer 102 and resistivity mainly determines by the withstand voltage scope of the diode designing, and for example thickness can be between 50um～500um, and resistivity can be between 20 Ω cm～500 Ω cm.It will be understood by those skilled in the art that to form by other means to there is the Semiconductor substrate 10 that comprises as shown in Figure 1 N doped layer and N-doped layer, as method of diffusion.
Fig. 2 is the N type semiconductor substrate 10 of Fig. 1 cross sectional representation after carrying out P doping.As shown in Figure 2, the N-type second layer 102 of the N type semiconductor substrate 10 of Fig. 1 is carried out to the doping of P type, form the 3rd layer 103, P type.P type alloy is triad, such as boron element etc.It will be understood by those skilled in the art that between the 3rd layer 103, P type and the N-type second layer 102 and form PN junction.In one embodiment, N type semiconductor substrate 10 is carried out can carrying out high annealing knot after the doping of P type, so that diffuseing to form downwards more equably, P type alloy distributes, to form good PN junction between the 3rd layer 103, P type and the N-type second layer 102.
Fig. 3 is that the Semiconductor substrate 10 of Fig. 2 is further being carried out the cross sectional representation after P+ doping.As shown in Figure 3, the P type of the Semiconductor substrate 10 of Fig. 2 is carried out to the doping of P+ type for the 3rd layer 103, form the 4th layer 104, P+ type.The 4th layer 104, P+ type is higher than the doping content of the 3rd layer 103, P type, so conductance is higher, is conducive to form good ohmic contact.
As mentioned above, Fig. 1 shows the process that forms PN junction with N type semiconductor substrate to Fig. 3.But in alternative embodiment, also can form PN junction with P type semiconductor substrate, that is, Fig. 1 can be exchanged to N-type and P type in Fig. 3.For example, can provide the Semiconductor substrate 10 that comprises P doped layer, this P doped layer comprises P+ type ground floor 101 and the P-type second layer 102; The P-type second layer 102 is carried out to N-type doping to form the 3rd layer 103 of N-type; And N-type is carried out to N+ doping for the 3rd layer 103 to form the 4th layer, N+ type, wherein N doped layer comprises the 4th layer 104, the 3rd layer 103 of N-type and N+ type.
Step 2: cover the first electrode layer 105 and cover the second electrode lay 106 at Semiconductor substrate 10 lower surfaces at Semiconductor substrate 10 upper surfaces.
Fig. 4 is the Semiconductor substrate 10 of Fig. 3 cross sectional representation after coated electrode.As shown in Figure 4, at Semiconductor substrate 10 upper surfaces of Fig. 3 upper surface of the 4th layer 104 (that is, P+ type), cover the first electrode layer 105 and cover the second electrode lay 106 at Semiconductor substrate 10 lower surfaces (that is, the lower surface of N+ type ground floor 101).The first electrode layer 105 and the second electrode lay 106 can adopt conductive metallic material, such as silver, copper, nickel, various alloys etc.The first electrode layer 105 and the second electrode lay 106 can adopt the methods such as evaporation, sputter to form, and electrode layers thickness can be respectively between 1um～5um.
Fig. 5 is the vertical view of Semiconductor substrate wafer according to an embodiment of the invention.For example, the Semiconductor substrate shown in Fig. 1-4 10 can be circular wafer.After the processing step shown in Fig. 1 to Fig. 4, can carry out scribing to this circular wafer, form the semiconductor diode chip 22 of single crystal grain form.It will be understood by those skilled in the art that each semiconductor diode chip 22 forming after scribing has sandwich construction as shown in Figure 4.In the present invention, because without litho pattern, so can carry out scribing according to the demand of different current capacities more neatly.For example, can configure according to demand shape (for example square or rectangular) and the size of single crystal grain.
Step 3: one or more semiconductor diode chips 22 are clipped in respectively between two adjacent metallic plates 24 to form diode, and wherein the first electrode layer 105 of semiconductor diode chip 22 contacts respectively two adjacent metallic plates 24 with the second electrode lay 106.
Fig. 6 is the cross sectional representation of diode according to an embodiment of the invention.The semiconductor diode chip forming after scribing 22 is clipped between metallic plate 24 to form diode 20, and the metallic plate 24 at diode 20 two ends is connected to contact conductor 26.Metallic plate 24 can be soldered to the electrode layer (the first electrode layer 105 or the second electrode lay 106) on semiconductor diode chip 22 surfaces.In one embodiment, can be according to the semiconductor diode chip 22 of the withstand voltage demand series connection of difference varying number, the PN junction direction of the semiconductor diode chip 22 of wherein each series connection is consistent.Semiconductor diode chip 22 quantity of series connection are more, diode 20 reverse withstand voltage just higher.In Fig. 6, illustrated 8 semiconductor diode chips 22 are respectively connected with metallic plate 24, but in other embodiments, diode 20 can comprise one or many semiconductor diode chips 22.In addition, the size of metallic plate 24 can be more than or equal to the size of semiconductor diode chip 22, but after excessive erosion, the size of metallic plate 24 is greater than the size of semiconductor diode chip 22, so that semiconductor diode chip 22 side ratios are easier to carry out passivation.Metallic plate 24 is generally acidproof metal, as Pb, Sn etc.On the one hand, metallic plate 24 is for encapsulating semiconductor diode chip 22; On the other hand, metallic plate 24 is convenient to the side passivation of diode 22 and is conducive to the electric field of balance diode 22.
Fig. 7 is the cross sectional representation of diode 20 after filling passivating material according to an embodiment of the invention.For example, passivating material 28 is filled on diode 20 surfaces that can form in as Fig. 6 around, to prevent electric leakage.In one embodiment, if the size of metallic plate 24 is greater than the size (as shown in Fig. 6 and 7) of semiconductor diode chip 22, more advantageously in the space between each metallic plate 24, fill passivating material 28.For example, can filling glass powder sintering or other dielectric passivations.
Fig. 8 is the cross sectional representation of diode 20 after encapsulation according to an embodiment of the invention.The diode forming in Fig. 7 20 for example can be encapsulated to 29(, plastic packaging, curing) to form diode 20 finished products.
The diode 20 being formed as described above is by the structure having as shown in Figure 8, and it comprises metallic plate 24; And one or more semiconductor diode chips 22, each semiconductor diode chip 22 is clipped between two adjacent metallic plates 24, and wherein each semiconductor diode chip 22 has structure as shown in Figure 4.That is, each semiconductor diode chip 22 comprises: Semiconductor substrate 10, and wherein Semiconductor substrate 10 comprises N doped layer and the P doped layer on N doped layer, between this P doped layer and N doped layer, forms PN junction; And cover the first electrode layer 105 of Semiconductor substrate 10 upper surfaces and the second electrode lay 106 of covering Semiconductor substrate 10 lower surfaces, wherein the first electrode layer 105 contacts respectively two adjacent metallic plates 24 with the second electrode lay 106.In a further embodiment, N doped layer can comprise N+ type ground floor 101 and the N-type second layer 102, and P doped layer can comprise the 4th layer 104, the 3rd layer 103, P type and P+ type, wherein between the 3rd layer 103, P type and the N-type second layer 102, forms PN junction.
The present invention, by wafer manufacture and encapsulation are combined, has simplified wafer manufacturing process, thereby has reduced cost.Particularly; the present invention takes full wafer doping knot technique and in encapsulation process, adopts the packing forms of metallic plate to combine in manufacture of semiconductor; in encapsulation process, with doing passivation between metallic plate, the various protection structures in conventional semiconductors high-voltage device structure have been replaced; as potential dividing ring, cut-off ring (district), field plate or place oxide layer etc.; thereby save the flow processs such as the photoetching in semiconductor fabrication process, etching, oxidation, significantly simplified semiconductor manufacturing process and significantly reduced diode cost.Compared to existing technology, mesa technique of the present invention (for example, passivation sintering) has also been save slot type structure, thereby has saved effective chip area.When having improved the effective rate of utilization of chip, because there is no figure, also can carry out according to actual needs scribing, greatly increased the flexibility of using.Be similar to high voltage silicon stack, during encapsulation, can carry out according to actual needs the series connection of tube core, to realize different withstand voltage demands.
By reference to the accompanying drawings embodiments of the invention are described above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; not departing from the scope situation that aim of the present invention and claim protect, also can make a lot of forms, within these all belong to protection scope of the present invention.
Claims (23)
1. a diode, is characterized in that, comprising:
Metallic plate; And
One or more semiconductor diode chips, each semiconductor diode chip is clipped between two adjacent metallic plates, and wherein each semiconductor diode chip comprises:
Semiconductor substrate, described Semiconductor substrate comprises N doped layer and the P doped layer on described N doped layer, between described P doped layer and described N doped layer, forms PN junction; And
Cover the first electrode layer of described Semiconductor substrate upper surface and the second electrode lay of the described Semiconductor substrate lower surface of covering, described the first electrode layer contacts respectively two adjacent metallic plates with described the second electrode lay.
2. diode as claimed in claim 1, is characterized in that:
Described N doped layer comprises N+ type ground floor and the N-type second layer on described N+ type ground floor,
Described P doped layer comprises the 4th layer, the 3rd layer, P type and the P+ type on the 3rd layer, described P type, between the 3rd layer, wherein said P type and the described N-type second layer, forms PN junction.
3. diode as claimed in claim 1, is characterized in that:
Described the first electrode layer and described the second electrode lay are respectively welded to two adjacent metallic plates.
4. diode as claimed in claim 1, is characterized in that:
A plurality of semiconductor diode chips are clipped in respectively between two adjacent metallic plates with identical PN junction direction, and a metallic plate for sharing between adjacent semiconductor diode chip.
5. diode as claimed in claim 1, is characterized in that, the size of described metallic plate is greater than the size of described semiconductor diode chip, and described diode also comprises:
The passivating material of filling in the space between adjacent metal sheets.
6. diode as claimed in claim 1, is characterized in that, also comprises:
The extended contact conductor of metallic plate from the two ends of described diode.
7. diode as claimed in claim 1, is characterized in that:
Described Semiconductor substrate is silicon substrate or germanium substrate.
8. diode as claimed in claim 1, is characterized in that:
The thickness of described Semiconductor substrate is between 100um～500um, and resistivity is between 0.002 Ω cm～0.05 Ω cm.
9. diode as claimed in claim 1, is characterized in that, also comprises:
The thickness of described the first electrode layer and described the second electrode lay is respectively between 1um～5um.
10. diode as claimed in claim 1, is characterized in that, described the first electrode layer and described the second electrode lay are conductive metallic materials, and described conductive metallic material comprises silver, copper, nickel or alloy material.
11. 1 kinds of diode fabricating methods, is characterized in that, comprising:
Step 1: form the Semiconductor substrate that comprises N doped layer and the P doped layer on described N doped layer, form PN junction between described P doped layer and described N doped layer;
Step 2: cover the first electrode layer and cover the second electrode lay to form semiconductor diode chip at described Semiconductor substrate lower surface at described Semiconductor substrate upper surface; And
Step 3: one or more semiconductor diode chips are clipped in respectively between two adjacent metallic plates, and wherein described first electrode layer of each semiconductor diode chip contacts respectively two adjacent metallic plates with described the second electrode lay.
12. diode fabricating methods as claimed in claim 11, is characterized in that, described step 1 also comprises:
Comprise the Semiconductor substrate of N doped layer and the P doped layer on described N doped layer in formation after, carry out high annealing knot.
13. diode fabricating methods as claimed in claim 11, is characterized in that, described step 1 also comprises:
The Semiconductor substrate that comprises N doped layer is provided, and described N doped layer comprises N+ type ground floor and the N-type second layer on described N+ type ground floor;
The described N-type second layer is carried out to the doping of P type to form the 3rd layer, P type; And
The 3rd layer, described P type is carried out to P+ doping to form the 4th layer, P+ type, and wherein said P doped layer comprises the 4th layer, the 3rd layer, described P type and described P+ type.
14. diode fabricating methods as claimed in claim 11, is characterized in that, described step 1 also comprises:
The Semiconductor substrate that comprises P doped layer is provided, and described P doped layer comprises P+ type ground floor and the P-type second layer on described P+ type ground floor;
The described P-type second layer is carried out to N-type doping to form the 3rd layer of N-type; And
The 3rd layer of described N-type carried out to N+ doping to form the 4th layer, N+ type, and wherein said N doped layer comprises the 4th layer, the 3rd layer of described N-type and described N+ type.
15. diode fabricating methods as claimed in claim 11, is characterized in that, described step 2 further comprises:
To having covered the described Semiconductor substrate of described the first electrode layer and described the second electrode lay, carry out scribing to form semiconductor diode chip.
16. diode fabricating methods as claimed in claim 11, is characterized in that, described step 3 further comprises:
Described the first electrode layer and described the second electrode lay are respectively welded to two adjacent metallic plates.
17. diode fabricating methods as claimed in claim 11, is characterized in that, described step 3 further comprises:
A plurality of semiconductor diode chips are clipped in respectively between two adjacent metallic plates with identical PN junction direction, and a metallic plate for sharing between adjacent semiconductor diode chip.
18. diode fabricating methods as claimed in claim 11, is characterized in that, the size of described metallic plate is greater than the size of described semiconductor diode chip, and described method also comprises:
In space between adjacent metal sheets, fill passivating material.
19. diode fabricating methods as claimed in claim 11, is characterized in that, also comprise:
From the metallic plate at the two ends of described diode, extend contact conductor.
20. diode fabricating methods as claimed in claim 11, is characterized in that:
Described Semiconductor substrate is silicon substrate or germanium substrate.
21. diode fabricating methods as claimed in claim 11, is characterized in that:
The thickness of described Semiconductor substrate is between 100um～500um, and resistivity is between 0.002 Ω cm～0.05 Ω cm.
22. diode fabricating methods as claimed in claim 11, is characterized in that:
The thickness of described the first electrode layer and described the second electrode lay is respectively between 1um～5um.
23. diode fabricating methods as claimed in claim 11, is characterized in that, described the first electrode layer and described the second electrode lay are conductive metallic materials, and described conductive metallic material comprises silver, copper, nickel or alloy material.
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| CN201310755008.4A CN103715185A (en) | 2013-12-31 | 2013-12-31 | Diode and manufacturing method thereof |
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| CN201310755008.4A CN103715185A (en) | 2013-12-31 | 2013-12-31 | Diode and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104795335A (en) * | 2015-04-22 | 2015-07-22 | 中国振华集团永光电子有限公司（国营第八七三厂） | Method for manufacturing high-reliability glass passivation high-voltage silicon stacks |
| CN108493107A (en) * | 2018-04-19 | 2018-09-04 | 如皋市大昌电子有限公司 | A kind of manufacturing method of highly reliable glassivation high voltage silicon rectifier stack |
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| CN104795335B (en) * | 2015-04-22 | 2017-06-27 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of manufacture method of highly reliable glassivation high voltage silicon rectifier stack |
| CN108493107A (en) * | 2018-04-19 | 2018-09-04 | 如皋市大昌电子有限公司 | A kind of manufacturing method of highly reliable glassivation high voltage silicon rectifier stack |
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Application publication date: 20140409 |