CN103647553B - Direct current frequency modulation reference source circuit of broadband ultra low phase noise - Google Patents

Abstract

The present invention provides a DC FM reference source circuit with broadband ultra-low phase noise, including a digital-to-analog conversion circuit, a data processing and control circuit, a DDS circuit, a bandpass filter, a loop filter and an integrated frequency synthesis chip; The digital-to-analog conversion circuit controls the tiny modulation signal fm to obtain frequency modulation data after conversion by the analog-to-digital conversion circuit. The frequency modulation data is processed by the data processing and control circuit control and the frequency control word of the DDS circuit is operated, and the output of the DDS circuit is controlled to generate ultra-low phase noise. An ultra-low spurious modulated signal, the modulated signal is sent to the integrated frequency synthesis chip after being passed through a band-pass filter, and used as a reference signal of a phase-locked loop. The above scheme adopts analog-to-digital conversion and digital signal processing technology and DDS and PLL hybrid frequency synthesis technology, which can realize DC frequency modulation of tiny analog signal to broadband signal.

Description

A Broadband Ultra-Low Phase Noise DC FM Reference Source Circuit

technical field

The invention belongs to the technical field of phase noise testing, and in particular relates to a DC frequency-modulating reference source circuit with broadband ultra-low phase noise.

Background technique

In the field of phase noise testing, the frequency/phase detection method is one of the main methods for measuring phase noise. It has the characteristics of high measurement sensitivity, wide measurement range, and separable amplitude modulation noise, etc., and is widely used. However, the sensitivity of the measurement is limited by the phase noise of the reference source itself. The reference signal must have an equal frequency according to the signal under test, and the phase noise of the reference signal is better than that of the source under test, so the reference source signal must be a broadband ultra-low phase The synthetic frequency signal of the noise; in addition, in the process of measuring phase noise by the frequency/phase detection method, the measured signal and the reference source signal are mixed for frequency detection and phase detection, and the tiny noise signal extracted by the phase detector is digitally sampled and passed through a digital filter. After processing, the tuning end of the reference source is driven to form a closed-loop phase-locked loop, which requires the reference source to have the function of DC frequency modulation by the tiny noise signal.

Frequency synthesis technology has gone through three generations, namely direct frequency synthesis technology (DS, Direct Frequency Synthesis), phase-locked frequency synthesis technology (PLL) and direct digital frequency synthesis technology DDS (Direct Digital Synthesis).

Direct frequency synthesis technology uses a crystal oscillator as a reference source to obtain more frequency components through frequency mixing, frequency division, frequency multiplication and band-pass filtering. Direct frequency synthesis technology has outstanding advantages in low phase noise frequency synthesis, but the resolution of reference source design using this technology is low, and DC frequency modulation cannot be realized.

The phase-locked frequency synthesis technology uses one or several reference frequency sources to generate a series of combined frequencies through frequency mixing or frequency division, and then uses a phase-locked loop to lock the frequency of the voltage-controlled oscillator to the reference frequency. Its advantage is that the phase-locked loop is equivalent to a narrow-band tracking filter, so it can well select the signal of the required frequency, suppress spurious components, and is conducive to integration and miniaturization. In recent years, fractional frequency division technology has been widely used in phase-locked frequency synthesis, which enables DC frequency modulation to be realized in phase-locked frequency synthesis technology.

DDS is a new type of frequency and phase waveform synthesis technology. It makes full use of the characteristics of large-scale integrated circuits such as fast, low power consumption, large capacity, and small size. Compared with traditional frequency synthesizers, it has low phase noise, It has the advantages of high frequency resolution and rapid conversion, and its frequency and phase change continuity can be used for phase and frequency modulation. However, the DDS output frequency band is limited, and the actual maximum operating frequency must obey the Nyquist law, which is only half of the clock frequency, generally about 40% of the clock frequency; The coming DDS has many spurs.

The emergence of DDS technology makes it possible to develop a high-performance frequency source, that is, to combine the advantages of DDS and the previous two generations of synthesis technology to synthesize their advantages. This frequency synthesizer is called a hybrid frequency synthesizer (Hybrid Frequency Synthesis). There are many schemes for the mixed use of DDS and PLL, and different schemes have different characteristics and are suitable for different engineering needs.

Figure 1 shows the existing solution, which uses a phase-locked loop with a fractional frequency divider to synthesize the required frequency range and frequency resolution, performs analog-to-digital conversion on the modulation signal, and superimposes it on the fractional frequency division ratio. Change the fractional frequency division ratio to change the frequency of the synthesized signal to realize DC frequency modulation. The fractional frequency-division phase-locked loop circuit includes: a reference clock, a phase detector, an integrator, a voltage-controlled oscillator, a prescaler, a Σ-Δ fractional frequency divider and a modulation signal conditioning circuit.

The output signal of the voltage-controlled oscillator is directly output on one side, and the other is routed to the prescaler and Σ-Δ fractional frequency divider to achieve frequency division. The phase detector distinguishes the frequency-divided signal from the reference signal output by the reference clock phase, the integrator performs integral filtering on the phase detection error signal output by the phase detector, generates a voltage-controlled oscillator tuning error control signal, controls the output signal of the voltage-controlled oscillator and locks it on the reference clock frequency. The sigma-delta fractional frequency divider is an FPGA circuit. The modulated signal is controlled by the gain and bias control module to control the gain and bias of the modulated signal, and the analog-to-digital conversion is realized through the analog-to-digital converter, and the 16-bit digital signal is output to the Σ-Δ fractional frequency divider. The sigma-delta fractional divider also includes registers that store the fractional divider ratio. The modulated signal is converted by the 16-bit analog-to-digital converter and loaded to the corresponding position of the register through the 16-bit data line, thereby changing the frequency division ratio of the fractional frequency division. Change, the output signal of the voltage controlled oscillator also changes according to this rule, thus realizing DC frequency modulation.

The use of FPGA circuits to achieve fractional frequency division will be limited by the operating frequency of the device and the resolution of the fractional frequency division. It cannot work at a higher frequency and can only work at a lower phase detection frequency. The phase noise of the phase loop frequency synthesizer has an improving effect, so the mentioned prior art cannot optimize the phase noise of the synthesized signal.

Using a single phase-locked loop for frequency synthesis, in the case of a low reference frequency, if the output frequency of the synthesized signal is increased, the frequency division ratio of the loop must be increased, and increasing the frequency division ratio will cause the deterioration of the phase noise of the synthesized signal. Not suitable as a reference source for phase noise testing.

If the phase noise of the synthesized signal is further improved on the basis of the existing technology, it is necessary to adopt a structure in which multiple phase-locked loops are nested, which will make the frequency synthesis scheme very complicated and increase the cost.

Therefore, there are defects in the prior art and need to be improved.

Contents of the invention

The technical problem to be solved by the present invention is to provide a DC frequency-modulating reference source circuit with broadband ultra-low phase noise for the deficiencies of the prior art.

Technical scheme of the present invention is as follows:

A DC FM reference source circuit with broadband ultra-low phase noise, including a digital-to-analog conversion circuit, a data processing and control circuit, a DDS circuit, a bandpass filter, a loop filter and an integrated frequency synthesizer HMC830; The digital-to-analog conversion circuit controls the tiny modulation signal f _m to obtain FM data after being converted by the analog-to-digital conversion circuit, and the FM data is processed and controlled by the control circuit to operate with the frequency control word of the DDS circuit to control the output of the DDS circuit to generate ultra-low The modulated signal with ultra-low phase noise and stray, the modulated signal is sent to the integrated frequency synthesizer HMC830 after passing through the band-pass filter, as the reference signal of the phase-locked loop.

The reference source circuit, wherein the digital-to-analog conversion circuit includes a gain bias control circuit and an A/D conversion circuit; the gain bias control circuit is composed of a differential ADC driver AD8138 and resistors, capacitors, and inductance components, After the tiny modulation signal f _m is input to the gain bias control circuit, the DC bias and amplitude are adjusted to a state suitable for the conversion of the A/D conversion circuit and then input to the A/D conversion circuit; the A/D conversion circuit is composed of 1.8V, 12-bit, 250Msps analog-to-digital converter MAX1215EGK and resistance-capacitance components, the A/D conversion circuit converts the input signal to digital-to-analog conversion and outputs the signal DATA1.

The reference source circuit, wherein the digital signal processing and control circuit is composed of a digital signal processor, a clock processing circuit and a resistance-capacitance element, and the digital signal processor is used to perform digital filter processing on the 12-bit digital signal DATA1 To meet the signal characteristics required by different test conditions, digitally filter the output signal DATA2; the clock processing circuit is to convert the frequency and amplitude of the input clock signal f _clk to meet the requirements of the digital signal processor.

Described reference source circuit, wherein, described DDS circuit is made up of the direct frequency synthesizer AD9912 of two spurious suppression channels, the 1000MHz ultra-low noise reference signal f _ref is connected to AD9912 after being converted from single-ended to double-ended as a system The clock and the frequency control word CtrlDATA1 are generated by the CPU and sent to the FPGA through the interface circuit. Inside the FPGA, the frequency modulation data DATA2 is added to the frequency control word CtrlDATA1 to obtain a new frequency control word CtrlDATA2 to control the output of the AD9912; where the frequency control word CtrlDATA1 is set After being fixed, the frequency modulation data DATA2 is continuously received under the action of the synchronous clock, and is calculated with the frequency control word CtrlDATA1, and a new frequency control word CtrlDATA2 is continuously generated, and the frequency control word CtrlDATA2 is continuously changed under the action of the synchronous clock The output frequency of AD9912 realizes the modulation of the output frequency of AD9912 and outputs signal f ₁ .

The reference source circuit, wherein the phase-locked loop is used to extend the output frequency range of the DDS circuit to 1.6-2.4GHz; the phase-locked loop includes a loop filter and an integrated frequency synthesizer HMC830, the integrated The frequency synthesizer HMC830 integrates VCO, variable frequency divider, phase detector and charge pump inside; the output signal f ₁ of the DDS circuit is passed through a band-pass filter, and the output f ₂ of the band-pass filter is connected to the phase-locked loop detector The reference input terminal of the phase converter is used for phase discrimination with the signal f ₃ output by the variable frequency divider. The error signal output by the charge pump is connected to the loop filter. The loop filter filters out the high-frequency components in the error signal and adjusts The output frequency of the VCO enables the phase-locked loop to obtain a final output signal f _out of 1.6-2.4GHz; the bandwidth of the phase-locked loop is set to 450-550kHz, and the out-of-band spurs and phase-detection spurs carried by the DDS circuit are suppressed by the loop .

Using the above scheme: 1. Using analog-to-digital conversion and digital signal processing technology and DDS and PLL hybrid frequency synthesis technology can realize DC frequency modulation of tiny analog signals to broadband microwave signals. 2. The advanced DDS integrated chip is used to synthesize a higher frequency ultra-low phase noise reference signal, and the high phase detection frequency is used for phase locking, which reduces the deterioration of the phase noise of the reference signal by the phase locked loop and ensures the ultra-low frequency of the synthesized broadband signal. Low phase noise characteristics. 3. Adopt a phase-locked loop circuit with superior performance, which integrates a phase detector, a charge pump, a frequency divider, and a VCO circuit. The output frequency range of the VCO is high. signal frequency.

Description of drawings

FIG. 1 is a circuit diagram for realizing DC frequency modulation by changing the frequency division ratio in the prior art.

Fig. 2 is a circuit diagram of a DC frequency-modulating reference source with broadband ultra-low phase noise according to the present invention.

Fig. 3 is a DDS circuit diagram in the present invention.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

The realization principle of the present invention is shown in Fig. 2, mainly comprises digital-to-analog conversion circuit, data processing and control, DDS circuit, bandpass filter, loop filter and integrated frequency synthesizer HMC830 totally 6 parts, integrated frequency The synthesizer HMC830 is composed of a phase detector, a charge pump, a voltage-controlled oscillator and a variable frequency divider.

After the analog-to-digital conversion, the tiny modulation signal f _m is operated with the frequency control word of the DDS to control the output of the DDS to generate a modulated signal with ultra-low phase noise and ultra-low spurious, and the modulated signal is sent to the The phase-locked loop phase detector is used as the reference signal of the phase-locked loop. The wideband signal frequency synthesis is realized by controlling the variable frequency divider of the phase-locked loop.

Among them, the main function of the digital-to-analog conversion circuit is to convert the tiny modulation signal f _m into a 12-bit digital signal. The circuit includes two parts: gain, bias control and A/D conversion. The gain and bias control can adjust the small modulation signal f _m to a state suitable for A/D conversion, and maximize the use efficiency of the A/D converter. The A/D converter is composed of low distortion, differential ADC driver AD8138, 1.8V, 12-bit, 250Msps analog-to-digital converter MAX1215EGK and resistance-capacitance components.

The function of the digital signal processing and control circuit is to process the 12-bit digital signal and send the processed data to the DDS module. The circuit is composed of a digital signal processor, a clock processing circuit and related resistance-capacitance components. The function of the digital signal processor is to digitally filter the 12-bit digital signal to meet the signal characteristics required by different test conditions; the clock processing circuit is to convert the frequency and amplitude of the input clock signal to meet the requirements of the digital signal processor. Requirements.

Figure 3 shows the block diagram of the high-purity DDS module. In order to achieve ultra-low phase noise and ultra-low spurious, the high-purity DDS module uses a direct frequency synthesizer AD9912 with two spurious suppression channels. The 1000MHz ultra-low noise reference signal f _ref is connected to AD9912 after being converted from single-ended to double-ended As the system clock, the frequency control word CtrlDATA1 is sent from the CPU to the FPGA through the interface circuit. Inside the FPGA, the frequency modulation data is added to the frequency control word CtrlDATA1 to obtain a new frequency control word CtrlDATA2 to control the output of AD9912. The frequency control word CtrlDATA1 remains unchanged after being set, and the frequency modulation data is continuously received under the action of the synchronous clock, and is calculated with the frequency control word CtrlDATA1, and a new frequency control word CtrlDATA2 is continuously generated, and the frequency control word CtrlDATA2 is synchronously Under the action of the clock, the output frequency of AD9912 is constantly changed, and the modulation of the output frequency of AD9912 is realized.

The phase-locked loop is to extend the output frequency range of the high-purity DDS module to 1.6-2.4GHz. The phase-locked loop includes a loop filter and an integrated frequency synthesizer HMC830. The integrated frequency synthesizer HMC830 integrates functional units such as VCO, variable frequency divider, phase detector, and charge pump. The output signal of the high-purity DDS module is connected to the input terminal of the phase-locked loop phase detector after passing through the band-pass filter, and is phase-identified with the signal output by the variable frequency divider. The error signal output by the charge pump is connected with the loop filter, and the loop filter filters out the high-frequency components in the error signal, adjusts the output frequency of the VCO, and locks the VCO output frequency at 1.6-2.4GHz. The bandwidth of the phase-locked loop is set to about 500kHz, and the out-of-band spurs and phase-detection spurs carried by the DDS signal are suppressed by the loop.

Example 2

On the basis of the above embodiments, further, as shown in Figures 2-3, a broadband ultra-low phase noise DC FM reference source circuit, which includes a digital-to-analog conversion circuit, a data processing and control circuit, and a DDS circuit , band-pass filter, loop filter and integrated frequency synthesizer HMC830; the digital-to-analog conversion circuit controls the tiny modulation signal f _m to obtain frequency modulation data after conversion by the analog-to-digital conversion circuit, and the frequency modulation data is controlled by data processing and control circuit Operate with the frequency control word of the DDS circuit, control the output of the DDS circuit, and generate a modulated signal with ultra-low phase noise and ultra-low spurious. The modulated signal is sent to the integrated frequency synthesizer HMC830 after passing through a band-pass filter. As a reference signal for the phase-locked loop.

Described digital-to-analog conversion circuit comprises gain, bias control circuit and A/D conversion circuit; Described gain, bias control circuit are made up of differential ADC driver AD8138 and resistance, electric capacity, inductive components and parts, and tiny modulation signal f _m is input to After the gain bias control circuit, the DC bias and amplitude are adjusted to a state suitable for the conversion of the A/D conversion circuit and then input to the A/D conversion circuit; the A/D conversion circuit consists of 1.8V, 12-bit, 250Msps analog-to-digital conversion The device is composed of MAX1215EGK and resistance-capacitance components, and the A/D conversion circuit performs digital-to-analog conversion on the input signal and outputs the signal DATA1.

The digital signal processing and control circuit is composed of a digital signal processor, a clock processing circuit and a resistance-capacitance element, and the digital signal processor is used to perform digital filter processing on the 12-bit digital signal DATA1 to meet the requirements of different test conditions. Signal characteristics, performing digital filtering to output the signal DATA2; the clock processing circuit performs frequency and amplitude conversion on the input clock signal f _clk to meet the requirements of the digital signal processor.

The DDS circuit is composed of two direct frequency synthesizers AD9912 with spurious suppression channels, and the 1000MHz ultra-low noise reference signal f _ref is connected to AD9912 as a system clock after being converted from single-ended to double-ended, and the frequency control word CtrlDATA1 is generated by the CPU It is sent to the FPGA through the interface circuit, and inside the FPGA, the frequency modulation data DATA2 is added to the frequency control word CtrlDATA1 to obtain a new frequency control word CtrlDATA2 to control the output of the AD9912; among them, the frequency control word CtrlDATA1 remains unchanged after being set, and the frequency modulation data DATA2 is in Under the action of the synchronous clock, it is continuously received, and is calculated with the frequency control word CtrlDATA1, and the new frequency control word CtrlDATA2 is continuously generated. The frequency control word CtrlDATA2 continuously changes the output frequency of the AD9912 under the action of the synchronous clock. Modulation of the output frequency, the output signal f ₁ .

The phase-locked loop is used to extend the output frequency range of the DDS circuit to 1.6-2.4GHz; the phase-locked loop includes a loop filter and an integrated frequency synthesizer HMC830, and the integrated frequency synthesizer HMC830 integrates a VCO, Variable frequency divider, phase detector, charge pump; after the output signal f _of the DDS circuit passes through a bandpass filter, the filter output f2 is connected to the reference input terminal of the phase _- locked loop phase detector, and the variable divider The signal f ₃ output by the frequency converter is used for phase detection, and the error signal output by the charge pump is connected to the loop filter. The final output signal f _out of ~2.4GHz; the bandwidth of the phase-locked loop is set to 450-550kHz, and the out-of-band spurs and phase detection spurs carried by the DDS circuit are suppressed by the loop.

Using the above scheme: 1. Using analog-to-digital conversion and digital signal processing technology and DDS and PLL hybrid frequency synthesis technology can realize DC frequency modulation of tiny analog signals to broadband microwave signals. 2. The advanced DDS integrated chip is used to synthesize a higher frequency ultra-low phase noise reference signal, and the high phase detection frequency is used for phase locking, which reduces the deterioration of the phase noise of the reference signal by the phase locked loop and ensures the ultra-low frequency of the synthesized broadband signal. Low phase noise characteristics. 3. Adopt a phase-locked loop circuit with superior performance, which integrates a phase detector, a charge pump, a frequency divider, and a VCO circuit. The output frequency range of the VCO is high. signal frequency.

It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should belong to the protection scope of the appended claims of the present invention.

Claims (3)

1. a kind of broadband ultralow phase noise can direct current chirp reference source circuit, it is characterised in that being included in can direct current frequency modulation D/A converting circuit, data processing and control circuit, the DDS being sequentially connected between the input and outfan of reference source circuit is electric Road, band filter, loop filter and integrated frequency synthesizer HMC830；The integrated frequency synthesizer HMC830 with The loop filter forms phaselocked loop；The D/A converting circuit controls small modulated signal f_mTurn through D/A converting circuit Frequcny modulation data is obtained after changing, frequcny modulation data Jing data processings and control circuit control are transported with the frequency control word of DDS circuit Calculate, control the output of DDS circuit, produce the ultralow spuious transferred signal of ultralow phase noise, the transferred signal is through band logical Integrated frequency synthesizer HMC830 is sent to after wave filter, as the reference signal of phaselocked loop；The D/A converting circuit bag Include gain, bias control circuit and A/D change-over circuits；The gain, bias control circuit by difference ADC driver AD8138 and Resistance, electric capacity, inductance component are constituted, small modulated signal f_mIt is input to gain, bias control circuit, direct current biasing and amplitude It is adjusted to after the state of suitable A/D change-over circuits conversion and is input to A/D change-over circuits；The A/D change-over circuits by 1.8V, 12 Position, 250Msps analog-digital converters MAX1215EGK and Resistor-Capacitor Unit are constituted, and input signal is carried out digital-to-analogue and turned by A/D change-over circuits Change rear output signal DATA1；

The data processing and control circuit, are made up of digital signal processor, clocked processing circuits and Resistor-Capacitor Unit, the number Word signal processor is used for carrying out at digital filtering through 12 position digital signal DATA1 produced by D/A converting circuit process Reason, to meet the characteristics of signals required by different test conditions, carries out digital filtering output signal DATA2；The clock is processed Circuit is clock signal f to being input into_clkEnter line frequency and amplitude conversion, reach the use requirement for meeting digital signal processor.

2. reference source circuit as claimed in claim 1, it is characterised in that the DDS circuit is by FPGA and Direct frequency synthesizer Device AD9912 is constituted, by 1000MHz ultra-low noise reference signals f_refIt is connected to direct frequency Jing after the single-ended conversion to both-end to close AD9912 grow up to be a useful person as system clock, frequency control word CtrlDATA1 produces Jing interface circuits and delivers to FPGA by CPU, in FPGA Inside, frequcny modulation data DATA2 is added with frequency control word CtrlDATA1 and obtains new frequency control word CtrlDATA2 controls directly Connect the output of frequency synthesizer AD9912；Wherein, frequency control word CtrlDATA1 is constant after being set, and frequcny modulation data DATA2 exists Do not stop to be received under synchronised clock effect, and computing is done with frequency control word CtrlDATA1, ceaselessly produce new FREQUENCY CONTROL Word CtrlDATA2, frequency control word CtrlDATA2 do not stop to change direct synthesizer AD9912's under synchronised clock effect Output frequency, realizes the modulation to direct synthesizer AD9912 output frequencies, output signal f₁。

3. reference source circuit as claimed in claim 1, it is characterised in that the phaselocked loop is used for the output frequency to DDS circuit Rate range expansion is to 1.6～2.4GHz；The phaselocked loop includes loop filter and integrated frequency synthesizer HMC830, integrated Frequency synthesizer HMC830 be internally integrated VCO, variable frequency divider, phase discriminator, charge pump；The DDS circuit output signal f₁Jing after band filter, band filter output f₂The reference input of the phase discriminator of phaselocked loop is connected to, it is defeated with variable frequency divider The signal f for going out₃Phase demodulation is carried out, the error signal of charge pump output is connected with loop filter, and loop filter filters error letter Radio-frequency component in number, adjusts the output frequency of VCO, makes phaselocked loop obtain final output signal f of 1.6～2.4GHz_out；Institute State bandwidth of phase lock loop and be set to 450-550kHz, band stray that DDS circuit is carried and phase demodulation is spuious is suppressed by loop.