CN103647010B - A kind of preparation method of high-power LED chip - Google Patents

Abstract

The invention provides the preparation method of a kind of high-power LED chip, it is included in deposition current barrier layer, epitaxial wafer surface successively, deposits transparency conducting layer, the step going impurity removing, high annealing, making pad and electrode wires, secondary high-temperature to anneal, wherein, before the step of deposition current barrier layer, or going between impurity removing step and high-temperature annealing step, be processed luminous zone table top and make it expose N-type GaN layer and form the step in isolation road；Described making pad and electrode wires step be: by negative-working photoresist, sweep glue, deposit, the mode such as stripping makes P-type electrode pad, N-type electrode pad, P-type electrode line and N-type electrode line, described P-type electrode line is distributed only over p-type GaN layer surface, on transparency conducting layer.The present invention abandons P-type electrode line and occupies isolation road and the structure on p-type GaN layer surface simultaneously, only allows P electrode line be arranged on core particles surface, is narrowed in isolation road, and width reduces to original 1/3rd, increases light-emitting area, is greatly improved luminosity.

Description

A kind of manufacturing method of high-power LED chip

technical field

The invention relates to the field of LED device production, in particular to a manufacturing method for improving the brightness of a high-power array LED chip.

Background technique

With the vigorous development of the third-generation semiconductor technology, semiconductor lighting has become the focus of social development due to its advantages of energy saving, environmental protection, high brightness, and long life. GaN-based LED chips are the "power" of semiconductor lighting. In recent years, the performance has been greatly improved, and the production cost has been continuously reduced, making outstanding contributions to the entry of semiconductor lighting into thousands of households.

In semiconductor lighting technology, GaN-based blue LED chip manufacturing and packaged blue LED excitation phosphor to obtain white light are the core technologies of its lighting. Reducing chip manufacturing and packaging costs and process difficulty is one of the key factors for the popularization of semiconductor lighting.

Traditional power LED lamp beads (such as 1W, 3W, 5W, 10W, etc.) are mostly obtained by packaging multiple power chips in a suitable series and parallel form in a bracket with its own circuit structure. This way the final drive current Small, but the voltage at both ends of the lamp bead is high, and the requirements for packaging technology are very high. When connecting in series and parallel, there are many wires. Not only the process is complicated, but also the reliability is difficult to guarantee, and the cost is relatively high.

In an ordinary array chip, array circuit connections are implemented inside the chip, which has good electrical performance, saves cost and improves yield. However, since the P-type electrode line occupies both the P-GaN surface and the isolation channel (the isolation channel is formed by etching the P-type GaN to achieve the effect of shunting and increase the light extraction efficiency), the resulting small light-emitting area results in low luminous brightness. .

Contents of the invention

The purpose of the present invention is to provide a manufacturing method for improving the luminous brightness of a high-power array LED chip, so as to solve the technical problem of low luminous brightness of the existing array chip.

In order to achieve the above object, the present invention provides a method for manufacturing a high-power LED chip, which sequentially includes the steps of depositing a current blocking layer on the surface of an epitaxial wafer, depositing a transparent conductive layer, removing impurities, high-temperature annealing, and making pads and electrode lines. ,in,

The step of depositing the current blocking layer is: depositing the current blocking layer under the P-type pad area and the position of the P-type electrode line, and the current blocking layer is transparent in the range of 440-720nm;

Before the step of depositing the current blocking layer, or between the step of removing impurities and the step of high-temperature annealing, the step of processing the mesa of the light-emitting region to expose the N-type GaN layer and forming the isolation channel;

The step of removing impurities is: removing conductive substances in the N-type pad area, the N-type electrode line groove and the P-type pad area;

The high-temperature annealing step is as follows: at a heating rate of 10-20°C/min and a nitrogen atmosphere of 8-13slm/min at the same time, the temperature is raised to 540-580°C, and the temperature is kept constant for 5-8min to make the transparent conductive layer more dense, and with A good ohmic contact is formed between the P-type GaN layers;

The step of making pads and electrode lines is: making P-type electrode pads, N-type electrode pads, P-type electrode lines and N-type electrode lines by means of negative photolithography, sweeping, deposition, and stripping. The P-type electrode lines are only distributed on the surface of the P-type GaN layer and on the transparent conductive layer.

Preferably, the method for processing the mesa of the light-emitting region includes the steps of photolithography, inductively coupled plasma etching or wet etching, and glue removal and cleaning.

Preferably, the method for depositing the current blocking layer is plasma enhanced chemical vapor deposition.

Preferably, the method for depositing the transparent conductive layer is magnetron sputtering deposition or electron beam evaporation deposition.

Preferably, after the second high temperature annealing step, depositing a passivation layer is also included to expose the P-type pad and the N-type pad.

Preferably, the method for depositing the passivation layer includes plasma-enhanced chemical vapor deposition or ion source-assisted deposition, followed by steps of photolithography, wet etching or dry etching, and gel removal and cleaning.

Preferably, the current blocking layer is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide.

Preferably, the transparent conductive layer is any one of indium tin oxide, nickel gold oxide or doped zinc oxide.

Preferably, after the pads and electrode wires are made, a secondary high-temperature annealing step is performed to make the P-type electrode wires and the transparent conductive layer, the P-type electrode pads and the insulating isolation layer, the N-type electrode wires and the N-type electrode pads A good ohmic contact is formed with the GaN layer.

The present invention has the following beneficial effects: the present invention abandons the structure that the P-type electrode wires occupy the isolation channel and the surface of the P-type GaN layer at the same time, and only allows the P-type electrode lines to be arranged on the surface of the core particle, so that the isolation channel is narrowed and the width is reduced to the original three one-third. In the first embodiment, in step 2, a narrow isolation channel is made by photolithography and etching, and in step 7, the P-type electrode line is arranged at the edge position of the surface of the P-type GaN layer; In the isolation channel, in step 7, the P-type electrode line is arranged on the edge of the surface of the P-type GaN layer, and the remaining two-thirds of the area occupied by the isolation channel is restored to the light-emitting area, which greatly improves the luminous brightness.

The method of the invention is simple in operation and obvious in effect, and the luminous intensity of the manufactured chip is 8-12% higher than that of the same-area high-power array chip manufactured by the traditional method.

In addition to the objects, features and advantages described above, the present invention has other objects, features and advantages. Hereinafter, the present invention will be described in further detail with reference to the drawings.

Description of drawings

The accompanying drawings constituting a part of this application are used to provide further understanding of the present invention, and the schematic embodiments and descriptions of the present invention are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:

Fig. 1 is a schematic cross-sectional view of a chip structure of a preferred embodiment of the present invention;

Fig. 2 is a schematic top view of a chip structure of a preferred embodiment of the present invention;

Among them, 1. Substrate; 2. N-type GaN layer; 3. Multi-quantum well layer in active region; 4. P-type GaN layer; 5. Current blocking layer; 6. Transparent conductive layer; 7. P-type electrode line; 8. N-type electrode line; 9. Passivation layer; 10. Isolation road; 71. P-type pad; 81. N-type pad.

detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention can be implemented in various ways defined and covered by the claims.

Referring to Fig. 1 and Fig. 2, the epitaxial wafer of GaN-based LED epitaxial structure taken in the following examples, the epitaxial wafer structure includes substrate 1, N-type GaN layer 2, active region multi-quantum well layer 3, P-type GaN layer 4 .

Embodiment one

1. Thoroughly clean the epitaxial wafer, which is an epitaxial wafer with a GaN-based light-emitting diode chip structure grown on a PSS sapphire substrate;

2. Manufacture the mesa of the light-emitting area of all chip units contained in a single core particle through steps such as yellow light lithography, inductively coupled plasma (ICP) etching, and glue removal cleaning, exposing the N-type GaN layer 2, and the grooves form isolation channels 10, and make as narrow a trench as possible (isolation channel 10) through yellow light lithography, the number of multi-quantum well layers etched away is reduced, the P-type GaN area is restored, the light-emitting area is increased, and the brightness is improved;

3. After cleaning, use plasma-enhanced chemical vapor deposition (PECVD) to deposit the current blocking layer 5. The material of the current blocking layer is Si ₂ N ₂ O. After steps such as photolithography, wet etching, and degumming cleaning, it is used for layout The positions of the P-type electrode lines 7 and the P-type pads 71 are covered by the current blocking layer 5 to avoid electric leakage;

4. Deposit the transparent conductive layer 6. The material of the transparent conductive layer 6 is indium tin oxide (ITO), and the etching method is wet etching; the deposition method is magnetron sputtering (Sputter) deposition;

5. Remove the conductive substances in the N-type electrode lines, N-type pads, and P-type pads through steps such as yellow light lithography and wet etching;

6. Perform high-temperature annealing on the wafer to form a good ohmic contact between the transparent conductive layer 6 and the P-type GaN layer 4; the annealing method is rapid annealing (RTA) under a nitrogen and oxygen atmosphere;

7. Make P-type electrode pads 71, N-type electrode pads 81, and P-type electrode lines 7 and N-type electrode lines 8 by means of negative photolithography, glue sweeping, deposition, and stripping, and make the P-type electrode lines 7 and N-type electrode lines 8 through yellow light lithography. Type electrode lines 7 are only distributed on the edge of the surface of the P-type GaN layer;

8. Perform secondary high-temperature annealing on the wafer to make the P-type electrode wire 7 and the transparent conductive layer 6, the P-type electrode pad 71 and the insulating isolation layer 5, the N-type electrode wire 8 and the N-type electrode pad 81 and the GaN layer 2 Good ohmic contact is formed between them; the annealing method is furnace tube annealing;

9. After cleaning, use plasma enhanced chemical vapor deposition (PECVD) to deposit passivation layer 9, the material of passivation layer 9 is silicon oxide (SiO ₂ ), and go through steps such as yellow photolithography, dry etching, degumming and cleaning Expose the P and N type electrode pads.

The size of a high-power array GaN-based light-emitting diode chip is 112mil×208mil. It is composed of 208 traditional GaN-based LED chips. Capability (ESD performance), reverse voltage, turn-on voltage and other parameters are all excellent, especially in terms of luminous intensity, compared with the same area of high-power array chip P-type electrode lines produced by traditional methods at the same time fabricated on P-type GaN The luminous intensity of the upper surface and the groove is 12% higher, and it can be seen from the mapping of spot measurement that the comprehensive yield rate of on-chip production reaches 91.38%.

Embodiment two

1. Thoroughly clean the epitaxial wafer, which is an epitaxial wafer with a GaN-based light-emitting diode chip structure grown on a PSS sapphire substrate;

2. After cleaning, use plasma-enhanced chemical vapor deposition (PECVD) to deposit the current blocking layer 5. The material of the current blocking layer is SiN, and after steps such as photolithography, wet etching, and degumming cleaning, it is used for laying P-type electrode lines 7 and the position of the P-type pad 71 are covered with the current blocking layer 5;

3. Deposit the transparent conductive layer 6, the material of the transparent conductive layer 6 is nickel gold (NiAu), the etching method is wet etching; the deposition method is electron beam evaporation deposition;

4. Remove the conductive substances in the N-type electrode lines, N-type pads, and P-type pads through steps such as yellow light lithography and wet etching;

5. Next, use steps such as photolithography, inductively coupled plasma (ICP) etching, wet etching, glue removal and cleaning to manufacture the light-emitting area mesa of all chip units contained in a single core particle, exposing the N-type GaN layer 2 and Groove, and make the groove as narrow as possible by yellow light lithography, the number of multi-quantum well layers etched away is reduced, the P-type GaN area is restored, the light-emitting area is increased, and the brightness is improved;

6. Perform high-temperature annealing on the wafer, annealing in an oxygen atmosphere in an annealing furnace, so that a good ohmic contact is formed between the transparent conductive layer 6 and the P-type GaN layer 4;

7. Make P-type electrode pads 71, N-type electrode pads 81, and P-type electrode lines 7 and N-type electrode lines 8 by means of negative photolithography, glue sweeping, deposition, and stripping, and make the P-type electrode lines 7 and N-type electrode lines 8 through yellow light lithography. Type electrode lines 7 are only distributed on the edge of the surface of the P-type GaN layer;

8. Perform secondary high-temperature annealing on the wafer to make the P-type electrode wire 7 and the transparent conductive layer 6, the P-type electrode pad 71 and the insulating isolation layer 5, the N-type electrode wire 8 and the N-type electrode pad 81 and the GaN layer 2 A good ohmic contact is formed between them; the annealing method is furnace tube nitrogen atmosphere annealing;

9. After cleaning, the passivation layer 9 is deposited by plasma enhanced chemical vapor deposition (PECVD). The material of the passivation layer 9 is silicon oxynitride, and P and N are exposed through steps such as yellow photolithography, wet etching, and degumming cleaning. type electrode pads.

The size of an arrayed high-power GaN-based LED chip is 34mil×45mil. It is composed of 18 traditional GaN-based LED chips in an array structure. The 18 light-emitting units emit light evenly, and the chip voltage, leakage, and antistatic Capability (ESD performance), reverse voltage, turn-on voltage and other parameters are all excellent, especially in terms of luminous intensity, which is 8.7% higher than that of high-power array chips with the same area produced by traditional methods. And it can be seen from the mapping of spot measurement that the comprehensive yield rate of on-chip production reaches 93.87%.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (9)

1. the preparation method of a high-power LED chip, it is characterised in that be included in the deposition current resistance of epitaxial wafer surface successively Barrier, deposit transparency conducting layer, go impurity removing, high annealing, making pad and the step of electrode wires, wherein,

Described deposition current barrier layer step is: deposition current barrier layer below the position of p-type welding disking area and P-type electrode line, Described current barrier layer is transparent in the range of 440-720nm；

Before the step of deposition current barrier layer, or going between impurity removing step and high-temperature annealing step, be processed luminescence District's table top makes it expose N-type GaN layer and form the step in isolation road；The width in isolation road is original 1/3rd；

Described remove impurity removing step be: remove N-type pad area, N-type electrode line trenches and the conductive materials of p-type pad area；

Described high-temperature annealing step is: under the heating rate of 10-20 DEG C/min, the nitrogen atmosphere of 8-13slm/min simultaneously, rise To 540-580 DEG C, constant temperature 5-8min, make transparency conducting layer finer and close, and and p-type GaN layer between form good Europe Nurse contacts；

Described making pad and electrode wires step be: by negative-working photoresist, sweep glue, deposit, stripping mode makes P-type electrode and welds Dish, N-type electrode pad, P-type electrode line and N-type electrode line, described P-type electrode line is distributed only over p-type GaN layer Surface Edge Edge, on transparency conducting layer.

The preparation method of a kind of high-power LED chip the most according to claim 1, it is characterised in that described processing is sent out The method of light district table top includes gold-tinted photoetching, inductively coupled plasma etching or wet etching, remove photoresist cleaning step.

The preparation method of a kind of high-power LED chip the most according to claim 1, it is characterised in that described deposition electricity The method of flow barrier is plasma enhanced chemical vapor deposition method.

The preparation method of a kind of high-power LED chip the most according to claim 1, it is characterised in that described deposition is saturating The method of bright conductive layer is magnetron sputtering deposition or electron-beam evaporation.

The preparation method of a kind of high-power LED chip the most according to claim 1, it is characterised in that making pad With include after electrode wires step second time high-temperature annealing step；After second time high-temperature annealing step, also include deposit passivation layer, Expose p-type pad and N-type pad.

The preparation method of a kind of high-power LED chip the most according to claim 5, it is characterised in that described deposition is blunt The method changing layer includes plasma enhanced chemical vapor deposition method or ion source assisted, and through photoetching, wet etching Or dry etching, remove photoresist cleaning step.

7. according to the preparation method of a kind of high-power LED chip described in any one of claim 1 to 6, it is characterised in that Described current barrier layer is silicon nitride, silica, silicon oxynitride, aluminum oxide.

8. according to the preparation method of a kind of high-power LED chip described in any one of claim 1 to 6, it is characterised in that Described transparency conducting layer is any one in tin indium oxide, nickel oxide gold or doping zinc-oxide.

9. according to the preparation method of a kind of high-power LED chip described in any one of claim 1 to 6, it is characterised in that After having made pad and electrode wires, carry out second time high-temperature annealing step, make P-type electrode line and transparency conducting layer, P-type electrode Good Ohmic contact is formed between pad and dielectric isolation layer, N-type electrode line and N-type electrode pad and GaN layer.