CN103646938B - Once first plate and lose metal frame subtraction afterwards and bury flip-chip bump structure and process - Google Patents
Once first plate and lose metal frame subtraction afterwards and bury flip-chip bump structure and process Download PDFInfo
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- 238000003486 chemical etching Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 4
- 239000008393 encapsulating agent Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 3
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- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明涉及一种一次先镀后蚀金属框减法埋芯片倒装凸点结构及工艺方法,其特征在于所述结构包括金属基板框,在所述金属基板框内部设置有基岛和引脚,所述基岛的背面和引脚的台阶面通过底部填充胶倒装有芯片,所述基岛外围的区域、基岛和引脚之间的区域、引脚与引脚之间的区域、基岛和引脚上部的区域、基岛和引脚下部的区域以及芯片外均包封有塑封料,在所述金属基板框的表面被覆抗氧化剂,所述塑封料与金属基板框上下表面的被覆抗氧化剂(OSP)齐平,在所述引脚背面设置有金属球。本发明能够解决传统金属引线框的板厚之中无法埋入物件而限制金属引线框的功能性和应用性能。
The present invention relates to a metal frame subtractive embedding chip flip-chip bump structure and process method, which is characterized in that the structure includes a metal substrate frame, and base islands and pins are arranged inside the metal substrate frame. The back side of the base island and the stepped surface of the pins are flipped with chips through the underfill glue, the area around the base island, the area between the base island and the pins, the area between the pins, the base The area above the island and the pins, the area below the base island and the pins, and the outside of the chip are encapsulated with a plastic compound, and the surface of the metal substrate frame is coated with an antioxidant, and the plastic compound and the coating on the upper and lower surfaces of the metal substrate frame The antioxidant (OSP) is flush with metal balls placed on the back of the pins. The invention can solve the problem that the thickness of the traditional metal lead frame cannot embed objects and limit the functionality and application performance of the metal lead frame.
Description
技术领域 technical field
本发明涉及一种一次先镀后蚀金属框减法埋芯片倒装凸点结构及其工艺方法。属于半导体封装技术领域。 The invention relates to a metal frame subtractive embedded chip flip-chip bump structure and a process method thereof. It belongs to the technical field of semiconductor packaging.
背景技术 Background technique
传统的四面扁平无引脚金属引线框结构主要有两种: There are two main types of conventional four-sided flat leadless metal leadframe structures:
一种是四面扁平无引脚封装(QFN)引线框,这种结构的引线框由铜材金属框架与耐高温胶膜组成(如图14所示)。 One is the four-sided flat no-lead package (QFN) lead frame. The lead frame of this structure is composed of a copper metal frame and a high-temperature resistant adhesive film (as shown in Figure 14).
一种是预包封四面扁平无引脚封装(pQFN)引线框,这种结构的引线框结构包括引脚与基岛,引脚与基岛之间的蚀刻区域填充有塑封料(如图15所示)。 One is a pre-encapsulated four-sided flat no-lead package (pQFN) lead frame. The lead frame structure of this structure includes pins and base islands, and the etched area between the pins and the base island is filled with plastic encapsulant (Figure 15 shown).
上述传统金属引线框存在以下缺点: The above conventional metal lead frame has the following disadvantages:
1、传统金属引线框作为装载芯片的封装载体,本身不具备系统功能,从而限制了传统金属引线框封装后的集成功能性与应用性能; 1. The traditional metal lead frame, as the packaging carrier for loading chips, does not have system functions, which limits the integrated functionality and application performance of the traditional metal lead frame after packaging;
2、由于传统金属引线框本身不具备系统功能,只能在引线框正面进行芯片及组件的平铺或者堆叠封装。而功率器件与控制芯片封装在同一封装体内,功率器件的散热会影响控制芯片信号的传输; 2. Since the traditional metal lead frame itself does not have system functions, chips and components can only be tiled or stacked on the front of the lead frame. While the power device and the control chip are packaged in the same package, the heat dissipation of the power device will affect the transmission of the signal of the control chip;
3、由于传统金属引线框本身不具备系统功能,所以多功能系统集成模块只能在传统金属引线框正面通过多芯片及组件的平铺或堆叠而实现,相应地也就增大元器件模块在PCB上所占用的空间。 3. Since the traditional metal lead frame itself does not have system functions, the multi-functional system integration module can only be realized by tiling or stacking multiple chips and components on the front of the traditional metal lead frame, which correspondingly increases the number of component modules in the system. space occupied on the PCB.
发明内容 Contents of the invention
本发明的目的在于克服上述不足,提供一种一次先镀后蚀金属框减法埋芯片倒装凸点结构及其方法,它能够解决传统金属引线框缺乏系统功能的问题。 The object of the present invention is to overcome the above-mentioned disadvantages, and provide a flip-chip bump structure and method thereof, which can solve the problem of lack of system functions in traditional metal lead frames.
本发明的目的是这样实现的:一种一次先镀后蚀金属框减法埋芯片倒装凸点结构的制作方法,所述方法包括如下步骤: The object of the present invention is achieved like this: a kind of manufacturing method of metal frame subtractive buried chip flip-chip bump structure after plating first, described method comprises the following steps:
步骤一、取金属基板 Step 1. Take the metal substrate
步骤二、贴光阻膜作业 Step 2. Paste photoresist film
在金属基板的正面及背面分别贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the front and back of the metal substrate;
步骤三、金属基板表面去除部分光阻膜 Step 3. Remove part of the photoresist film from the surface of the metal substrate
利用曝光显影设备将步骤二完成贴光阻膜作业的金属基板表面进行图形曝光、显影与去除部分图形光阻膜; Use the exposure and development equipment to expose, develop and remove part of the patterned photoresist film on the surface of the metal substrate that has completed the photoresist film pasting operation in step 2;
步骤四、被覆抗氧化剂(OSP) Step 4: Coating Antioxidant (OSP)
在步骤三中金属基板表面去除部分光阻膜的区域内进行被覆抗氧化剂(OSP),防止金属氧化,如金、镍金、镍钯金、锡。 In step 3, the area where part of the photoresist film is removed from the surface of the metal substrate is coated with an antioxidant (OSP) to prevent metal oxidation, such as gold, nickel gold, nickel palladium gold, and tin.
步骤五、去除光阻膜 Step 5. Remove the photoresist film
去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;
步骤六、贴光阻膜作业 Step 6. Paste photoresist film
在金属基板的表面贴上可进行曝光显影的光阻膜; Paste a photoresist film that can be exposed and developed on the surface of the metal substrate;
步骤七、金属基板表面去除部分光阻膜 Step 7. Remove part of the photoresist film from the surface of the metal substrate
利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板表面进行图形曝光、显影与去除部分图形光阻膜,具体是去除被覆抗氧化剂(OSP)以外的光阻膜,以露出金属基板背面后续需要进行蚀刻的区域图形; Use exposure and development equipment to expose, develop and remove part of the patterned photoresist film on the surface of the metal substrate that has been pasted with the photoresist film in step 6, specifically remove the photoresist film other than the coated antioxidant (OSP) to expose the back of the metal substrate The pattern of the area that needs to be etched later;
步骤八、化学蚀刻 Step 8. Chemical etching
在步骤七中金属基板表面去除部分光阻膜的区域内进行不同深度的化学蚀刻,化学蚀刻完成后即形成相对应的基岛和台阶状引脚; Chemical etching of different depths is carried out in the area where part of the photoresist film is removed from the surface of the metal substrate in step 7. After the chemical etching is completed, the corresponding base island and stepped pins are formed;
步骤九、去除光阻膜 Step 9. Remove the photoresist film
去除金属基板表面的光阻膜; Remove the photoresist film on the surface of the metal substrate;
步骤十、装片 Step ten, loading film
在步骤九的基岛背面和引脚台阶面将已完成表面有凸点的芯片进行倒装,完成后并通过底部填充胶进行底部填充保护; On the back of the base island and the step surface of the pins in step 9, flip the completed chip with bumps on the surface, and protect the underfill with underfill glue after completion;
步骤十一、包封 Step 11. Encapsulation
对步骤十的金属基板内部采用塑封料进行塑封,塑封料与金属基板的正面和背面均齐平。 The inside of the metal substrate in step ten is plastic-sealed with a plastic sealing compound, and the plastic sealing compound is flush with the front and back of the metal substrate.
步骤十二、植球 Step 12. Planting the ball
在步骤十一的引脚背面植入金属球。 Implant metal balls on the back of the pins in step eleven.
当步骤四中的抗氧化金属层为镍金或镍钯金时,所述步骤六和步骤七可以省略。 When the anti-oxidation metal layer in step four is nickel-gold or nickel-palladium-gold, the steps six and seven can be omitted.
一种一次先镀后蚀金属框减法埋芯片倒装凸点结构,它包括金属基板框,在所述金属基板框内部设置有基岛和引脚,所述引脚呈台阶状,所述基岛和引脚的正面与金属基板框正面齐平,所述引脚的背面与金属基板框的背面齐平,所述基岛背面与引脚的台阶面齐平,所述基岛的背面通过底部填充胶倒装有芯片,所述基岛外围的区域、基岛和引脚之间的区域、引脚与引脚之间的区域、基岛和引脚上部的区域、基岛和引脚下部的区域以及芯片外均包封有塑封料,在所述基岛正面、引脚的正面和背面以及金属基板框的表面被覆抗氧化剂(OSP),所述塑封料与金属基板框上下表面的被覆抗氧化剂(OSP)齐平,在所述引脚的正面设置有金属球。 A flip-chip bump structure of first-plating and later-etching metal frame subtractive buried chip, which includes a metal substrate frame, a base island and pins are arranged inside the metal substrate frame, the pins are stepped, and the base The front of the island and the pin is flush with the front of the metal substrate frame, the back of the pin is flush with the back of the metal substrate frame, the back of the base island is flush with the stepped surface of the pin, and the back of the base island passes through The underfill is flip-chip, the area around the base island, the area between the base island and the pins, the area between the pins, the area above the base island and the pins, the base island and the pins The area of the lower part and the outside of the chip are all encapsulated with a molding compound, and the front side of the base island, the front and back sides of the pins, and the surface of the metal substrate frame are coated with antioxidant (OSP), and the molding compound and the upper and lower surfaces of the metal substrate frame Antioxidant coated (OSP) flush with metal balls placed on the front side of the pins.
在所述基岛背面和引脚的台阶面上被覆抗氧化剂。 Antioxidant is coated on the back of the base island and the stepped surface of the pin.
与现有技术相比,本发明具有以下有益效果: Compared with the prior art, the present invention has the following beneficial effects:
1、金属减法技术引线框架的夹层可以因为系统与功能的需要而在需要的位置或是区域内埋入主动元件或是组件或是被动的组件,成为一个单层线路系统级的金属引线框架; 1. The interlayer of the metal subtraction technology lead frame can embed active components or components or passive components in the required position or area due to the needs of the system and functions, and become a single-layer line system-level metal lead frame;
2、从金属减法技术引线框架成品的外观完全看不出来内部夹层已埋入了因系统或是功能需要的对象,尤其是硅材的芯片的埋入连X光都无法检视,充分达到系统与功能的隐密性及保护性; 2. From the appearance of the finished lead frame of metal subtraction technology, it is completely impossible to see that the internal interlayer has been embedded with objects required by the system or function, especially the embedding of silicon chips that cannot be inspected even by X-rays, which fully meets the requirements of the system and Confidentiality and protection of functions;
3、金属减法技术引线框架的夹层在制作过程中可以埋入高功率器件,二次封装再进行控制芯片的装片,从而高功率器件与控制芯片分别装在金属减法技术引线框两侧,可以避免高功率器件因热辐射而干扰控制芯片的信号传输。 3. The interlayer of the metal subtraction technology lead frame can be embedded with high-power devices during the production process, and then the control chip is mounted after secondary packaging, so that the high-power device and the control chip are respectively installed on both sides of the metal subtraction technology lead frame, which can Avoid high-power devices from interfering with the signal transmission of the control chip due to heat radiation.
4、金属减法技术引线框架本身内含埋入对象的功能,二次封装后可以充分实现系统功能的集成与整合,从而同样功能的元器件模块的体积尺寸要比传统引线框封装的模块来的小,相应在PCB上所占用的空间也就比较少,从而也就降低了成本。 4. Metal subtraction technology The lead frame itself contains the function of embedded objects, and the integration and integration of system functions can be fully realized after secondary packaging, so that the volume size of the component module with the same function is smaller than that of the traditional lead frame packaged module. Small, the corresponding space occupied on the PCB is relatively small, which also reduces the cost.
5、金属减法技术引线框架的夹层在制作过程中可以因为导热或是散热需要而在需要的位置或是区域内埋入导热或是散热对象,从而改善整个封装结构的散热效果; 5. The metal subtraction technology lead frame interlayer can embed heat conduction or heat dissipation objects in the required position or area due to heat conduction or heat dissipation requirements during the production process, thereby improving the heat dissipation effect of the entire package structure;
6、金属减法技术引线框架成品本身就富含了各种的组件,如果不再进行后续第二次封装的情况下,将金属减法技术引线框架依照每一格单元切开,本身就可成为一个超薄的封装体或是简易型系统级封装体; 6. The finished metal subtraction technology lead frame itself is rich in various components. If the subsequent second packaging is not carried out, the metal subtraction technology lead frame is cut according to each cell, and it can become a Ultra-thin package or simple system-in-package;
7、金属减法技术引线框架除了本身内含对象的埋入功能之外还可以在封装体外围再叠加不同的单元封装或是系统级封装,充分达到单层线路金属引线框架的双系统或是多系统级的封装技术能力。 7. Metal subtraction technology In addition to the embedded function of the embedded object, the lead frame can also be superimposed with different unit packages or system-level packages on the periphery of the package, fully achieving the dual system or multi-system of single-layer metal lead frames. System-level packaging technology capabilities.
8、金属减法技术引线框架内所埋入的物件或对象均与金属厚度齐平,充分的体现出超薄与高密度的填充在金属减法技术引线框内的厚度空间之中。 8. The objects or objects embedded in the metal subtraction technology lead frame are all flush with the metal thickness, which fully reflects the ultra-thin and high-density filling in the thickness space in the metal subtraction technology lead frame.
附图说明 Description of drawings
图1~图12为本发明一次先镀后蚀金属框减法埋芯片倒装凸点结构的工艺方法的各工序示意图。 Figures 1 to 12 are schematic diagrams of each process of the process method of first plating first and then etching the metal frame subtractive embedded chip flip-chip bump structure of the present invention.
图13为本发明一次先镀后蚀金属框减法埋芯片倒装凸点结构的示意图。 FIG. 13 is a schematic diagram of a flip-chip bump structure of a metal frame subtractive buried chip in a method of plating first and then etching in accordance with the present invention.
图14为传统四面扁平无引脚封装(QFN)引线框结构的示意图。 FIG. 14 is a schematic diagram of a conventional quad flat no-leads (QFN) lead frame structure.
图15为预包封四面扁平无引脚封装(pQFN)引线框结构的示意图。 Figure 15 is a schematic diagram of the lead frame structure of a pre-encapsulated quad flat no-lead package (pQFN).
其中: in:
金属基板框1 Metal Substrate Frame 1
基岛2 Key Island 2
引脚3 pin 3
底部填充胶4 Underfill 4
芯片5 chip 5
塑封料6 Plastic compound 6
被覆抗氧化剂7 Coated Antioxidant 7
金属球8。 metal ball 8.
具体实施方式 detailed description
本发明一种一次先镀后蚀金属框减法埋芯片倒装凸点结构的工艺方法如下: The process method of the present invention is a metal frame subtractive embedded chip flip-chip bump structure as follows:
步骤一、取金属基板 Step 1. Take the metal substrate
参见图1,取一片厚度合适的金属基板,此板材的材质主要是以金属材料为主,而金属材料的材质可以是铜材﹑铁材﹑镀锌材﹑不锈钢材﹑铝材或可以达到导电功能的金属物质或非全金属物质等,厚度的选择可依据产品特性进行选择。 See Figure 1, take a piece of metal substrate with appropriate thickness, the material of this plate is mainly metal material, and the material of metal material can be copper, iron, galvanized, stainless steel, aluminum or can achieve electrical conductivity Functional metal substances or non-all-metal substances, etc., the choice of thickness can be selected according to product characteristics.
步骤二、贴光阻膜作业 Step 2. Paste photoresist film
参见图2,在金属基板的正面及背面分别贴上可进行曝光显影的光阻膜,以保护后续的蚀刻工艺作业,光阻膜可以是干式光阻膜也可以是湿式光阻膜。 Referring to Figure 2, a photoresist film that can be exposed and developed is attached to the front and back of the metal substrate to protect the subsequent etching process. The photoresist film can be a dry photoresist film or a wet photoresist film.
步骤三、金属基板表面去除部分光阻膜 Step 3. Remove part of the photoresist film from the surface of the metal substrate
参见图3,利用曝光显影设备将步骤二完成贴光阻膜作业的金属基板表面(正面和背面)进行图形曝光、显影与去除部分图形光阻膜,以露出金属基板表面后续需要进行电镀的区域图形。 Referring to Figure 3, use the exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the metal substrate surface (front and back) that has completed the photoresist film pasting operation in step 2, so as to expose the area that needs to be electroplated on the metal substrate surface graphics.
步骤四、被覆抗氧化剂(OSP) Step 4: Coating Antioxidant (OSP)
参见图4,在步骤三中金属基板表面去除部分光阻膜的区域内进行被覆抗氧化剂(OSP),防止金属氧化,如金、镍金、镍钯金、锡。 Referring to FIG. 4 , coating antioxidant (OSP) is carried out in the area where part of the photoresist film is removed from the surface of the metal substrate in step 3 to prevent metal oxidation, such as gold, nickel gold, nickel palladium gold, and tin.
步骤五、去除光阻膜 Step 5. Remove the photoresist film
参见图5,去除金属基板表面的光阻膜,去除光阻膜的方法可采用化学药水软化并采用高压水冲洗的方式去除光阻膜。 Referring to FIG. 5 , the photoresist film on the surface of the metal substrate is removed. The method of removing the photoresist film can be softened with chemical potions and washed with high-pressure water to remove the photoresist film.
步骤六、贴光阻膜作业 Step 6. Paste photoresist film
参见图6,在金属基板的表面贴上可进行曝光显影的光阻膜,以保护后续的蚀刻工艺作业,光阻膜可以是干式光阻膜也可以是湿式光阻膜。 Referring to FIG. 6 , a photoresist film that can be exposed and developed is pasted on the surface of the metal substrate to protect the subsequent etching process. The photoresist film can be a dry photoresist film or a wet photoresist film.
步骤七、金属基板表面去除部分光阻膜 Step 7. Remove part of the photoresist film from the surface of the metal substrate
参见图7,利用曝光显影设备将步骤六完成贴光阻膜作业的金属基板表面进行图形曝光、显影与去除部分图形光阻膜,具体是去除被覆抗氧化剂(OSP)以外的光阻膜,以露出金属基板背面后续需要进行蚀刻的区域图形。 Referring to Fig. 7, use the exposure and development equipment to expose, develop and remove part of the photoresist film on the surface of the metal substrate that has completed the photoresist film pasting operation in step 6, specifically to remove the photoresist film other than the coated antioxidant (OSP), so as to Exposing the pattern of the area on the back of the metal substrate that needs to be etched later.
步骤八、化学蚀刻 Step 8. Chemical etching
参见图8,在步骤七中金属基板表面去除部分光阻膜的区域内进行不同深度的化学蚀刻,化学蚀刻完成后即可形成相应的基岛和台阶状引脚,蚀刻药水可以采用氯化铜或是氯化铁或是可以进行金属材质化学蚀刻的药水或技术。 Referring to Figure 8, chemical etching of different depths is carried out in the area where part of the photoresist film is removed from the surface of the metal substrate in step 7. After the chemical etching is completed, the corresponding base island and stepped pins can be formed. The etching solution can be copper chloride. Either ferric chloride or a potion or technique that chemically etches metal.
步骤九、去除光阻膜 Step 9. Remove the photoresist film
参见图9,去除金属基板表面的光阻膜,去除光阻膜的方法可采用化学药水软化并采用高压水冲洗的方式去除光阻膜。 Referring to FIG. 9 , the photoresist film on the surface of the metal substrate is removed. The method of removing the photoresist film can be softened with chemical potions and washed with high-pressure water to remove the photoresist film.
步骤十、装片 Step ten, loading film
参见图10,在步骤九的基岛背面和引脚台阶面将已完成表面有凸点的芯片进行倒装,完成后并通过底部填充胶进行底部填充保护。 Referring to FIG. 10 , flip-chip the completed chip with bumps on the back of the base island and the step surface of the pins in step 9, and perform underfill protection with underfill glue after completion.
为了防止金属基板氧化影响芯片与基板之间的电性互联以及倒装时的锡扩散,因此在步骤十装片之前可先在金属基板表面裸露的金属表面进行被覆抗氧化剂。 In order to prevent the oxidation of the metal substrate from affecting the electrical interconnection between the chip and the substrate and the tin diffusion during flip-chip, the exposed metal surface of the metal substrate surface can be coated with an antioxidant before step ten.
步骤十一、包封 Step 11. Encapsulation
参见图11,对步骤十的金属基板内部采用塑封料进行塑封,塑封料与金属基板上下表面的被覆抗氧化剂(OSP)齐平,塑封方式可以采用模具灌胶方式、喷涂方式、刷胶方式或是贴膜方式,所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。 Referring to Figure 11, the inside of the metal substrate in step 10 is plastic-sealed with a plastic sealing compound. The plastic sealing compound is flush with the coating antioxidant (OSP) on the upper and lower surfaces of the metal substrate. The plastic sealing method can be mold filling, spraying, brushing or It is a film-pasting method, and the molding compound can be epoxy resin with filler or no filler.
步骤十二、植球 Step 12. Planting the ball
参见图12,在步骤十五的引脚背面植入金属球,植球的方式可以是直接植入金属球也可以是采用掩模板(MASK)刷入金属膏,再经过高温回流而行成金属球。 Referring to Figure 12, metal balls are implanted on the back of the pins in Step 15. The ball planting method can be directly implanted with metal balls or brushed with metal paste using a mask (MASK), and then reflowed at high temperature to form a metal ball. ball.
参见图13,为本发明一种一次先镀后蚀金属框减法埋芯片倒装凸点结构的结构示意图,它包括金属基板框1,在所述金属基板框1内部设置有基岛2和引脚3,所述引脚3呈台阶状,所述基岛2和引脚3的正面与金属基板框1正面齐平,所述引脚3的背面与金属基板框1的背面齐平,所述基岛2背面与引脚3的台阶面齐平,所述基岛2的背面通过底部填充胶4倒装有芯片5,所述基岛2外围的区域、基岛2和引脚3之间的区域、引脚3与引脚3之间的区域、基岛2和引脚3上部的区域、基岛2和引脚3下部的区域以及芯片外均包封有塑封料6,在所述基岛2正面、引脚3的正面和背面以及金属基板框1的表面被覆抗氧化剂(OSP)7,所述塑封料6与金属基板框1上下表面的被覆抗氧化剂(OSP)7齐平,在所述引脚3的正面设置有金属球8。 Referring to FIG. 13 , it is a structural schematic diagram of a metal frame subtractive embedded chip flip-chip bump structure of the present invention, which includes a metal substrate frame 1, and a base island 2 and a lead are arranged inside the metal substrate frame 1. pin 3, the pin 3 is stepped, the front of the base island 2 and the pin 3 is flush with the front of the metal substrate frame 1, and the back of the pin 3 is flush with the back of the metal substrate frame 1, so The back of the base island 2 is flush with the step surface of the pin 3, and the back of the base island 2 is flip-mounted with a chip 5 through the underfill glue 4, and the area around the base island 2, the base island 2 and the pin 3 The area between pin 3 and pin 3, the area above base island 2 and pin 3, the area below base island 2 and pin 3, and the outside of the chip are encapsulated with plastic encapsulant 6. The front of base island 2, the front and back of pins 3, and the surface of metal substrate frame 1 are coated with antioxidant (OSP) 7, and the molding compound 6 is flush with the coated antioxidant (OSP) 7 on the upper and lower surfaces of metal substrate frame 1 , a metal ball 8 is arranged on the front surface of the pin 3 .
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453858A (en) * | 2002-04-22 | 2003-11-05 | Nec化合物半导体器件株式会社 | Semiconductor device and producing method thereof |
CN101814482A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | Base island lead frame structure and production method thereof |
CN101814446A (en) * | 2010-04-28 | 2010-08-25 | 江苏长电科技股份有限公司 | Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof |
CN102714201A (en) * | 2010-01-19 | 2012-10-03 | 维西埃-硅化物公司 | Semiconductor package and method |
CN103400771A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-flipped type three-dimensional system-level metal circuit board structure and process method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6815251B1 (en) * | 1999-02-01 | 2004-11-09 | Micron Technology, Inc. | High density modularity for IC's |
US20090115070A1 (en) * | 2007-09-20 | 2009-05-07 | Junji Tanaka | Semiconductor device and method for manufacturing thereof |
CN102683221B (en) * | 2011-03-17 | 2017-03-01 | 飞思卡尔半导体公司 | Semiconductor device and its assemble method |
-
2013
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1453858A (en) * | 2002-04-22 | 2003-11-05 | Nec化合物半导体器件株式会社 | Semiconductor device and producing method thereof |
CN102714201A (en) * | 2010-01-19 | 2012-10-03 | 维西埃-硅化物公司 | Semiconductor package and method |
CN101814446A (en) * | 2010-04-28 | 2010-08-25 | 江苏长电科技股份有限公司 | Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof |
CN101814482A (en) * | 2010-04-30 | 2010-08-25 | 江苏长电科技股份有限公司 | Base island lead frame structure and production method thereof |
CN103400771A (en) * | 2013-08-06 | 2013-11-20 | 江苏长电科技股份有限公司 | Packaging-prior-to-etching chip-flipped type three-dimensional system-level metal circuit board structure and process method thereof |
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