CN103632969A - How the transistor is formed - Google Patents

Abstract

A method for forming a transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a gate structure; forming openings in the semiconductor substrate on both sides of the gate structure; A first liner layer is formed on the surface, the material of the first liner layer is silicon germanium or silicon carbide, and there are dopant ions in the first liner layer, and the dopant ions are P-type ions or N-type ions ; A second liner layer filling the opening is formed on the surface of the first liner layer, the material of the second liner layer is consistent with that of the first liner layer, and the inside of the second liner layer The atomic percent concentration of germanium or carbon is higher than that of the first liner layer, and the second liner layer has the same dopant ions as in the first liner layer, and the dopant ion concentration in the second liner layer is higher than that of the first liner layer. The first underlayment layer is high. The formed transistor has a reduced threshold voltage and stable performance.

Description

How the transistor is formed

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor.

Background technique

As the most basic semiconductor device, transistors are currently being widely used. With the increase of component density and integration of semiconductor devices, the gate size of transistors has become shorter than before; however, the shortened gate size of transistors will make transistors The short channel effect is generated, and then leakage current is generated, which finally affects the electrical performance of the semiconductor device. At present, in the prior art, the stress of the channel region of the transistor is mainly increased to increase the mobility of carriers, thereby increasing the driving current of the transistor and reducing the leakage current in the transistor.

In the prior art, the method for increasing the stress of the channel region of the transistor is to form a stress liner layer in the source/drain region of the transistor, wherein the material of the stress liner layer of the PMOS transistor is silicon germanium (SiGe), silicon and silicon germanium. The compressive stress formed by the lattice mismatch between them improves the performance of the PMOS transistor; the material of the stress liner layer of the NMOS transistor is silicon carbide (SiC), and the tensile stress formed by the lattice mismatch between silicon and silicon carbide, Thereby improving the performance of the NMOS transistor.

The schematic cross-sectional structural diagrams of the formation process of transistors with stress liner layers in the prior art, as shown in FIGS. 1 to 3 , include:

Referring to FIG. 1 , a semiconductor substrate 10 is provided, and a gate structure 11 is formed on the surface of the semiconductor substrate 10 . The gate structure 11 includes: a gate dielectric layer 14 on the surface of the semiconductor substrate 10, a gate electrode layer 15 on the surface of the gate dielectric layer 14, and the gate electrode layer 15 on the surface of the semiconductor substrate 10 on both sides of the gate electrode layer 15. side wall 16.

Referring to FIG. 2 , openings 12 are formed in the semiconductor substrate 10 on both sides of the gate structure 11 . The opening 12 has a sigma (Σ, sigma) shape, that is, the sidewall of the opening 12 and the surface of the semiconductor substrate 10 form a sigma shape, and the apex angle on the sidewall of the opening 12 faces below the gate structure 11 extending within the semiconductor substrate 10 .

Referring to FIG. 3 , a stress liner layer 13 is formed in the opening 12 , and the material of the stress liner layer 13 is silicon germanium or silicon carbide.

It should be noted that, in order to better match the lattice between the stress liner layer 13 and the semiconductor substrate 10, a transition layer 14 is formed between the stress liner layer 13 and the semiconductor substrate 10 in the prior art. The material of the layer 14 is the same as that of the stress liner layer 13 , and the atomic percentage concentration of carbon or germanium in the transition layer 14 is smaller than that of the stress liner layer 13 .

However, the threshold voltage of the transistor with the stress liner layer formed in the prior art is too high and the performance is poor.

For more transistors with stressed liner layers, please refer to the US patent document with publication number US 2011256681A1.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a transistor, which reduces the threshold voltage of the formed transistor and improves performance.

In order to solve the above problems, the present invention provides a method for forming a transistor, comprising: providing a semiconductor substrate, the surface of which has a gate structure; forming openings in the semiconductor substrate on both sides of the gate structure; The sidewall and bottom surface of the opening form a first liner layer, the material of the first liner layer is silicon germanium or silicon carbide, the first liner layer contains dopant ions, and the dopant ion It is a P-type ion or an N-type ion; a second liner layer filling the opening is formed on the surface of the first liner layer, the material of the second liner layer is consistent with that of the first liner layer, and the The atomic percentage concentration of germanium or carbon in the second liner layer is higher than that of the first liner layer, the second liner layer has the same doping ions as in the first liner layer, and the second liner layer The concentration of doping ions in the layer is higher than that of the first liner layer.

Optionally, when the material of the first pad layer and the second pad layer is silicon germanium, the dopant ions are boron or indium.

Optionally, the doping concentration of boron or indium in the first pad layer is 1E17 atoms/cubic centimeter to 1E19 atoms/cubic centimeter, and the doping concentration of boron or indium in the second pad layer is 1E19 atoms/cubic centimeter - 1E21 atoms/cubic centimeter.

Optionally, the atomic percentage concentration of germanium in the first liner layer is 1%-25%, and the atomic percentage concentration of germanium in the second liner layer is 25%-45%.

Optionally, when the material of the first liner layer and the second liner layer is silicon carbide, the dopant ions are phosphorus or arsenic.

Optionally, the doping concentration of phosphorus or arsenic in the first liner layer is 1E17 atoms/cubic centimeter to 1E19 atoms/cubic centimeter, and the doping concentration of phosphorus or arsenic in the second liner layer is 1E19 atoms/cubic centimeter - 1E21 atoms/cubic centimeter.

Optionally, the atomic percentage concentration of carbon in the first liner layer is 0.05%-1%, and the atomic percentage concentration of germanium in the second liner layer is 1%-10%.

Optionally, the formation process of the first liner layer and the second liner layer is a selective epitaxial deposition process.

Optionally, the temperature of the selective epitaxial deposition process is 500°C-800°C, and the gas pressure is 1 Torr-100 Torr.

Optionally, the gas of the selective epitaxial deposition process includes SiH ₄ or SiH ₂ Cl ₂ , and the flow rate of the SiH ₄ or SiH ₂ Cl ₂ is 1 sccm-1000 sccm.

Optionally, the gas in the selective epitaxial deposition process further includes: HCl and H ₂ , the flow rate of HCl is 1 sccm-1000 sccm, and the flow rate of H ₂ is 0.1 slm-50 slm.

Optionally, the process of doping ions in the first liner layer and the second liner layer is an in-situ doping process.

Optionally, the gas of the in-situ doping process is B ₂ H ₆ , InCl ₃ , PH ₃ or AsH ₃ , and the flow rate of the B ₂ H ₆ , InCl ₃ , PH ₃ or AsH ₃ is 1 sccm-1000 sccm.

Optionally, the process of doping ions in the second liner layer is an ion implantation process.

Optionally, the thickness of the first liner layer is 1 angstrom to 200 nanometers, and the thickness from the bottom of the second liner layer to the surface of the semiconductor substrate is 1 angstrom to 200 nanometers.

Optionally, the sidewall of the opening and the surface of the semiconductor substrate form a sigma shape, and the vertex on the sidewall of the opening extends into the semiconductor substrate below the gate structure.

Optionally, a covering layer is formed on the surfaces of the first pad layer and the second pad layer.

Optionally, the material of the covering layer is titanium silicon, nickel silicon or cobalt silicon.

Optionally, the material of the semiconductor substrate is silicon or silicon-on-insulator.

Optionally, the gate structure includes: a gate dielectric layer on the surface of the semiconductor substrate, a gate electrode layer on the surface of the gate dielectric layer, and spacers on the surface of the semiconductor substrate on both sides of the gate electrode layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Form a first liner layer on the sidewall and bottom of the opening, and a second substrate layer filling the opening, the material of the second liner layer is consistent with that of the first liner layer, and the second liner layer The atomic percent concentration of germanium or carbon in the inner liner layer is higher than that of the first liner layer; the second liner layer has the same doping ions as in the first liner layer, and when the formed transistor works, the first liner layer The internally doped ions can enter the channel region, and the migration of the dopant ions in the first liner layer can make it easier for the dopant ions in the second liner layer to pass through the first liner layer , and enter the channel region, so that the threshold voltage of the formed transistor is reduced and the performance is improved; in addition, the dopant ion concentration in the first liner layer is lower than that in the second liner layer, which ensures that in the non-operating state , the dopant ions in the first liner layer will not diffuse to form leakage current, so that the performance of the transistor is stable.

Description of drawings

1 to 3 are schematic cross-sectional structural diagrams of the formation process of a transistor with a stress liner layer in the prior art;

4 to 8 are schematic cross-sectional structure diagrams of the formation process of the transistor described in this embodiment.

Detailed ways

As mentioned in the background art, the threshold voltage of the transistor with the stress liner layer formed in the prior art is too high, and the performance is poor.

Please continue to refer to FIG. 3, in a transistor with a stress liner layer, in order to increase the stress applied to the channel region by the stress liner layer 13, it is necessary to increase the atomic percentage concentration of carbon or germanium in the stress liner layer 13; however, the stress liner layer The higher the atomic percentage concentration of carbon or germanium in the pad layer 13 is, the more serious the lattice difference between the stress pad layer 13 and the semiconductor substrate 10 is, and the Defects at the interface. Therefore, in order to alleviate the lattice difference between the stress liner layer 13 and the semiconductor substrate 10 in the prior art, a transition layer 14 is formed between the stress liner layer 13 and the semiconductor substrate 10, The atomic percent concentration of carbon or germanium in the transition layer 14 is lower than that in the stress liner layer 13, thereby playing a transitional role; and when the atomic percent concentration of carbon or germanium in the transition layer 14 is 20%-25 %, the transition effect is better.

The inventors of the present invention have found through research that after doping ions in the stress liner layer 13 to form source/drain regions, when the transistor is working, it is difficult for the doped ions to cross the transition layer 14 and enter the channel. region, causing the threshold voltage of the transistor to be raised, which increases the power consumption of the semiconductor device; moreover, the higher the atomic percentage concentration of carbon or germanium in the transition layer 14, the doped ions pass through the transition layer The greater the difficulty of 14, the higher the threshold voltage; yet, if the atomic percentage concentration of carbon or germanium in the transition layer 14 is reduced, the transition layer 14 cannot cope with the stress liner layer 13 and the semiconductor substrate 10. The lattice difference between them plays a transitional role, and at the same time, the stress applied to the channel region by the stress liner layer 13 will be correspondingly reduced, which is not conducive to the improvement of the performance of the transistor.

After further research, the inventors of the present invention formed a first liner layer on the sidewalls and bottom of the opening on both sides of the gate structure, formed a second liner layer on the surface of the first liner layer to fill the opening, and The material of the first liner layer is the same as that of the second liner layer, and the atomic percentage concentration of germanium or carbon in the second liner layer is higher than that of the first liner layer; The same dopant ions in the first liner layer, when the transistor is working, the dopant ions in the first liner layer can migrate to the channel region, thereby driving the dopant ions in the second liner layer to the channel Migration in the region makes it easier for the dopant ions in the second liner layer to enter the channel region, thereby reducing the threshold voltage of the transistor; on the other hand, the dopant ion concentration in the first liner layer is higher than that of the second liner The layer is low, and when the transistor is turned off, the dopant ions in the first liner layer are prevented from diffusing to cause leakage current, so that the performance of the transistor is more stable.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. 4 to 8 are schematic cross-sectional structure diagrams of the formation process of the transistor described in this embodiment.

Referring to FIG. 4 , a semiconductor substrate 100 is provided, and the surface of the semiconductor substrate 100 has a gate structure 101 .

The semiconductor substrate 100 is used to provide a working platform for subsequent processes, and the material of the semiconductor substrate 100 is single crystal silicon or silicon-on-insulator, so that the first pad layer and the second pad layer formed subsequently are compatible with the There is a lattice mismatch between the semiconductor substrates 100, which can provide stress to the channel region to increase the mobility of carriers; the crystal plane on the surface of the semiconductor substrate 100 is (100), so that the subsequent anisotropic wet The sidewall of the opening formed after etching by the method and the surface of the semiconductor substrate 100 form a sigma shape, further increasing the stress.

The gate structure 101 includes: a gate dielectric layer 110 located on the surface of the semiconductor substrate 100, a gate electrode layer 111 located on the surface of the gate dielectric layer 110, and semiconductor substrates located on both sides of the gate electrode layer 111 100 surface side walls 112 .

The material of the gate electrode layer 111 is polysilicon or metal; when the material of the gate electrode layer 111 is polysilicon, the gate dielectric layer 110 is silicon oxide, silicon nitride, silicon oxynitride; when the gate electrode layer When the material of 111 is metal, the gate dielectric layer 110 is a high-K dielectric material, and the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide, the metal includes: aluminum, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum or tungsten; the material of the side wall 112 One or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

When the material of the gate electrode layer 111 is polysilicon, and the gate dielectric layer 110 is silicon oxide, silicon nitride, or silicon oxynitride, the formation process of the gate structure 101 is as follows: on the surface of the semiconductor substrate 100 Depositing and forming a gate dielectric film; forming a gate electrode film on the surface of the gate dielectric film; etching the gate dielectric film and the gate electrode film to form a gate dielectric layer 110 and a gate electrode layer 111; A spacer layer is formed on the surface of the dielectric layer 110 and the gate electrode layer 111 ; the spacer layer is etched back to form spacer walls 112 on the surface of the semiconductor substrate 100 on both sides of the gate electrode layer 111 .

When the material of the gate electrode layer 111 is metal and the gate dielectric layer 110 is a high-K dielectric material, the formation process of the gate structure 101 is as follows: depositing and forming a gate dielectric thin film on the surface of the semiconductor substrate 100; Form a dummy gate film on the surface of the gate dielectric film, the material of the dummy gate film is polysilicon; etch the gate dielectric film and the gate film to form a gate dielectric layer 110 and a dummy gate; The semiconductor substrate 100, the gate dielectric layer 110 and the surface of the dummy gate form a spacer layer; the sidewall layer is etched back, and spacer 112 is formed on the surface of the semiconductor substrate 100 on both sides of the dummy gate; An insulating layer is formed on the surface of the semiconductor substrate on both sides of the sidewall 112 and the dummy gate; after the insulating layer is formed, the dummy gate is removed to form an opening; metal is filled in the opening to form a gate electrode layer 111 .

It should be noted that there is also a mask layer (not shown) on the surface of the gate electrode layer 111, and the material of the mask layer is silicon nitride, titanium nitride, thallium nitride, tungsten nitride, aluminum oxide One or more combinations of them; the mask layer is used to avoid damage to the surface of the gate electrode layer 211 during the subsequent dry etching and wet etching processes for forming sigma-shaped openings; the mask layer The film layer is removed after the first liner layer and the second liner layer are formed in a subsequent process.

Referring to FIG. 5 , openings 102 are formed in the semiconductor substrate 100 on both sides of the gate structure 101 .

The opening 102 is used to form a first pad layer and a second pad layer in a subsequent process; in this embodiment, the sidewall of the opening 102 and the surface of the semiconductor substrate 100 form a sigma (Σ, sigma) shape, the vertex on the side wall of the opening 102 extends into the semiconductor substrate 100 below the gate structure 101, so that the first pad layer formed in the opening 102 on both sides of the gate structure 101 will If the distance is shorter, the stress applied to the channel region under the gate structure 101 by the subsequently formed first liner layer and the second liner layer is greater, and the performance of the formed transistor is improved.

In this embodiment, the forming process of the opening 102 is as follows: using the gate structure 101 as a mask, dry etching is used to form a hole in the semiconductor substrate 100 with sidewalls perpendicular to the surface of the semiconductor substrate 100. an opening (not shown); after dry etching, wet etching is used to etch the opening so that the apex on the sidewall of the opening extends into the semiconductor substrate 100 below the gate structure 101 to form a sigma-shaped The opening 102.

The dry etching is anisotropic dry etching, and the etching gas is chlorine, hydrogen bromide or a mixed gas of chlorine and hydrogen bromide; the dry etching process parameters are: the flow rate of hydrogen bromide The flow rate of the chlorine gas is 20-100 sccm, the flow rate of the inert gas is 50-1000 sccm, the pressure of the etching chamber is 2-200 mTorr, and the etching time is 15-60 seconds.

The wet etching is anisotropic wet etching, the etching solution is an alkaline solution, and the alkaline solution is potassium hydroxide (KOH), sodium hydroxide (NaOH), lithium hydroxide ( LiOH), lithium hydroxide ammonia water (NH ₄ OH) is one or more combinations of tetramethylammonium hydroxide (TMAH).

Since the crystal plane of the surface of the semiconductor substrate 100 is (100), the etching rate of the anisotropic wet etching in the direction perpendicular to the surface of the semiconductor substrate 100 and parallel to the surface of the semiconductor substrate 100 is Faster, and the etching rate is the slowest when etching the crystal plane (111), so that the shape of the opening 102 becomes a sigma shape; when the first liner layer is subsequently formed in the opening 102, the adjacent If the distance between the first liner layers is small, the stress exerted by the first liner layer on the channel region is relatively large.

In another embodiment, the opening 102 is formed by anisotropic dry etching, and the sidewall of the opening 102 is perpendicular to the surface of the semiconductor substrate, which simplifies the process and saves cost.

Please refer to FIG. 6 , a first liner layer 103 is formed on the sidewall and bottom surface of the opening 102 , and the material of the first liner layer 103 is silicon germanium or silicon carbide. It has doping ions, and the doping ions are P-type ions or N-type ions.

The thickness of the first pad layer 103 is 1 angstrom to 200 nanometers, and the formation process of the first pad layer 103 is a selective epitaxial deposition process; when the formed transistor is a PMOS transistor, the first pad layer The material of the layer 103 is silicon germanium, wherein the atomic percentage concentration of germanium is 1%-25%, preferably, the atomic percentage concentration of germanium is 20%-25%, so that the first liner layer 103 can be used as the second liner layer formed subsequently. At the same time as the transition between the second liner layer and the semiconductor substrate 100, sufficient stress is provided to the formed transistor channel region to improve carrier mobility; when the formed transistor is an NMOS transistor, the first The material of the liner layer 103 is silicon carbide, wherein the atomic percent concentration of carbon is 0.05%˜1%.

When the formed transistor is a PMOS transistor, and the material of the first pad layer 103 is silicon germanium, the doped ions in the first pad layer 103 are P-type ions, including boron or indium; the boron or The doping concentration of indium in the first pad layer 103 is 1E17 atoms/cubic centimeter-1E19 atoms/cubic cm; when the formed transistor is an NMOS transistor and the material of the first pad layer 103 is silicon carbide, the The doped ions in the first pad layer 103 are N-type ions, including phosphorus or arsenic; the doping concentration of the phosphorus or arsenic in the first pad layer 103 is 1E17 atoms/cm3-1E19 atoms/cubic centimeter.

The doped ions in the first liner layer 103 can migrate to the channel region when the formed transistor works; and the migration of doped ions in the first liner layer 103 can drive the subsequently formed second The dopant ions in the liner layer pass through the first liner layer and enter the channel region, thereby reducing the threshold voltage of the formed transistor; in addition, the doping of the first liner layer 103 The concentration of ions is lower than that of the subsequently formed second liner layer, so when the formed transistor is turned off, the ions in the first liner layer 103 will not diffuse to form leakage current, and the performance of the formed transistor is stable.

When the formed transistor is a PMOS transistor, the formation process of the first liner layer 103 is a selective epitaxial deposition process, the temperature is 500-800 degrees Celsius, the pressure is 1 Torr-100 Torr, and the reaction gas includes silicon source gas SiH ₄ or SiH ₂ Cl ₂ , and germanium source gas GeH ₄ , the flow rate of the silicon source gas and germanium source gas is 1 sccm-1000 sccm; the gas of the selective epitaxial deposition process also includes HCl and H ₂ , the flow rate of the HCl is 1sccm-1000sccm, the flow rate of _H2 is 0.1slm-50slm.

The process of doping boron or indium in the first liner layer 103 is an in-situ doping process, that is, when the first liner layer 103 is selectively epitaxially deposited, boron source gas _B2H is added to the reaction gas _6. Or the indium source gas InCl ₃ , the flow rate of the boron source gas or the indium source gas is 1 sccm-1000 sccm.

When the formed transistor is an NMOS transistor, the formation process of the first liner layer 103 is a selective epitaxial deposition process, the temperature is 500°C-800°C, the pressure is 1 Torr-100 Torr, and the reaction gas includes silicon source gas SiH ₄ Or SiH ₂ Cl ₂ , and carbon source gas CH ₄ , CH ₃ Cl or CH ₂ Cl ₂ , the flow rate of the silicon source gas and carbon source gas is 1 sccm-1000 sccm; the gas of the selective epitaxial deposition process also includes HCl and H ₂ , the HCl flow rate is 1 sccm-1000 sccm, and the H ₂ flow rate is 0.1 slm-50 slm.

The process of doping phosphorus or arsenic in the first pad layer 103 is an in-situ doping process, that is, during the selective epitaxial deposition of the first pad layer 103, phosphorus source gas PH ₃ , Or the arsenic source gas AsH ₃ , the flow rate of the phosphorus source gas or the arsenic source gas is 1 sccm-1000 sccm.

Please refer to FIG. 7 , a second liner layer 104 filling the opening 102 (as shown in FIG. 6 ) is formed on the surface of the first liner layer 103, and the material of the second liner layer 104 is the same as the first The liner layer 103 is consistent, and the atomic percentage concentration of germanium or carbon in the second liner layer 104 is higher than that of the first liner layer 103. The same dopant ions in the second liner layer 104 are higher than that in the first liner layer 103 .

The thickness of the second pad layer 104 is 1 angstrom to 200 nanometers, and the formation process of the second pad layer 104 is a selective epitaxial deposition process; when the formed transistor is a PMOS transistor, the second pad layer The material of layer 104 is silicon germanium, wherein the atomic percentage concentration of germanium is 25%~45%; when the formed transistor is an NMOS transistor, the material of the second liner layer 104 is silicon carbide, wherein the atomic percentage concentration of carbon is 1% to 10%; the atomic percentage concentration of germanium or carbon in the second liner layer 104 is higher than that of the first liner layer 103, which can provide greater stress to the channel region and increase carrier mobility , the performance of the transistor is good.

When the formed transistor is a PMOS transistor and the material of the second pad layer 104 is silicon germanium, the doped ions in the second pad layer 104 are P-type ions, including boron or indium; the boron or The doping concentration of indium in the first liner layer 103 is 1E19-1E21 atoms/cubic centimeter; when the formed transistor is an NMOS transistor and the material of the second liner layer 104 is silicon carbide, the first liner The doped ions in the pad layer 103 are N-type ions, including phosphorus or arsenic; the doping concentration of the phosphorus or arsenic in the first pad layer 103 is 1E19 atoms/cubic centimeter-1E21 atoms/cubic centimeter; After doping ions in the second liner layer 104 , a source/drain region is formed; when the formed transistor is in operation, the doped ions in the second liner layer 104 are affected by the working voltage and migrate to the channel region.

Since the first pad layer 103 is formed as a transition between the second pad layer 104 and the semiconductor substrate 100, there will be no gap between the second pad layer 104 and the semiconductor substrate 100 at the interface due to lattice differences. cause defects; therefore, when the formed transistor works, the doped ions in the second liner layer 104 need to pass through the first liner layer 103 to reach the channel region; in this embodiment, the first liner layer There are the same dopant ions in the pad layer 103 as in the second pad layer 104, when the formed transistor works, the dopant ions in the first pad layer 103 will migrate to the channel region, thereby driving the second pad layer The dopant ions in the liner layer 104 pass through the first liner layer 103, so the dopant ions in the second liner layer 104 are easier to pass through the first liner layer 103, thereby reducing the formed The threshold voltage of the transistor improves the performance of the transistor.

The formation process of the second liner layer 104 is a selective epitaxial deposition process, and the process of doping ions is an in-situ doping process. The formation process of the second liner layer 104 and the process of doping ions are the same as those of the first The liner layer 103 is the same and will not be repeated here.

It should be noted that, in other embodiments, the doped ions in the second liner layer 104 can be doped by ion implantation after the selective epitaxial deposition of silicon germanium or silicon carbide.

Referring to FIG. 8 , a covering layer 105 is formed on the surfaces of the first liner layer 103 and the second liner layer 104 .

The cover layer 105 is used as an electrode for the formed transistor source/drain region; the material of the cover layer 105 is metal silicide (salicide), including titanium silicon, nickel silicon or cobalt silicon; the cover layer 105 The forming process is as follows: a mask layer is formed on the surface of the semiconductor substrate 100 on both sides of the gate structure 101, and the mask layer exposes the surfaces of the first pad layer 103 and the second pad layer 104; layer, a silicon layer is formed by selective epitaxial deposition on the surface of the first pad layer 103 and the second pad layer 104; a metal layer is deposited on the surface of the silicon layer, and the material of the metal layer is titanium, nickel or cobalt; after the metal layer is formed, thermal annealing is performed to make the metal layer react with the silicon layer to form the covering layer 105; and the remaining metal layer and mask layer on the surface of the covering layer 105 are removed.

In the method for forming the transistor in this embodiment, the first liner layer 103 and the second liner layer 104 located on the surface of the first liner layer 103 and filling the opening are formed in the openings on both sides of the gate structure 101 ; The second liner layer 104 has the same dopant ions as in the first liner layer 103, when the transistor works, the doped ions in the first liner layer 103 can flow to the channel region migration, thereby driving the doped ions in the second liner layer 104 to pass through the first liner layer 103 and enter the channel region; the threshold voltage of the formed transistor is reduced; secondly, the ions in the first liner layer 103 The concentration of doping ions is lower than that in the second pad layer 104. When the transistor is turned off, the doped ions in the first pad layer 103 will not diffuse, which avoids leakage current. Stable performance.

In summary, a first liner layer is formed on the sidewall and bottom of the opening, and a second substrate layer that fills the opening is formed, the material of the second liner layer is consistent with that of the first liner layer, and the The atomic percent concentration of germanium or carbon in the second liner layer is higher than that of the first liner layer; the second liner layer has the same doping ions as in the first liner layer, and when the formed transistor works, The doped ions in the first liner layer can enter the channel region, and the migration of the doped ions in the first liner layer can make it easier for the dopant ions in the second liner layer to pass through the channel region. The first liner layer, and enter the channel region, so that the threshold voltage of the formed transistor is reduced and the performance is improved; in addition, the dopant ion concentration in the first liner layer is lower than that of the second liner layer, ensuring that In the non-working state, the dopant ions in the first liner layer will not diffuse to form leakage current, so that the performance of the transistor is stable.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (20)

1. A method for forming a transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a gate structure; forming openings in the semiconductor substrate on both sides of the gate structure; A first liner layer is formed on the sidewall and bottom surface of the opening, the material of the first liner layer is silicon germanium or silicon carbide, the first liner layer contains dopant ions, and the dopant Ions are P-type ions or N-type ions; A second liner layer filling the opening is formed on the surface of the first liner layer, the material of the second liner layer is consistent with that of the first liner layer, and the germanium in the second liner layer Or the atomic percent concentration of carbon is higher than that of the first liner layer, the second liner layer has the same dopant ions as in the first liner layer, and the dopant ion concentration in the second liner layer is higher than that of the first liner layer One cushion layer height. 2 . The method for forming a transistor according to claim 1 , wherein when the material of the first pad layer and the second pad layer is silicon germanium, the dopant ions are boron or indium. 3 . 3. The method for forming a transistor according to claim 2, wherein the doping concentration of boron or indium in the first liner layer is 1E17 atoms/cubic centimeter to 1E19 atoms/cubic centimeter, and the second The doping concentration of boron or indium in the liner layer is 1E19 atoms/cm3-1E21 atoms/cm3. 4. The forming method of the transistor according to claim 2, wherein the atomic percentage concentration of germanium in the first pad layer is 1%-25%, and the atomic percentage concentration of germanium in the second pad layer is 25%-45%. 5 . The method for forming a transistor according to claim 1 , wherein when the material of the first pad layer and the second pad layer is silicon carbide, the dopant ions are phosphorus or arsenic. 6. The method for forming a transistor according to claim 5, wherein the doping concentration of phosphorus or arsenic in the first liner layer is 1E17 atoms/cubic centimeter to 1E19 atoms/cubic centimeter, and the second The doping concentration of phosphorus or arsenic in the liner layer is 1E19 atoms/cm3-1E21 atoms/cm3. 7. The method for forming a transistor according to claim 5, wherein the atomic percentage concentration of carbon in the first pad layer is 0.05%-1%, and the atomic percentage concentration of germanium in the second pad layer is 1%-10%. 8 . The method for forming a transistor according to claim 1 , wherein the forming process of the first pad layer and the second pad layer is a selective epitaxial deposition process. 9 . The method for forming a transistor according to claim 8 , wherein the temperature of the selective epitaxial deposition process is 500° C.-800° C., and the gas pressure is 1 Torr-100 Torr. 10. The method for forming a transistor according to claim 8, wherein the gas in the selective epitaxial deposition process comprises SiH ₄ or SiH ₂ Cl ₂ , and the flow rate of the SiH ₄ or SiH ₂ Cl ₂ is 1 sccm-1000 sccm . 11. The method for forming a transistor according to claim 10, wherein the gas in the selective epitaxial deposition process further comprises: HCl and H ₂ , the flow of HCl is 1 sccm-1000 sccm, and the flow of H ₂ is 0.1 slm-50slm. 12 . The method for forming a transistor according to claim 1 , wherein the process of doping ions in the first pad layer and the second pad layer is an in-situ doping process. 13 . 13. The method for forming a transistor according to claim 12, wherein the gas used in the in-situ doping process is B ₂ H ₆ , InCl ₃ , PH ₃ or AsH ₃ , and the B ₂ H ₆ , InCl ₃ , PH ₃ or AsH ₃ flow rate is 1sccm-1000sccm. 14. The method for forming a transistor according to claim 1, wherein the process of doping ions in the second liner layer is an ion implantation process. 15. The method for forming a transistor according to claim 1, wherein the thickness of the first pad layer is 1 angstrom to 200 nanometers, and the thickness from the bottom of the second pad layer to the surface of the semiconductor substrate is 1 Angstrom ~ 200 nanometers. 16. The method for forming a transistor according to claim 1, wherein the sidewall of the opening forms a sigma shape with the surface of the semiconductor substrate, and the vertex angle on the sidewall of the opening faces to the bottom of the gate structure. extending within the semiconductor substrate. 17. The method for forming a transistor according to claim 1, wherein a covering layer is formed on the surfaces of the first pad layer and the second pad layer. 18. The method for forming a transistor according to claim 17, wherein the material of the capping layer is titanium silicon, nickel silicon or cobalt silicon. 19. The method for forming the transistor according to claim 1, wherein the material of the semiconductor substrate is silicon or silicon-on-insulator. 20. The method for forming a transistor according to claim 1, wherein the gate structure comprises: a gate dielectric layer on the surface of the semiconductor substrate, a gate electrode layer on the surface of the gate dielectric layer, and the gate The sidewalls on the surface of the semiconductor substrate on both sides of the electrode layer.

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