CN103632962A - A manufacturing method for a DMOS pipe and an apparatus - Google Patents

Abstract

The invention discloses a manufacturing method and device of a DMOS tube. The manufacturing method includes: making an epitaxial layer on the surface of an N-type substrate; forming a field oxide layer on the surface of the epitaxial layer, wherein the surface of the epitaxial layer includes a first region and a second region; only for the first region Photolithography is performed on the field oxide layer in the first region to form a channel in the first region, so that the field oxide layer corresponding to the second region remains.

Description

A kind of manufacturing method and device of DMOS tube

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method and device for manufacturing a DMOS tube.

Background technique

A DMOS device is composed of hundreds or thousands of DMOS cells of a single structure. The number of these units is determined according to the driving capability required by a chip, and the performance of DMOS directly determines the driving capability and chip area of the chip.

DMOS is similar in structure to CMOS devices, and also includes electrodes such as active sources, drains, and gates. The main technical indicators to measure a DMOS are: on-resistance, threshold voltage, breakdown voltage, etc. Among them, on-resistance refers to the resistance from drain to source when the device is working. For DMOS devices, the on-resistance should be reduced as much as possible, because when the on-resistance is small, the DMOS device will provide a good switching characteristic, that is, if the on-resistance between the drain and source is small, there will be Larger output current, which can have a stronger drive capability.

In power applications, since DMOS devices adopt a vertical device structure, they have many advantages, including high current drive capability, low Rds on-resistance, and high breakdown voltage. Since DMOS devices have a high switching frequency and low power consumption during the switching process, they are considered to be very suitable as ideal semiconductor components for switching operations.

In DMOS devices, the thickness of the gate oxide layer is inversely proportional to the gate capacitance, and the thicker the oxide layer is, the smaller the capacitance is. Since the switching of DMOS devices is realized by charging and discharging the gate capacitance, the smaller the gate capacitance is, the faster the switching speed is, so the thickness of the gate oxide layer is proportional to the switching speed of the DMOS device. The thicker, the faster the switching speed of the power transistor.

In the prior art, methods for manufacturing DMOS devices include:

Step 1: making an N-type epitaxial layer on an N-type substrate;

Step 2: growing a field oxide layer on the epitaxial layer;

Step 3: removing the field oxide layer;

Step 4: growing a thin oxide layer on the surface of the epitaxial layer;

Step 5: growing a gate oxide layer on the surface of the thin oxide layer;

Step 6: growing a polysilicon layer on the surface of the gate oxide layer;

Step 7: making P wells and N wells on the epitaxial layer;

Step 8: growing a dielectric layer on the surface of the polysilicon layer;

Step 9: forming a metal layer on the dielectric layer.

After the above steps 1 to 9, the DMOS device as shown in FIG. 1 is manufactured.

However, in the process of realizing the technical solution of the invention in the embodiment of the present application, the inventor of the present application found that the above-mentioned technology has at least the following technical problems:

In the method described in the above prior art, in order to increase the thickness of the gate oxide layer of the power transistor, a thin oxide layer is grown after removing the field oxide layer, but there is an increase in the thickness of the gate oxide layer corresponding to the channel region. technical problems.

Since the threshold voltage and on-resistance of the DMOS device are proportional to the thickness of the gate oxide layer corresponding to the channel region, when the thickness of the gate oxide layer corresponding to the channel region increases, the threshold voltage and on-resistance of the DMOS device will also exist. Technical problem of high on-resistance.

That is, in the prior art, although the switching speed of the DMOS device is improved, other performances of the DMOS device are also reduced.

Contents of the invention

Embodiments of the present application provide a method and device for manufacturing a DMOS transistor, which are used to solve the technical problem of increasing the thickness of the gate oxide layer corresponding to the channel region in the prior art.

An embodiment of the present application provides a method for manufacturing a DMOS transistor, including: forming an epitaxial layer on the surface of an N-type substrate; forming a field oxide layer on the surface of the epitaxial layer, wherein the surface of the epitaxial layer includes a first region and The second region: performing photolithography on only the field oxide layer in the first region to form a channel in the first region, so that the field oxide layer corresponding to the second region can be preserved.

Preferably, after performing photolithography on only the field oxide layer in the first region, the method further includes: forming a gate oxide layer on the surfaces of the first region and the second region.

Preferably, after the gate oxide layer is formed on the surface of the first region and the second region, the method further includes: forming a polysilicon layer on the surface of the gate oxide layer; etching the polysilicon layer in the first region , forming a channel in the second region.

Preferably, after the formation of the channel in the second region, the method further includes: forming a P well by implanting first ions into the channel in the second region.

Preferably, after the formation of the P well, the method further includes: covering the third region with photoresist, the third region being located in the channel of the second region; The second ion, forming an N well in the channel of the second region except the third region; removing the photoresist in the third region; adding a medium on the surface of the first region and the second region layer; etching the dielectric layer and gate oxide layer in the first region according to preset rules; and covering the surface of the first region and the second region with a metal layer.

On the other hand, the embodiment of the present application also provides a semiconductor device, including: an N-type substrate; an epitaxial layer located on the surface of the N-type substrate, wherein the surface of the epitaxial layer includes a first region and a second region a field oxide layer formed on the surface of the epitaxial layer corresponding to the second region; a gate oxide layer formed on the surfaces of the first region and the second region except the fourth region, wherein the fourth region is located In the channel of the second region, the channel of the second region is located in the first region; the polysilicon layer is formed on the surface of the gate oxide layer except the channel in the second region; Surfaces of the first region and the second region outside the region; a metal layer covering the first region and the second region.

One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

In the embodiment of the present application, when the field oxide layer is photolithography, the field oxide layer except the gate field oxide layer corresponding to the channel region is retained. While not changing the thickness of the gate oxide layer corresponding to the channel region, the thickness of the gate oxide layer is increased.

Further, due to the increased thickness of the gate oxide layer, the gate capacitance is improved and the switching speed of the power transistor is increased.

Furthermore, while the switching speed of the DMOS transistor is increased, the threshold voltage and on-resistance of the DMOS transistor remain unchanged, and no cost is increased.

Description of drawings

Fig. 1 is the structural diagram of DMOS tube in the prior art;

Fig. 2 is the manufacturing flowchart of DMOS tube in an embodiment of the present application;

FIG. 3 is a structural diagram of a DMOS tube after forming an epitaxial layer in an embodiment of the present application;

FIG. 4 is a structural diagram of a DMOS tube after forming a field oxide layer in an embodiment of the present application;

FIG. 5 is a structure diagram of a DMOS tube after etching the field oxide layer in an embodiment of the present application;

FIG. 6 is a structure diagram of a DMOS transistor after forming a gate oxide layer in an embodiment of the present application;

FIG. 7 is a structural diagram of a DMOS transistor after forming a polysilicon layer in an embodiment of the present application;

FIG. 8 is a structural diagram of a DMOS transistor after forming a P well in an embodiment of the present application;

FIG. 9 is a structural diagram of a DMOS tube covered with photoresist in an embodiment of the present application;

FIG. 10 is a structural diagram of a DMOS transistor after forming an N well in an embodiment of the present application;

FIG. 11 is a structural diagram of a DMOS tube after forming a dielectric layer in an embodiment of the present application;

FIG. 12 is a structure diagram of a DMOS tube after forming a metal layer in an embodiment of the present application.

Detailed ways

An embodiment of the present application provides a method for manufacturing a DMOS transistor. By retaining the field oxide layer except for the gate oxide layer corresponding to the channel region, the thickness of the gate oxide layer corresponding to the channel region is not changed, and the thickness of the gate oxide layer is increased. the thickness of the gate oxide layer. It solves the problem of increasing the thickness of the gate oxide layer corresponding to the channel region in the prior art to increase the gate oxide layer, which improves the threshold voltage and on-resistance of the MOS tube, which affects the MOS tube while increasing the switching speed. other performance technical issues.

The technical solution in the embodiment of the present application is to solve the above problems, and the general idea is as follows:

Making an epitaxial layer on the surface of the N-type substrate; forming a field oxide layer on the surface of the epitaxial layer, wherein the surface of the epitaxial layer includes a first region and a second region; only performing the field oxidation layer on the first region Photolithography, forming a channel in the first region, so that the field oxide layer corresponding to the second region is preserved.

In order to better understand the above technical solution, the above technical solution will be described in more detail below in conjunction with the accompanying drawings and specific implementation methods.

A method for manufacturing a DMOS tube is provided in the embodiment of the present application. The specific manufacturing process refers to FIG. 2, as shown in FIG. 2, the method includes:

Step 201: Fabricate an N-type epitaxial layer on an N-type substrate.

In the embodiment of the present application, the specific implementation process of step 201 is: forming a gate structure on an N-type substrate, forming an isolation layer on the semiconductor substrate and the gate structure, and then sacrificing the semiconductor substrates on both sides of the spacer layer. A recessed region is formed in the bottom, and epitaxy is formed in the recessed region by a selective epitaxial process, wherein the semiconductor epitaxial layer is N type.

Through step 201, a semiconductor device as shown in FIG. 3 is obtained, and the device includes: an N-type substrate, and an N-type epitaxial layer formed on the N-type substrate.

After forming the N-type epitaxial layer based on step 201, the method in the embodiment of the present application proceeds to step 202, that is, forming a field oxide layer on the surface of the epitaxial layer, wherein the surface of the epitaxial layer includes a first region and a second area.

Through step 202, a semiconductor device as shown in FIG. 4 is obtained, and the device further includes: a field oxide layer located on the surface of the N-type epitaxial layer.

After forming the field oxide layer based on step 202, proceed to step 203, that is, only perform photolithography on the oxide layer in the first region to form a channel in the first region, so that the field oxide layer corresponding to the second region can be retained .

In a specific implementation process, the photolithography step in step 203 generally includes:

First, drop a surface treatment agent on the surface of the first area to be treated for surface treatment;

Then, according to the requirements, select the required glue type for uniform glue coating;

Then, use a hot plate to bake the glue to remove the solvent in the film and improve the adhesion;

Next, enter the exposure process, and then select the developer according to the type of photoresist, leave the film as a masking part through development, and wash off the excess film;

Finally, the photoresist is finally removed through processes such as film hardening and corrosion.

Photolithography is a key step in semiconductor processing, and the quality of photolithography will affect the performance and reliability of devices.

Through step 203, a semiconductor device as shown in FIG. 5 is obtained, and the device includes:

N-type substrate; an N-type epitaxial layer on the N-type substrate; a field oxide layer in the second region retained by photolithography; a channel in the first region is formed in the field oxide layer, The gate is divided into a channel region gate and a gate outside the channel region, and the gate outside the channel region is the second region.

After performing photolithography on the first region based on step 203, proceed to step 204, ie, generate a gate oxide layer on the surface of the first region and the second region.

Through step 204, a semiconductor device as shown in FIG. 6 is obtained, and the device further includes: a gate oxide layer located on the surface of the first region and the second region.

After generating the gate oxide layer based on step 204, proceed to step 205, namely: form a polysilicon layer on the surface of the gate oxide layer, etch the polysilicon layer in the first region to form a channel in the second region.

Through step 205, a semiconductor device as shown in FIG. 7 is obtained, wherein the range of the channel in the second region formed by etching the polysilicon layer is determined by specific rules. For example, for high-voltage products, the common design is 7-9um.

After forming the polysilicon layer based on step 205, proceed to step 206, that is, implant the first ions into the channel of the second region to form a P well.

In the embodiment of the present application, the first ions may be boron ions. In actual production, since boron ions are implanted and only form a junction depth of less than 0.5um on the surface of the epitaxial layer, in order to achieve the required breakdown voltage , the general junction depth needs to be about 3-4um, which needs to be realized by pushing the junction step. The junction pushing step specifically refers to that the doped wafer passes through a certain temperature and a certain period of time in the furnace tube, so that the boron ions Diffused to the desired junction depth. Among the common process conditions, the temperature is 1150° C. and the time is 120 minutes. In the embodiment of the present application, it is necessary to pay attention to the selection of the temperature and time for pushing the junction of the P well, so that the P well cannot be diffused below the field oxygen, otherwise the threshold voltage will be adversely affected. Threshold voltage is an important parameter of MOS devices, and breakdown voltage is another important parameter thereof. Threshold voltage and breakdown voltage are related to many factors, such as well concentration, gate oxide thickness, etc. Those skilled in the art can determine the implanted dose according to the required range of breakdown voltage and threshold voltage, usually around E13 atoms/cm2.

Through step 206, a semiconductor device as shown in FIG. 8 is obtained, and the semiconductor device further includes: a P well located in the N-type epitaxial layer.

After the P well is manufactured based on step 206, enter into step 207, that is, cover the photoresist in the third region, and the third region is located in the channel of the second region.

Through step 207, a semiconductor device as shown in FIG. 9 is obtained, and the semiconductor device further includes: a photoresist located in the third region in the channel of the second region.

After step 207, proceed to step 208, that is, by implanting second ions into the channel of the second region, an N well is formed in the channel of the second region except the third region.

In the specific implementation process, the second ions in the embodiment of the present application are phosphorus ions. Of course, the second ions can also be arsenic ions. For the dose, those skilled in the art can determine the required breakdown voltage and threshold voltage The range determines the implanted dose, usually E15 atoms/cm2 or E16 atoms/cm2.

Through step 208, the semiconductor device as shown in FIG. 10 is obtained, and the device further includes: an N well.

In the manufacturing steps of the above-mentioned P well and N well, it should be noted that different doses and different energies of implanted ions should be selected according to the specific required doping concentration during ion implantation, because the depth of entry and exit of ions increases with the increase of ion energy. Increased, therefore doping depth can be achieved by controlling the ion beam energy high or low. Another issue that needs attention during the injection process is the processing temperature.

After the fabrication of the N well based on step 208 is completed, proceed to step 209 , that is, remove the photoresist in the third region.

Further, after step 209, the method in this embodiment of the present application further includes step 210, that is: adding a dielectric layer on the surface of the first area and the second area, and according to the preset rule, the Dielectric layer and gate oxide layer are etched.

Through step 210, a semiconductor device as shown in FIG. 11 is obtained. In the specific implementation process, the preset rules are set by those skilled in the art according to the needs. Generally, the etching of the dielectric layer, that is, the etching of holes, is generally designed to be 3-5um. The etching process is divided into wet etching and dry etching. In the embodiment of the present application, those skilled in the art can choose from wet etching and dry etching according to specific requirements in practice.

After the etching of the dielectric layer and the gate oxide layer based on step 210 is completed, proceed to step 211, namely: cover the surface of the first region and the second region with a metal layer.

Through step 211, a semiconductor device as shown in FIG. 12 is obtained. In the embodiment, the covered metal layer is aluminum, or aluminum doped with silicon or copper. Of course, for those of ordinary skill in the art, it is also possible to cover the metal layer made of other materials according to the actual situation. Here, examples will not be given one by one in this application.

An embodiment of the present invention also provides a semiconductor device. In the embodiment of the present application, the semiconductor device is specifically a DMOS transistor. Please refer to FIG. 12, which specifically includes:

N-type substrate;

The epitaxial layer is located on the surface of the N-type substrate, wherein the surface of the epitaxial layer includes a first region and a second region.

The specific manufacturing method of the epitaxial layer includes: forming a gate structure on an N-type substrate, forming an isolation layer on the semiconductor substrate and the gate structure, and then forming recessed regions in the semiconductor substrate on both sides of the sacrificial spacer layer , and using a selective epitaxy process to form epitaxy in the recessed region, wherein the semiconductor epitaxy layer is N-type.

A field oxide layer is formed on the surface of the epitaxial layer corresponding to the second region.

In the embodiment of the present application, the field oxide layer is completed by photolithography, and only the oxide layer in the first region is photolithographically formed to form a channel in the first region, so that the field oxide layer corresponding to the second region can be reserve.

The photolithography steps generally include:

First, drop the surface treatment agent on the surface of the first area that needs to be treated for surface treatment, and then select the required glue type for uniform glue coating according to the requirements;

Then, use a hot plate to bake the glue to remove the solvent in the film and improve the adhesion;

Then, enter the exposure process, and then select the developer according to the type of photoresist, leave the film as a masking part through development, wash off the excess film, and then go through the process of film hardening and corrosion;

Finally, the photoresist is removed. Photolithography is a key step in semiconductor processing, and the quality of photolithography will affect the performance and reliability of devices. a gate oxide layer formed on the surfaces of the first region and the second region except the fourth region, wherein the fourth region is located in the channel of the second region, and the channel of the second region is located in the first region .

a gate oxide layer formed on the surfaces of the first region and the second region except the fourth region, wherein the fourth region is located in the channel of the second region, and the channel of the second region is located in the first region . The gate oxide layer first covers the surfaces of the first region and the second region, and is formed by etching together with the dielectric layer in the step of etching the dielectric layer.

A polysilicon layer is formed on the surface of the gate oxide layer except the channel in the second region. The polysilicon layer is based on first forming a polysilicon layer on the gate oxide layer, and then etching it to retain the polysilicon layer except the channel in the second region.

A dielectric layer is formed on the surfaces of the first region and the second region except the fourth region.

The dielectric layer is completed by etching holes after the first region and the second region are covered with the dielectric layer.

a metal layer covering the first area and the second area. Wherein, in this embodiment, the covered metal layer is aluminum, or aluminum doped with silicon or copper. Of course, for those of ordinary skill in the art, it is also possible to cover the metal layer made of other materials according to the actual situation. The metal layer, here, will not be exemplified one by one in this application.

One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

In the embodiment of the present application, when the field oxide layer is photolithography, the field oxide layer except the gate field oxide layer corresponding to the channel region is retained. While not changing the thickness of the gate oxide layer corresponding to the channel region, the thickness of the gate oxide layer is increased.

Further, due to the increased thickness of the gate oxide layer, the gate capacitance is improved and the switching speed of the power transistor is increased.

Furthermore, while the switching speed of the DMOS transistor is increased, the threshold voltage and on-resistance of the DMOS transistor remain unchanged, and no cost is increased.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. A manufacturing method of a DMOS tube, characterized in that, comprising: Making an epitaxial layer on the surface of the N-type substrate; forming a field oxide layer on the surface of the epitaxial layer, wherein the surface of the epitaxial layer includes a first region and a second region; Photolithography is only performed on the field oxide layer in the first region to form a channel in the first region, so that the field oxide layer corresponding to the second region remains. 2. The method according to claim 1, further comprising: after performing photolithography only on the field oxide layer in the first region: A gate oxide layer is formed on the surfaces of the first region and the second region. 3. The method according to claim 2, further comprising: forming a polysilicon layer on the surface of the gate oxide layer; Etching the polysilicon layer in the first region to form a channel in the second region. 4. The method according to claim 3, further comprising: A P well is formed by implanting first ions into the channel of the second region. 5. The method according to claim 4, characterized in that, after the formation of the P well, the method further comprises: covering the third region with photoresist, the third region being located in the channel of the second region; forming an N well in a region of the channel in the second region except for the third region by implanting second ions into the channel in the second region; removing the photoresist in the third region; Adding a dielectric layer on the surface of the first region and the second region; Etching the dielectric layer and the gate oxide layer in the first region according to preset rules; A metal layer is covered on the surface of the first region and the second region. 6. A semiconductor device, comprising: N-type substrate; an epitaxial layer located on the surface of the N-type substrate, wherein the surface of the epitaxial layer includes a first region and a second region; A field oxide layer is formed on the surface of the epitaxial layer corresponding to the second region. 7. The device of claim 6, further comprising: a gate oxide layer formed on the surfaces of the first region and the second region except the fourth region, wherein the fourth region is located in the channel of the second region, and the channel of the second region is located in the first region . 8. The device of claim 7, further comprising: A polysilicon layer is formed on the surface of the gate oxide layer except the channel in the second region. 9. The apparatus of claim 8, further comprising: A dielectric layer is formed on the surfaces of the first region and the second region except the fourth region. 10. The apparatus of claim 9, further comprising: a metal layer covering the first area and the second area.

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