CN103632957A - Manufacturing method for semiconductor chip first layer metal barrier layer - Google Patents
Manufacturing method for semiconductor chip first layer metal barrier layer Download PDFInfo
- Publication number
- CN103632957A CN103632957A CN201210302580.0A CN201210302580A CN103632957A CN 103632957 A CN103632957 A CN 103632957A CN 201210302580 A CN201210302580 A CN 201210302580A CN 103632957 A CN103632957 A CN 103632957A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor chip
- metal barrier
- barrier layer
- titanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000004888 barrier function Effects 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000010936 titanium Substances 0.000 claims abstract description 23
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010937 tungsten Substances 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910000906 Bronze Inorganic materials 0.000 claims description 9
- 239000010974 bronze Substances 0.000 claims description 9
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 5
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 88
- 238000010586 diagram Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910016570 AlCu Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method for a semiconductor chip first layer metal barrier layer. The method comprises the following steps: filling tungsten in a trench filled with a medium in a silicon substrate; depositing a titanium layer; depositing a titanium nitride layer; performing rapid heat annealing and depositing an aluminum copper layer; depositing the titanium layer again; and depositing the titanium nitride layer again. The manufacture method for the semiconductor chip first layer metal barrier layer can prevent the titanium layer and the titanium nitride layer in the semiconductor chip first layer metal barrier layer from generating peeling phenomena with the aluminum copper layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the manufacture method on a kind of semiconductor chip first layer metal barrier layer.
Background technology
The Metal-1 Layer(first layer metal barrier layer of semiconductor chip) structure is by Ti(titanium) layer, TiN(titanium nitride) layer, AlCu(aluminum bronze) layer, Ti layer, TiN layer sequentially form; Wherein the Ti of lower floor layer (i.e. the Ti layer adjacent with filled media) is as adhesive linkage, and TiN layer prevents the material phase counterdiffusion of levels as interlayer, and prevents Al(aluminium) electromigration.At present, along with the requirement of different product to Metal-1 Layer resistance value, the Ti of lower floor layer, TiN layer thickness also must be made coupling in various degree, cause the tackness variation between different levels, easily produce " peeling " phenomenon (as shown in Figure 1, be that Ti layer, TiN layer and AlCu layer fail effectively to stick together), and cause the electromigratory ability variation of semiconductor chip.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of manufacture method that can avoid the semiconductor chip first layer metal barrier layer of titanium layer, titanium nitride layer and aluminum bronze layer generation " peeling " phenomenon in semiconductor chip first layer metal barrier layer.
For solving the problems of the technologies described above, the manufacture method on semiconductor chip first layer metal of the present invention barrier layer, comprising:
(1) in the groove of silicon substrate filled media, fill tungsten;
(2) deposit titanium layer;
(3) deposit titanium nitride layer;
(4) rapid thermal annealing
(5) deposit aluminum bronze layer;
(6) deposit titanium layer again;
(7) deposit titanium nitride layer again.
Manufacture of the present invention increases rapid thermal annealing after being placed on step (3), and rapid thermal annealing is a kind of various energy, very wide annealing process of annealing time scope of adopting.By the processing of this annealing process, can improve the state on titanium layer/titanium nitride layer surface, thereby improve the tackness on titanium layer/titanium nitride layer surface, improve " peeling " phenomenon; By analogue simulation, experimental verification, manufacture method of the present invention can also reduce electromigration, improves the reliability of semiconductor chip.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is that prior art is manufactured the analogous diagram that semiconductor chip first layer metal barrier layer produces " peeling " phenomenon.
Fig. 2 is the flow chart of manufacture method of the present invention.
Fig. 3 is the partial structurtes schematic diagram on semiconductor chip first layer metal barrier layer.
Fig. 4 is the analogous diagram on existing manufacture semiconductor chip first layer metal barrier layer.
Fig. 5 is the analogous diagram that manufacture method of the present invention is manufactured semiconductor chip first layer metal barrier layer.
Fig. 6 is the experimental result schematic diagram on existing manufacture semiconductor chip first layer metal barrier layer, has shown " peeling " phenomenon.
Fig. 7 is the experimental result schematic diagram that manufacture method of the present invention is manufactured semiconductor chip first layer metal barrier layer, shows " peeling " phenomenon does not occur.
Fig. 8 adopts the present invention and existing manufacture method to manufacture the electromigration logarithm normal distribution comparison diagram on semiconductor chip first layer metal barrier layer, by slope and the linearity, completes fit line.
Reference numeral
The 1st, aluminum bronze layer
The 2nd, titanium nitride layer
The 3rd, titanium layer
The 4th, filled media
The 5th, groove
A is the electromigration logarithm normal distribution fit line that manufacture method of the present invention is manufactured semiconductor chip first layer metal barrier layer
B is the electromigration logarithm normal distribution fit line that existing manufacture method is manufactured semiconductor chip first layer metal barrier layer.
Embodiment
As shown in Figure 2, the manufacture method on semiconductor chip first layer metal of the present invention barrier layer, comprising:
(1) in the groove of silicon substrate filled media, fill tungsten;
(2) deposit titanium layer;
(3) deposit titanium nitride layer;
(4) rapid thermal annealing
(5) deposit aluminum bronze layer;
(6) deposit titanium layer again;
(7) deposit titanium nitride layer again.
As shown in Figure 4, Figure 5, can clearly show that the tackness that increases semiconductor chip first layer metal barrier layer titanium layer after rapid thermal anneal step, titanium nitride layer and aluminum bronze layer obviously increases, there is not " peeling " phenomenon in the device of the manufacture after rapid thermal annealing.
As shown in Figure 6, adopting the experimental result on existing manufacture semiconductor chip first layer metal barrier layer to show, do not increase rapid thermal anneal step, there is " peeling " phenomenon in the not strong device of titanium layer, titanium nitride layer and aluminum bronze layer tackness.
As shown in Figure 7, the experimental result that adopts manufacture method of the present invention to manufacture semiconductor chip first layer metal barrier layer shows not generation " peeling " phenomenon, and after increase rapid thermal anneal step, the tackness of titanium layer, titanium nitride layer and aluminum bronze layer obviously increases.
As shown in Figure 8, adopt respectively the inventive method, existing manufacture method to manufacture semiconductor chip first layer metal barrier layer, electromigration logarithm normal distribution is completed to fit line by slope and the linearity; Wherein, A adopts manufacture method of the present invention to manufacture the fit line on semiconductor chip first layer metal barrier layer; B adopts existing manufacture method to manufacture the fit line on semiconductor chip first layer metal barrier layer; From this figure, can draw and adopt manufacture method increase of the present invention soon as after thermal annealing, can reduce electromigration, improve the reliability of semiconductor chip, can extend the useful life of semiconductor chip simultaneously.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (1)
1. the manufacture method on semiconductor chip first layer metal barrier layer, comprising:
(1) in the groove of silicon substrate filled media, fill tungsten;
(2) deposit titanium layer;
(3) deposit titanium nitride layer;
(4) deposit aluminum bronze layer;
(5) deposit titanium layer again;
(6) deposit titanium nitride layer again;
It is characterized in that: between step (3) and (4), also there is step (A) rapid thermal annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210302580.0A CN103632957A (en) | 2012-08-23 | 2012-08-23 | Manufacturing method for semiconductor chip first layer metal barrier layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210302580.0A CN103632957A (en) | 2012-08-23 | 2012-08-23 | Manufacturing method for semiconductor chip first layer metal barrier layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103632957A true CN103632957A (en) | 2014-03-12 |
Family
ID=50213860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210302580.0A Pending CN103632957A (en) | 2012-08-23 | 2012-08-23 | Manufacturing method for semiconductor chip first layer metal barrier layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103632957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109132995A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | TiAlN thin film lithographic method applied to MEMS device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030022507A1 (en) * | 2001-05-07 | 2003-01-30 | Applied Materials, Inc. | CVD TiSiN barrier for copper integration |
| CN1567547A (en) * | 2003-06-12 | 2005-01-19 | 矽统科技股份有限公司 | Modification method of metal layer |
| CN101431058A (en) * | 2007-11-09 | 2009-05-13 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
-
2012
- 2012-08-23 CN CN201210302580.0A patent/CN103632957A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030022507A1 (en) * | 2001-05-07 | 2003-01-30 | Applied Materials, Inc. | CVD TiSiN barrier for copper integration |
| CN1567547A (en) * | 2003-06-12 | 2005-01-19 | 矽统科技股份有限公司 | Modification method of metal layer |
| CN101431058A (en) * | 2007-11-09 | 2009-05-13 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109132995A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | TiAlN thin film lithographic method applied to MEMS device |
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Application publication date: 20140312 |
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