CN103904025A - Method for improving electromigration reliability of metal connection wire - Google Patents
Method for improving electromigration reliability of metal connection wire Download PDFInfo
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- CN103904025A CN103904025A CN201410111284.1A CN201410111284A CN103904025A CN 103904025 A CN103904025 A CN 103904025A CN 201410111284 A CN201410111284 A CN 201410111284A CN 103904025 A CN103904025 A CN 103904025A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53261—Refractory-metal alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method for improving electromigration reliability of a metal connection wire. The method comprises the steps of providing a semi-conductor substrate, depositing a first medium layer on the semi-conductor substrate, and forming a first metal layer in the first medium layer through the single Damascus technology; depositing a first barrier layer on the first medium layer, forming a groove through etching, and exposing a the first metal layer; forming a first metal protective layer and filling the groove with the first metal protective layer; depositing a second medium layer, and forming a second metal layer on the second medium layer through the second Damascus technology; then forming a second metal protective layer and a sub-sequent metal layer and metal protective layer. The metal layers are covered with the metal protective layers to effectively improve adhesiveness of the surfaces of metal, particularly adhesiveness of the surface of copper, the diffusion phenomenon at the interface position of the upper surface of the metal and the barrier layer is depressed, and electromigration reliability of the metal connection wire can be effectively improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field thereof, particularly a kind of method that improves metal connecting line electromigration reliability.
Background technology
Along with the development of very large scale integration technology, characteristic size constantly reduces, chip integration is also more and more higher, cause current density on metal connecting line sharply to rise, chip unit are power consumption increases, therefore, the reliability of metal connecting line is that integrated circuit is manufactured the major issue that field is concerned about always.
In 45nm and following technique, refer to resistance in order to reduce back segment interconnection RC(R, C refers to electric capacity) postpone, copper/medium with low dielectric constant (low k dielectric) system replaces traditional aluminium/silica system gradually becomes industry main flow.Compared with interconnecting with traditional aluminium, copper-connection has many advantages, for example: the resistivity of copper is less; The parasitic capacitance of copper interconnecting line is less than aluminum interconnecting; The resistance of copper interconnecting line is little, makes power dissipation ratio aluminium on copper interconnecting line interconnect little; The deelectric transferred rate of copper is better than aluminium, can not produce interconnection cavity because of electromigration, has improved the reliability of device.The advantages such as therefore,, compared with traditional interconnection system, copper/medium with low dielectric constant has that the metal interconnecting wires number of plies is few, chip speed is high, low in energy consumption, low cost of manufacture, high resistance electromobility.
Although compared with aluminium interconnection, copper-connection electromigration (Electro-Migration is called for short EM) phenomenon is greatly improved, it is still an important integrity problem.Research shows, the failure mechanism of copper and aluminium different.In aluminium interconnection, main diffusion way is crystal boundary diffusion, and in copper-connection, prevailing diffusion is interfacial diffusion, and the interface between copper upper surface and dielectric passivation is the topmost diffusion path of electromigration.
Therefore, how to suppress the diffusion of copper atom along interface, the electromigration lifetime that improves copper interconnecting line is the technical problem that those skilled in the art need solution badly.
Summary of the invention
The object of the present invention is to provide a kind of method that improves metal connecting line electromigration reliability, solve the interfacial diffusion phenomenon between copper upper surface and dielectric passivation, improve the problem of copper electromigration invalidation.
Technical scheme of the present invention is a kind of method that improves metal connecting line electromigration reliability, comprises the following steps:
S1: semi-conductive substrate is provided, deposits first medium layer thereon, form the first metal layer in described first medium layer;
S2: deposit the first barrier layer on described first medium layer, form groove by etching, expose described the first metal layer;
S3: form the first coat of metal and fill described groove;
S4: the body structure surface deposition second medium layer forming at S3 forms the second metal level on described second medium layer.
Further, described first medium layer and second medium layer are advanced low-k materials.
Further, the material of described first medium layer and second medium layer is SiOCH.
Further, adopt chemical vapor deposition method deposition first medium layer, second medium layer and the first barrier layer.
Further, adopt single Damascus technics to form the first metal layer, adopt dual damascene process to form the second metal level.
Further, the material of described the first metal layer and the second metal level is copper.
Further, the material on described the first barrier layer is SiN, SiC, SiOC, SiOCN or SiCN.
Further, the material of described the first coat of metal is Ti, TiN, Ta, TaN, W, WN or ZrN, or double-deck Ti/TiN, Ta/TaN or W/WN.
Further, adopt physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process to form the first coat of metal.
Further, form the first coat of metal and carry out planarization afterwards, adopt chemical mechanical milling tech to be ground to the first barrier layer.
Further, after step S4, also comprise: use identical technique to form the second coat of metal and follow-up metal level and coat of metal.
Inventor finds after deliberation, covers the coat of metal that one deck is thin on copper cash, can effectively improve the adhesion on copper surface, suppresses the diffusion of copper atom along interface, thereby can effectively improve the electromigration lifetime of copper interconnecting line.
Compared with prior art, the present invention has the following advantages:
The present invention, by covering metal protective layer on every layer of metal level, effectively improves the adhesion of metal surface, the especially adhesion on copper surface, and the diffusion phenomena of inhibition metallic upper surface and interface, barrier layer, effectively improve the electromigratory reliability of metal connecting line.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that improves metal connecting line electromigration reliability in one embodiment of the invention.
Fig. 2～7 are for improving each step structural representation of the method for metal connecting line electromigration reliability in one embodiment of the invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and in the time that example of the present invention is described in detail in detail, for convenience of explanation, schematic diagram does not amplify according to general ratio is local, should be to this as restriction of the present invention.
Core concept of the present invention is: covering metal protective layer on every layer of metal level, the diffusion phenomena of inhibition metallic upper surface and interface, barrier layer, effectively improve the electromigratory reliability of metal connecting line.
Fig. 1 is the method flow diagram that improves metal connecting line electromigration reliability in one embodiment of the invention, and as shown in Figure 1, the present invention proposes a kind of method that improves metal connecting line electromigration reliability, comprises the following steps:
Step S1: semi-conductive substrate is provided, deposits first medium layer thereon, form the first metal layer in described first medium layer;
Step S2: deposit the first barrier layer on described first medium layer, form groove by etching, expose described the first metal layer;
Step S3: form the first coat of metal and fill described groove;
Step S4: the body structure surface deposition second medium layer forming at S3 forms the second metal level on described second medium layer;
Step S5: adopt identical processing step, form the second coat of metal and follow-up metal level and coat of metal.
Fig. 2～7, for improving each step structural representation of the method for metal connecting line electromigration reliability in one embodiment of the invention, please refer to shown in Fig. 1, and in conjunction with Fig. 2～Fig. 7, describe the method for the raising metal connecting line electromigration reliability of the present invention's proposition in detail:
In step S1, Semiconductor substrate 00 is provided, in described Semiconductor substrate 00, deposition forms first medium layer 10, and at the interior formation the first metal layer 11 of described first medium layer 10, forms the structure shown in Fig. 2.
Described Semiconductor substrate 00 can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI) in the present embodiment, or well known to a person skilled in the art other Semiconductor substrate, can be also the substrate that is formed with semiconductor device.Adopt chemical vapor deposition method to deposit in described Semiconductor substrate 00 and form first medium layer 10, described first medium layer 10 is advanced low-k materials, for example: SiOCH, on described first medium layer 10, form silicon dioxide layer of protection, for the protection of first medium layer 10, this silicon dioxide layer of protection is removed in follow-up technique, also not shown in Fig. 2; Same, adopt the method for chemical vapour deposition (CVD) to form described silicon dioxide layer of protection.
Then adopt single Damascus etching technics etching silicon dioxide protective layer and first medium layer 10; form groove; utilize physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process; the first barrier metal layer is formed on sidewall and bottom at groove; finally adopt Cu electroplating technique to electroplate in groove and fill metallic copper; then utilize chemical mechanical milling tech to carry out planarization to metallic copper, form the first metal layer 11, in Fig. 2, do not distinguish metal barrier and metallic copper.In the present embodiment, the material of the described the first metal layer 11 of formation is copper, in other embodiments, also can adopt other metal.
In step S2, on described first medium layer 10, deposit the first barrier layer 12, form groove 13 by exposure and etching, expose described the first metal layer 11, form structure as shown in Figure 3.
Adopt the method for chemical vapour deposition (CVD) on described first medium layer 10, to form the first barrier layer 12, the material on described the first barrier layer 12 is SiN, SiC, SiOC, SiOCN or SiCN.Adopt single Damascus etching technics, the first barrier layer 12, to described first medium layer 10, forms groove 13 described in etching, and the position of described groove 13 is consistent with described the first metal layer 11, and described groove 13 exposes the upper surface of described the first metal layer 11.
In step S3, form the first coat of metal 14 and fill described groove 13, form structure as shown in Figure 4.
In the present embodiment; adopt physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process on remaining the first barrier layer 12 and in described groove 13, deposit the first coat of metal 14; the material of described the first coat of metal 14 is Ti, TiN, Ta, TaN, W, WN or ZrN, or described the first coat of metal 14 can be also double-deck Ti/TiN, Ta/TaN or W/WN.Then carry out planarization, adopt chemical mechanical milling tech to carry out planarization to described the first coat of metal 14, be ground on described the first barrier layer 12.
Described the first coat of metal 14 covers on described the first metal layer 11, effectively improves the adhesion on the first metal layer 11 surfaces, suppresses the diffusion phenomena on the first metal layer 11 upper surfaces and the first barrier layer 12, effectively improves the electromigratory reliability of metal connecting line.
In step S4, the device architecture surface deposition second medium layer 20 forming in step S3 forms the second metal level 21 on described second medium layer 20, forms structure as shown in Figure 5.
S1 is similar with step, adopt chemical vapor deposition method to deposit on described the first barrier layer 14 and form second medium layer 20, described second medium layer 20 is identical with described first medium layer 10, for advanced low-k materials, for example: SiOCH forms silicon dioxide layer of protection, for the protection of second medium layer 20 on described second medium layer 20, this silicon dioxide layer of protection is removed in follow-up technique, also not shown in Fig. 5; Same, adopt the method for chemical vapour deposition (CVD) to form described silicon dioxide layer of protection.
Then adopt dual damascene etching technics etching silicon dioxide protective layer and second medium layer 20 upper surface to described the first metal layer 11, to form copper interconnecting line through hole and groove, utilize physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process, the first barrier metal layer and copper seed layer are formed on sidewall and bottom at copper interconnecting line through hole and groove, finally adopt Cu electroplating technique to electroplate and fill metallic copper, then utilize chemical mechanical milling tech to carry out planarization to metallic copper, form the second metal level 21, in Fig. 5, do not distinguish metal barrier and metallic copper.In the present embodiment, the material of described second metal level 21 of formation is copper, in other embodiments, also can adopt other metal.
In step S5, adopt processing step same as described above, form the second coat of metal and follow-up metal level and coat of metal, as shown in Figure 6 and Figure 7.
The processing step that forms the second coat of metal 24 is similar with the processing step that forms the first coat of metal 14:
First, adopt the method for chemical vapour deposition (CVD) on described second medium layer 20, to form the second barrier layer 22, the material on described the second barrier layer 22 is identical with described the first barrier layer 12, is SiN, SiC, SiOC, SiOCN or SiCN.Adopt single Damascus etching technics, described in etching, the second barrier layer 22, to described the second metal level 21, forms groove 23, and the position of described groove 23 is consistent with described the second metal level 21, described groove 23 exposes described the second metal level 21, forms structure as shown in Figure 6.
Then; adopt physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process on remaining the second barrier layer 22 and in described groove 23, deposit the second coat of metal 24; the material of described the second coat of metal 24 is Ti, TiN, Ta, TaN, W, WN or ZrN, or described the second coat of metal 24 can be also double-deck Ti/TiN, Ta/TaN or W/WN.Then carry out planarization, adopt chemical mechanical milling tech to carry out planarization to described the second coat of metal 24, be ground on described the second barrier layer 22.
Described the second coat of metal 24 covers on described the second metal level 21; effectively improve the adhesion on the second metal level 21 surfaces; the diffusion phenomena that suppress the second metal level 21 upper surfaces and 22 interfaces, the second barrier layer, effectively improve the electromigratory reliability of metal connecting line.
Then, adopt just as technique complete metal level and the coat of metal of the follow-up requirement such as the 3rd metal level, the 3rd coat of metal.
It should be noted that, in the present embodiment, the material of described the first metal layer, the second metal level and follow-up metal level is copper, what be that the present invention mainly solves is the interfacial diffusion phenomenon between copper surface and the dielectric passivation of copper interconnecting line, improve the problem of copper electromigration invalidation, but, can be applied to too on other metal connecting lines of Similar Problems.
In sum; the present invention, by covering metal protective layer on every layer of metal level, effectively improves the adhesion of metal surface, especially the adhesion on copper surface; the diffusion phenomena that suppress metallic upper surface and interface, barrier layer, effectively improve the electromigratory reliability of metal connecting line.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (11)
1. a method that improves metal connecting line electromigration reliability, is characterized in that, comprises the following steps:
S1: semi-conductive substrate is provided, deposits first medium layer thereon, form the first metal layer in described first medium layer;
S2: deposit the first barrier layer on described first medium layer, form groove by etching, expose described the first metal layer;
S3: form the first coat of metal and fill described groove;
S4: the body structure surface deposition second medium layer forming at S3 forms the second metal level on described second medium layer.
2. the method for raising metal connecting line electromigration reliability as claimed in claim 1, is characterized in that, described first medium layer and second medium layer are advanced low-k materials.
3. the method for raising metal connecting line electromigration reliability as claimed in claim 2, is characterized in that, the material of described first medium layer and second medium layer is SiOCH.
4. the method for raising metal connecting line electromigration reliability as claimed in claim 3, is characterized in that, adopts chemical vapor deposition method deposition first medium layer, second medium layer and the first barrier layer.
5. the method for raising metal connecting line electromigration reliability as claimed in claim 1, is characterized in that, adopts single Damascus technics to form the first metal layer, adopts dual damascene process to form the second metal level.
6. the method for raising metal connecting line electromigration reliability as claimed in claim 5, is characterized in that, the material of described the first metal layer and the second metal level is copper.
7. the method for raising metal connecting line electromigration reliability as claimed in claim 1, is characterized in that, the material on described the first barrier layer is SiN, SiC, SiOC, SiOCN or SiCN.
8. the method for raising metal connecting line electromigration reliability as claimed in claim 1, is characterized in that, the material of described the first coat of metal is Ti, TiN, Ta, TaN, W, WN or ZrN, or double-deck Ti/TiN, Ta/TaN or W/WN.
9. the method for raising metal connecting line electromigration reliability as claimed in claim 8, is characterized in that, adopts physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process to form the first coat of metal.
10. the method for raising metal connecting line electromigration reliability as claimed in claim 9, is characterized in that, forms the first coat of metal and carries out planarization afterwards, adopts chemical mechanical milling tech to be ground to the first barrier layer.
The method of 11. raising metal connecting line electromigration reliabilities as described in any one in claim 1 to 10, is characterized in that, also comprises: use identical technique to form the second coat of metal and follow-up metal level and coat of metal after step S4.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105808807A (en) * | 2014-12-31 | 2016-07-27 | 新思科技有限公司 | Electro-migration verification for advanced semiconductor technology |
| CN106409754A (en) * | 2015-07-29 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN109385651A (en) * | 2018-12-05 | 2019-02-26 | 上海华力集成电路制造有限公司 | The method of the groove of copper filling |
| CN115274594A (en) * | 2022-09-19 | 2022-11-01 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2023024233A1 (en) * | 2021-08-27 | 2023-03-02 | 长鑫存储技术有限公司 | Semiconductor structure, method for manufacturing semiconductor structure, and memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105808807A (en) * | 2014-12-31 | 2016-07-27 | 新思科技有限公司 | Electro-migration verification for advanced semiconductor technology |
| CN106409754A (en) * | 2015-07-29 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN109385651A (en) * | 2018-12-05 | 2019-02-26 | 上海华力集成电路制造有限公司 | The method of the groove of copper filling |
| WO2023024233A1 (en) * | 2021-08-27 | 2023-03-02 | 长鑫存储技术有限公司 | Semiconductor structure, method for manufacturing semiconductor structure, and memory |
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