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CN103632939A - Method for optimizing top rounded corner of power device groove - Google Patents

Method for optimizing top rounded corner of power device groove Download PDF

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Publication number
CN103632939A
CN103632939A CN201210289589.2A CN201210289589A CN103632939A CN 103632939 A CN103632939 A CN 103632939A CN 201210289589 A CN201210289589 A CN 201210289589A CN 103632939 A CN103632939 A CN 103632939A
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oxide layer
trench
layer
silicon nitride
silicon substrate
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斯海国
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0289—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes

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Abstract

本发明公开了一种优化功率器件沟槽顶部圆角的方法，在硅衬底上依次形成衬垫氧化层和氮化硅层；在沟槽形成后对已经形成的器件结构进行热氧化；去除所述氮化硅层和衬垫氧化层；用各向同性气体对所述沟槽进行处理，将沟槽的边角修圆；在所述硅衬底的表面和沟槽的内表面生长一层牺牲氧化层，然后再去除该牺牲氧化层，进一步将所述沟槽的边角修圆；在所述硅衬底的表面和沟槽的内表面生长一层隔离用的栅氧化层；在所述硅衬底上端的栅氧化层上和沟槽中淀积并回刻栅电极多晶硅；在所述硅衬底上端的栅氧化层上和沟槽内栅电极多晶硅的上端淀积隔离层。本发明能够改善沟槽顶部拐角的曲率半径，从而使器件的栅氧化层有更好的均匀性和可靠性。

Figure 201210289589

The invention discloses a method for optimizing the fillet at the top of a trench of a power device. A pad oxide layer and a silicon nitride layer are sequentially formed on a silicon substrate; after the formation of the trench, the formed device structure is thermally oxidized; The silicon nitride layer and the pad oxide layer; treating the trench with an isotropic gas to round the corners of the trench; growing a silicon nitride layer on the surface of the silicon substrate and the inner surface of the trench layer a sacrificial oxide layer, and then remove the sacrificial oxide layer to further round the corners of the trench; grow a gate oxide layer for isolation on the surface of the silicon substrate and the inner surface of the trench; Depositing and etching back gate electrode polysilicon on the gate oxide layer at the upper end of the silicon substrate and in the trench; depositing an isolation layer on the gate oxide layer at the upper end of the silicon substrate and at the upper end of the gate electrode polysilicon in the trench. The invention can improve the curvature radius of the top corner of the groove, so that the gate oxide layer of the device has better uniformity and reliability.

Figure 201210289589

Description

The method of optimizing power device trenches top fillet
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to the method for a kind of optimizing power device trenches top fillet.
Background technology
Slot type power device is because its ducting capacity is strong, and power consumption is little, little many advantages, gradually the success rate device main flow of waiting of chip area.As everyone knows, the gate insulation quality of slot type power device, particularly deep slot type power device not as planar device good.This is because the corner processing of groove is good not, causes quality of gate oxide uniformity not as planar power device.And such defect tends to cause some integrity problems of power device itself.
Due to trench etch process, often more sharp-pointed at the turning at groove top.After gate insulation layer growth finishes, also can experience some complicated thermal processs, and etching process, can make the quality of oxide layer of this part poor, easy fracture etc.By encapsulating the chip of rear test, in reliability of the gate oxide test process, due to the quality of gate oxide defect of groove top corner, can first puncture herein, affect device and use (referring to Fig. 1).In Fig. 1, by failure analysis, navigate to obtain gate oxide leakage, groove top oxide layer is too small because of radius of curvature, causes fracture, thereby brings gate oxide electric leakage or lowly puncture inefficacy.
Summary of the invention
The technical problem to be solved in the present invention is to provide the method for a kind of optimizing power device trenches top fillet, can improve the radius of curvature of groove top corner, thereby makes the gate oxide of device have better uniformity and reliability.
For solving the problems of the technologies described above, the method for optimizing power device trenches of the present invention top fillet, comprises the steps:
Step 1, on silicon substrate, form successively cushion oxide layer and silicon nitride layer;
Step 2, at described silicon nitride layer surface-coated photoresist, by one deck light shield, define the pattern of groove, adopt the method for dry etching, silicon nitride layer and cushion oxide layer described in etching;
Step 3, remove described photoresist, and by described silicon nitride layer and cushion oxide layer as hard etching barrier layer, silicon substrate described in dry etching, forms groove;
Wherein, also comprise:
Step 4, the device architecture having formed is carried out to thermal oxidation after above-mentioned steps is processed;
Step 5, remove described silicon nitride layer and cushion oxide layer;
Step 6, with isotropism gas, described groove is processed, by the corner cavetto of groove;
Step 7, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further by the corner cavetto of described groove;
Step 8, at the gate oxide of the surface of described silicon substrate and the inner surface of groove growth one deck isolation use;
Step 9, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
Step 10, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
The another kind of technical scheme that the method for optimizing power device trenches of the present invention top fillet adopts, comprises the steps:
The first step, on silicon substrate, form successively cushion oxide layer and silicon nitride layer;
Second step, at described silicon nitride layer surface-coated photoresist, by photoetching, define with photoresist the figure of groove, adopt dry etching to carve and wear described silicon nitride layer;
The 3rd step, remove described photoresist, and the device architecture having formed after above-mentioned steps is processed is carried out to thermal oxidation;
The 4th step, using described silicon nitride layer as hard light shield, etching oxidation layer; Using described silicon nitride layer or oxide layer as hard light shield again, and silicon substrate described in dry etching, forms groove;
The 5th step, remove described silicon nitride layer and oxide layer; Described groove is waited to tropism's gas etching, by the corner cavetto of described groove;
The 6th step, at the surface of described silicon substrate and the inner surface of groove growth one deck sacrificial oxide layer, and then remove this sacrificial oxide layer, further the corner cavetto of groove;
The 7th step, at the gate oxide of the surface of described silicon substrate and the inner surface of groove growth one deck isolation use;
The 8th step, deposit return to carve gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove;
The 9th step, the upper end deposit separator of gate electrode polysilicon on the gate oxide of described silicon substrate upper end and in groove.
The present invention is by the optimization to groove processing technique, at groove top, carry out partial thermal oxidation, thereby in groove making, good processing has been carried out in groove top, the radius of curvature of groove top corner is improved, thereby improve the grid reliability of the power device of groove structure, as the test of HTGB(high temp. grate bias voltage) ability, maintain other performances of device (as puncture voltage, conducting resistance) constant simultaneously; Better solved the ubiquitous grid of the power device source electric leakage problem of groove structure.
The present invention can be for trench gate IGBT(insulated gate bipolar transistor), the groove of the slot type power device such as MOS (metal-oxide layer-semiconductor) processes.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the gate oxide leakage slice map of failure analysis location;
Fig. 2 has applied ambipolar "off" transistor structural representation of insulated trench grid of the present invention;
Fig. 3 is traditional ambipolar "off" transistor structural representation of insulated trench grid;
Fig. 4 is the silicon chip schematic diagram of preparing;
Fig. 5 is deposit cushion oxide layer schematic diagram;
Fig. 6 is deposit silicon nitride layer schematic diagram;
Fig. 7 is the pattern schematic diagram that defines groove;
Fig. 8 forms groove schematic diagram;
Fig. 9 is the schematic diagram carrying out after thermal oxidation;
Figure 10 is the schematic diagram of removing silicon nitride layer and cushion oxide layer;
Figure 11 is the schematic diagram after groove being processed with isotropism gas;
Figure 12 is the schematic diagram of growth one deck sacrificial oxide layer;
Figure 13 is the schematic diagram of removing after sacrificial oxide layer;
Figure 14 is the schematic diagram after the gate oxide of growth isolation use;
Figure 15 is the schematic diagram after deposit gate electrode polysilicon;
Figure 16 is back to carve the schematic diagram after gate electrode polysilicon;
Figure 17 is the schematic diagram after deposit separator;
Figure 18 is the pictorial diagram that defines with photoresist groove;
Figure 19 removes photoresist schematic diagram;
Figure 20 is the schematic diagram carrying out after thermal oxidation;
Figure 21 is the schematic diagram after etching oxidation layer;
Figure 22 is the schematic diagram forming after groove;
Figure 23 is the schematic diagram of removing after silicon nitride layer and oxide layer.
Embodiment
Embodiment mono-
The method of described optimizing power device trenches top fillet comprises the steps:
Step 1, shown in Figure 4, prepares a slice silicon chip 1, and its thickness, resistivity, pre-treatment etc. are determined by device property and designing requirement.Described pre-treatment comprises the processing that the design of the devices such as making of terminal own is wanted.
Step 2, shown in Figure 5, in the cushion oxide layer 2 of the employing chemical vapor deposition (CVD) of the surface of described silicon chip 1 or heat growth one deck suitable thickness, the thickness of this cushion oxide layer 2 can be arrive etc., by required beak pattern, do not determined.
Step 3, shown in Figure 6 after step 2 completes, adopts the silicon nitride layer 3 of chemical vapor deposition (CVD) one deck suitable thickness in described cushion oxide layer 2, and the thickness of this silicon nitride layer 3 can be
Figure BDA00002012761100063
arrive
Figure BDA00002012761100064
etc., specifically by required beak pattern, do not determined.
Step 4, shown in Figure 7 applies photoresist 4 on described silicon nitride 3 surfaces, defines the pattern of groove 5 by one deck light shield, adopts the method for dry etching, silicon nitride layer 3 and the cushion oxide layer 2 on silicon chip 1 surface described in etching.
Step 5, shown in Figure 8, removes photoresist 4, and by silicon nitride layer 3 and cushion oxide layer 2 as hard etching barrier layer, silicon chip 1 described in dry etching, formation groove 5.
Step 6, shown in Figure 9, carries out thermal oxidation to the device architecture having formed after above-mentioned steps is processed, and mode of oxidizing can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.Through this step process, form oxide layer beak region 6-1 and sacrificial oxide layer 6-2.
Step 7, shown in Figure 10, removes described silicon nitride 3 and cushion oxide layer 2.
Step 8, shown in Figure 11, carries out preliminary treatment with isotropism gas to described groove 5, by the corner cavetto of groove 5.
Step 9, shown in Figure 12, at the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck sacrificial oxide layer, and then removes this sacrificial oxide layer, further the corner cavetto of groove 5, as shown in figure 13.
Step 10, shown in Figure 14, at the gate oxide 7 of the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck isolation use.
Step 11, referring to shown in Figure 15,16, deposit return to carve gate electrode polysilicon 8 on the gate oxide 7 of described silicon chip 1 upper end and in groove 5.
Step 12, shown in Figure 17, on the gate oxide 7 of described silicon chip 1 upper end and the upper end deposit separator 9 of the interior gate electrode polysilicon 8 of groove 5, then makes electrode.
Embodiment bis-
The method of described optimizing power device trenches top fillet comprises the steps:
Step 1, shown in Figure 4, prepares a slice silicon chip 1, and its thickness, resistivity, pre-treatment etc. are determined by device property and designing requirement.
Step 2, shown in Figure 5, in the cushion oxide layer 2 of surface deposition one deck suitable thickness of described silicon chip 1, the thickness of this cushion oxide layer 2 can be
Figure BDA00002012761100071
arrive
Figure BDA00002012761100072
etc., by required beak pattern, do not determined.
Step 3, shown in Figure 6, the silicon nitride layer 3 of deposit one deck suitable thickness in described cushion oxide layer 2, the thickness of this silicon nitride layer 3 can be
Figure BDA00002012761100073
arrive
Figure BDA00002012761100074
etc., specifically by required beak pattern, do not determined.
Step 4, shown in Figure 18 applies photoresist 4 on the surface of described silicon nitride layer 3, by the photoetching figure of 4 definition grooves 5 with photoresist, adopts dry etching to carve and wears described silicon nitride layer 3.
Step 5, shown in Figure 19, removes photoresist 4.
Step 6, shown in Figure 20, carries out thermal oxidation to the device architecture having formed after above-mentioned steps is processed, and mode of oxidizing can be dry method, can be also wet method, can also be the combination that dry method adds wet method, and oxidizing temperature and time determine according to the design of device.
Step 7, ginseng as shown in Figure 21, are usingd described silicon nitride layer 3 as hard light shield, etching oxidation layer 2.
Step 8, ginseng as shown in Figure 22, are usingd described silicon nitride layer 3 or oxide layer 2 as hard light shield, and dry etching silicon slice 1, forms groove 5.
Step 9, ginseng as shown in Figure 23, are removed described silicon nitride and are surveyed layer 3 and oxide layer 2.
Step 10, shown in Figure 11, carries out isotropism gas etching to described groove 5, by the corner cavetto of groove 5.
Step 11, shown in Figure 12, at superficial growth one deck sacrificial oxide layer of described silicon chip 1 and groove 5, and then removes this sacrificial oxide layer, further the corner cavetto of groove 5, as shown in figure 13.
Step 12, shown in Figure 14, at the gate oxide 7 of the surface of described silicon chip 1 and the inner surface of groove 5 growth one deck isolation use.
Step 13, referring to shown in Figure 15,16, deposit return to carve gate electrode polysilicon 8 on the gate oxide 7 of described silicon chip 1 upper end and in groove 5.
Step 14, on the gate oxide 7 of described silicon chip 1 upper end and the upper end deposit separator 9 of the interior gate electrode polysilicon 8 of groove 5, then make electrode.
Ambipolar the "off" transistor structure of insulated trench grid that adopts said method to make is shown in Figure 2, and Fig. 3 is traditional ambipolar "off" transistor structure of insulated trench grid.Wherein, 11 is P type doped region, and 12 is N-type doped region, 13 is gate oxide, the gate oxide corner region of 13a for adopting method of the present invention to form, and 13b is traditional gate oxide corner region, 14 is spacer medium layer, and 15 is polygate electrodes, and 16 is electric field cutoff layer, 17 is P type doped region, 18a is collector electrode metal electrode, and 18b is emitter metal electrode, and E is emitter, C is collector electrode, and G is gate electrode.By the gate oxide corner region 13a through optimizing that adopts method of the present invention to form in comparison diagram 2, and traditional without the gate oxide corner region of optimizing in Fig. 3, the gate oxide stability that can visually see, has very large advantage.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.For example in some device design aspect contents, can intert in groove forming process described in the invention; as long as groove is made partly identical with the present invention; or without departing from the principles of the present invention, the distortion of doing and improvement, all should be considered as protection scope of the present invention.

Claims (10)

1.一种优化功率器件沟槽顶部圆角的方法，包括如下步骤：1. A method for optimizing the top fillet of a trench of a power device, comprising the steps of: 步骤一、在硅衬底上依次形成衬垫氧化层和氮化硅层；Step 1, sequentially forming a pad oxide layer and a silicon nitride layer on the silicon substrate; 步骤二、在所述氮化硅层表面涂覆光刻胶，通过一层光罩定义出沟槽的图案，采用干法刻蚀的方法，刻蚀所述氮化硅层和衬垫氧化层；Step 2: Coating photoresist on the surface of the silicon nitride layer, defining a groove pattern through a layer of photomask, and etching the silicon nitride layer and pad oxide layer by dry etching ; 步骤三、去除所述光刻胶，并用所述氮化硅层和衬垫氧化层作为硬刻蚀阻挡层，干法刻蚀所述硅衬底，形成沟槽；其特征在于，还包括：Step 3, removing the photoresist, and using the silicon nitride layer and pad oxide layer as a hard etching barrier layer, dry etching the silicon substrate to form a trench; it is characterized in that it also includes: 步骤四、对经上述步骤处理后已经形成的器件结构进行热氧化；Step 4, thermally oxidizing the device structure that has been formed after the above steps; 步骤五、去除所述氮化硅层和衬垫氧化层；Step 5, removing the silicon nitride layer and pad oxide layer; 步骤六、用各向同性气体对所述沟槽进行处理，将沟槽的边角修圆；Step 6, treating the groove with an isotropic gas, and rounding the corners of the groove; 步骤七、在所述硅衬底的表面和沟槽的内表面生长一层牺牲氧化层，然后再去除该牺牲氧化层，进一步将所述沟槽的边角修圆；Step 7, growing a sacrificial oxide layer on the surface of the silicon substrate and the inner surface of the trench, and then removing the sacrificial oxide layer, and further rounding the corners of the trench; 步骤八、在所述硅衬底的表面和沟槽的内表面生长一层隔离用的栅氧化层；Step 8, growing a gate oxide layer for isolation on the surface of the silicon substrate and the inner surface of the trench; 步骤九、在所述硅衬底上端的栅氧化层上和沟槽中淀积并回刻栅电极多晶硅；Step 9, depositing and etching back gate electrode polysilicon on the gate oxide layer at the upper end of the silicon substrate and in the trench; 步骤十、在所述硅衬底上端的栅氧化层上和沟槽内栅电极多晶硅的上端淀积隔离层。Step 10, depositing an isolation layer on the gate oxide layer on the upper end of the silicon substrate and on the upper end of the polysilicon gate electrode in the trench. 2.如权利要求1所述的方法，其特征在于：所述硅衬底的厚度、电阻率和前处理由器件性质和设计要求决定；所述前处理包括终端的制作在内的器件本身设计所需要的处理。2. The method according to claim 1, characterized in that: the thickness, resistivity and pre-treatment of the silicon substrate are determined by the properties of the device and design requirements; the design of the device itself including the making of the terminal in the pre-treatment processing required. 3.如权利要求1所述的方法，其特征在于：所述衬垫氧化层采用化学汽相淀积CVD或热生长形成，该衬垫氧化层的厚度为
Figure FDA00002012761000021
3. The method according to claim 1, wherein the pad oxide layer is formed by chemical vapor deposition (CVD) or thermal growth, and the pad oxide layer has a thickness of
Figure FDA00002012761000021
 4.如权利要求1所述的方法，其特征在于：所述氮化硅层采用化学汽相淀积CVD形成，该氮化硅层的厚度为
Figure FDA00002012761000022
4. method as claimed in claim 1 is characterized in that: described silicon nitride layer adopts chemical vapor deposition CVD to form, and the thickness of this silicon nitride layer is
Figure FDA00002012761000022
 5.如权利要求1所述的方法，其特征在于：所述热氧化方式可以是干法，也可以是湿法，还可以是干法加湿法的组合，氧化温度和时间根据器件的设计决定。5. The method according to claim 1, characterized in that: the thermal oxidation method can be a dry method, a wet method, or a combination of dry and humid methods, and the oxidation temperature and time are determined according to the design of the device . 6.一种优化功率器件沟槽顶部圆角的方法，包括如下步骤：6. A method for optimizing the top fillet of a power device trench, comprising the steps of: 第一步、在硅衬底上依次形成衬垫氧化层和氮化硅层；The first step is to sequentially form a pad oxide layer and a silicon nitride layer on the silicon substrate; 第二步、在所述氮化硅层表面涂覆光刻胶，通过光刻用光刻胶定义沟槽的图形，采用干法刻蚀刻穿所述氮化硅层；其特征在于，还包括：The second step is to coat photoresist on the surface of the silicon nitride layer, define the pattern of the trench with the photoresist by photolithography, and etch through the silicon nitride layer by dry etching; it is characterized in that it also includes : 第三步、去除所述光刻胶，并对经上述步骤处理后已经形成的器件结构进行热氧化；The third step, removing the photoresist, and thermally oxidizing the device structure that has been formed after the above steps; 第四步、以所述氮化硅层作为硬光罩，刻蚀氧化层；再以所述氮化硅层或氧化层作为硬光罩，干法刻蚀所述硅衬底，形成沟槽；The fourth step is to use the silicon nitride layer as a hard mask to etch the oxide layer; then use the silicon nitride layer or the oxide layer as a hard mask to dry etch the silicon substrate to form a trench ; 第五步、去除所述氮化硅层和氧化层；对所述沟槽进行等向性气体刻蚀，将所述沟槽的边角修圆；The fifth step, removing the silicon nitride layer and the oxide layer; performing isotropic gas etching on the trench, and rounding the corners of the trench; 第六步、在所述硅衬底的表面和沟槽的内表面生长一层牺牲氧化层，然后再去除该牺牲氧化层，进一步把沟槽的边角修圆；Step 6, growing a sacrificial oxide layer on the surface of the silicon substrate and the inner surface of the trench, and then removing the sacrificial oxide layer, and further rounding the corners of the trench; 第七步、在所述硅衬底的表面和沟槽的内表面生长一层隔离用的栅氧化层；Step 7, growing a gate oxide layer for isolation on the surface of the silicon substrate and the inner surface of the trench; 第八步、在所述硅衬底上端的栅氧化层上和沟槽中淀积并回刻栅电极多晶硅；The eighth step, depositing and etching back gate electrode polysilicon on the gate oxide layer at the upper end of the silicon substrate and in the trench; 第九步、在所述硅衬底上端的栅氧化层上和沟槽内栅电极多晶硅的上端淀积隔离层。Step 9, depositing an isolation layer on the gate oxide layer on the upper end of the silicon substrate and on the upper end of the polysilicon gate electrode in the trench. 7.如权利要求6所述的方法，其特征在于：所述硅衬底的厚度、电阻率和前处理由器件性质和设计要求决定；所述前处理包括终端的制作在内的器件本身设计所需要的处理。7. The method according to claim 6, characterized in that: the thickness, resistivity and pre-treatment of the silicon substrate are determined by the properties of the device and design requirements; processing required. 8.如权利要求6所述的方法，其特征在于：所述衬垫氧化层采用化学汽相淀积CVD或热生长形成，该衬垫氧化层的厚度为
Figure FDA00002012761000031
8. The method according to claim 6, wherein the pad oxide layer is formed by chemical vapor deposition (CVD) or thermal growth, and the pad oxide layer has a thickness of
Figure FDA00002012761000031
 9.如权利要求6所述的方法，其特征在于：所述氮化硅层采用化学汽相淀积CVD形成，该氮化硅层的厚度为 9. method as claimed in claim 6 is characterized in that: described silicon nitride layer adopts chemical vapor deposition CVD to form, and the thickness of this silicon nitride layer is 10.如权利要求6所述的方法，其特征在于：所述热氧化方式可以是干法，也可以是湿法，还可以是干法加湿法的组合，氧化温度和时间根据器件的设计决定。10. The method according to claim 6, characterized in that: the thermal oxidation method can be a dry method, a wet method, or a combination of dry and humid methods, and the oxidation temperature and time are determined according to the design of the device .
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CN104616982A (en) * 2015-01-13 2015-05-13 株洲南车时代电气股份有限公司 Method for etching trench gate
CN105428407A (en) * 2015-11-16 2016-03-23 株洲南车时代电气股份有限公司 IGBT device and forming method therefor
CN107994076A (en) * 2016-10-26 2018-05-04 深圳尚阳通科技有限公司 The manufacture method of groove grid super node device
CN110137082A (en) * 2018-02-09 2019-08-16 天津环鑫科技发展有限公司 A Method for Optimizing Trench Morphology of Power Devices
CN112447507A (en) * 2019-08-30 2021-03-05 株洲中车时代半导体有限公司 GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics
CN112802742A (en) * 2021-03-24 2021-05-14 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device

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CN104616982A (en) * 2015-01-13 2015-05-13 株洲南车时代电气股份有限公司 Method for etching trench gate
CN105428407A (en) * 2015-11-16 2016-03-23 株洲南车时代电气股份有限公司 IGBT device and forming method therefor
CN105428407B (en) * 2015-11-16 2018-07-13 株洲南车时代电气股份有限公司 A kind of IGBT device and forming method thereof
CN107994076A (en) * 2016-10-26 2018-05-04 深圳尚阳通科技有限公司 The manufacture method of groove grid super node device
CN110137082A (en) * 2018-02-09 2019-08-16 天津环鑫科技发展有限公司 A Method for Optimizing Trench Morphology of Power Devices
CN112447507A (en) * 2019-08-30 2021-03-05 株洲中车时代半导体有限公司 GOI test sample wafer manufacturing method for improving trench gate breakdown characteristics
CN112802742A (en) * 2021-03-24 2021-05-14 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device

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Application publication date: 20140312