CN103630816B - doping failure analysis method - Google Patents
doping failure analysis method Download PDFInfo
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- CN103630816B CN103630816B CN201210296921.8A CN201210296921A CN103630816B CN 103630816 B CN103630816 B CN 103630816B CN 201210296921 A CN201210296921 A CN 201210296921A CN 103630816 B CN103630816 B CN 103630816B
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Abstract
The invention discloses a kind of analysis method adulterated and lost efficacy, including step: provide non-defective unit silicon chip；Non-defective unit silicon chip and testing sample silicon chip are processed until exposing substrate surface；Non-defective unit silicon chip and testing sample silicon chip are placed on base；Selected resolution chart on non-defective unit silicon chip and testing sample silicon chip；It is set for the condition of SRP；Respectively the resolution chart on non-defective unit silicon chip and testing sample silicon chip carried out SRP and obtain the data of resistivity or carrier concentration；Non-defective unit silicon chip and the described resistivity of testing sample silicon chip or the data of carrier concentration are compared, it is judged that whether the doping of testing sample silicon chip lost efficacy, the dopant dose inefficacy size of estimation testing sample silicon chip.The present invention can inefficacy that accurately fast verification doping is relevant, and confirm the difference degree of impurity, the time of chip failure analysis can be greatly saved and guarantee the accuracy of failure analysis, for clear and definite technological reason and promote the yield of Related product and play significant role.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of doping failure analysis side
Method.
Background technology
In semiconductor integrated circuit manufactures, doping is a kind of general technique, often results in last when doping was lost efficacy
The most whether the inefficacy of the chip product formed, judge to adulterate and lost efficacy, and determine that chip produces according to judged result
The inefficacy of product be whether have doping to lose efficacy cause is a kind of important analysis method in chip product failure analysis.Existing
Doping failure analysis method includes:
1, proving the electrical testing of device, the method is by each port of device or electrode are applied electric answering
Power, thus monitor the voltage x current of each electrode etc. and understand characteristic.The method there is the problem that
1.1, device is tested the nano-probe technology needing to use complexity or microprobe analysis used by liner (pad).
Even if 1.2 clear and definite device electrology characteristics are abnormal, still cannot confirm whether component failure is to be caused by doping inefficacy
, because multiple reasons such as component failure is probably by adulterating, etch, be directed at, abnormal Redundant frame cause.
2, the dyeing for dopant species and concentration processes.The method there is the problem that
2.1, dye closely related with the proportioning of dyeing medicinal liquid, time, need repetition test, take time and effort；
2.2, when the abnormal dosage adulterated or concentration difference are less, it is coloured to power and is substantially reduced.
3, SIMS analysis (SIMS).The method there is the problem that analysis is complicated, cost intensive, and
And big to the restriction of sample size, it is embodied in and requires length and width all more than 100 microns.
Summary of the invention
The technical problem to be solved is to provide a kind of analysis method adulterated and lost efficacy, and can accurately mix by fast verification
The inefficacy that dephasign closes, and confirm the difference degree of impurity, the time of chip failure analysis can be greatly saved with true
Protecting the accuracy of failure analysis, the yield for clear and definite technological reason and lifting Related product plays significant role.
For solving above-mentioned technical problem, the analysis method that the doping that the present invention provides was lost efficacy comprises the steps:
Step one, the offer one satisfactory non-defective unit silicon chip of doping, this non-defective unit silicon chip is for carrying out testing sample silicon chip
Comparative analysis.
Step 2, processing described non-defective unit silicon chip and described testing sample silicon chip, this process is by described non-defective unit silicon chip
All remove with the film layer structure on the substrate surface of described testing sample silicon chip, until exposing described non-defective unit silicon chip and described
The substrate surface of testing sample silicon chip.
Step 3, the described non-defective unit silicon chip processed and described testing sample silicon chip are individually positioned on a base.
Step 4, respectively a selected resolution chart, described non-defective unit on described non-defective unit silicon chip and described testing sample silicon chip
Resolution chart on silicon chip and the resolution chart on described testing sample silicon chip equivalently-sized.
Step 5, it is set for the test condition of Spreading resistance (SRP).
Step 6, according to set test condition, respectively to the resolution chart on described non-defective unit silicon chip and described to be measured
Resolution chart on sample silicon chip is extended resistance test, respectively obtain after test described non-defective unit silicon chip resistivity or
The data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration.
Step 7, data to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or carrier concentration are carried out
Relatively, according to the resistivity of described non-defective unit silicon chip and described testing sample silicon chip or carrier concentration is the most identical judges
Whether the doping of described testing sample silicon chip lost efficacy, according to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip
Or the difference of carrier concentration estimates the dopant dose inefficacy size of described testing sample silicon chip.
Further improving and be, the process technique in step 2 uses Fluohydric acid. to carry out corrosion treatmentCorrosion Science.
Further improving is that the described base in step 3 is aclinic flat base.
Further improve and be, the test on the described non-defective unit silicon chip selected in step 4 and described testing sample silicon chip
Graphics request is: the region of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip will smooth and impurity
Being evenly distributed, the length of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all respectively greater than described expansion
The needle gage of exhibition resistance test, the width of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all distinguished greatly
Diameter in the pin of described Spreading resistance.
Further improving is that the test condition being set for Spreading resistance in step 5 includes: described extension electricity
In multiple step values that the step value of the pin of resistance test can be given from the test system of described Spreading resistance arbitrarily
Selecting one, it is multiple that the inclination angle of described Spreading resistance can be given from the test system of described Spreading resistance
Arbitrarily selecting one in non-zero angle, the number of test points of described Spreading resistance is set smaller than described resolution chart
Width is divided by the step value of the pin of described Spreading resistance；The test point of described Spreading resistance will respectively fall in
In resolution chart on described non-defective unit silicon chip and described testing sample silicon chip, and the start bit of the test of described non-defective unit silicon chip
Put and the final position test of position and described testing sample silicon chip initial in the resolution chart of described non-defective unit silicon chip
Position is identical with final position position in the resolution chart of described testing sample silicon chip.
Further improving and be, in step 6, test obtains resistivity or the data of carrier concentration of described non-defective unit silicon chip
And the inclination angle of the described resistivity of testing sample silicon chip or the data of carrier concentration and described Spreading resistance without
Close relevant with the quantity of each test point of described Spreading resistance and test point.
The present invention directly carries out SRP test by the doped region of sample to be tested, and by this test result and a doping
The test result of the doped region of satisfactory non-defective unit silicon chip compares, and can the most quickly test according to comparative result
Whether card doping lost efficacy and confirmed the difference degree of impurity, thus also can be directly quick and judge chip accurately
Lost efficacy and whether caused by doping inefficacy, therefore the time of chip failure analysis can be greatly saved and guarantee the accurate of failure analysis
Property, the yield for clear and definite technological reason and lifting Related product plays significant role.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is SRP test philosophy schematic diagram；
Fig. 2 is embodiment of the present invention method flow diagram；
Fig. 3 A-Fig. 3 E is schematic diagram in each step of embodiment of the present invention method；
Fig. 4 is embodiment of the present invention test result curve.
Detailed description of the invention
The embodiment of the present invention uses SRP test, before the embodiment of the present invention is explained, first introduce SRP
Test philosophy, as it is shown in figure 1, be SRP test philosophy schematic diagram.Existing SRP test is that the cross section to sample is carried out
Double probe tests, thus draw the depth profiles of carrier concentration and resistivity, the work process of existing SRP test is such as
Under:
1, sample 102 and base 101 are determined.Wherein the graphic aspect size of sample 102 will more than hundreds of microns,
To guarantee to test the degree of depth needed for inclined-plane 103 can cover.Base 101 is the module of band specified angle, such as 17 ', 34 ',
1 ° 9 ', 2 ° 52 ' etc..
2, sample 102 is pasted onto on base 101 and is ground, and obtains and the inclined-plane 103 at base same tilt angle.Grind
Bevel edge 104, and PN junction interface 105. is exposed after mill
3, sample 102 enters SRP board and tests, and wherein two probes 106 of SRP pass through on inclined-plane 103
Step-by-step movement moves and contacts, and there is 5mv voltage, by current measurement conversion etc., obtain two probes between two probes 106
Resistance value between 106.
4, measured resistance value is converted to resistivity and carrier concentration through calibration curve, and probe 106 is each
Contact location, by angle and distance transform, obtains the depth value of pin correspondence position, and data above is comprehensive,
The resistivity of the most available sample or the depth profile curve of carrier concentration.
As it is shown in figure 1, be embodiment of the present invention method flow diagram；The analysis method bag that embodiment of the present invention doping was lost efficacy
Include following steps:
Step one, the offer one satisfactory non-defective unit silicon chip of doping, this non-defective unit silicon chip is for carrying out testing sample silicon chip
Comparative analysis.Described non-defective unit silicon chip and described testing sample silicon chip to have identical film layer structure, and have identical
Doped structure, but the doping of the doped region of described non-defective unit silicon chip is it has been acknowledged that for meeting the requirements.As shown in Figure 3A,
Film layer structure 2 and multiple doped region 3 of plural layers composition it is formed with on described testing sample silicon chip 1.
Step 2, processing described non-defective unit silicon chip and described testing sample silicon chip, this process is by described non-defective unit silicon chip
All remove with the film layer structure on the substrate surface of described testing sample silicon chip 1, until exposing described non-defective unit silicon chip and institute
State the substrate surface of testing sample silicon chip 1.As shown in Figure 3 B, the embodiment of the present invention is to use Fluohydric acid. to corrode
Process and film layer structure is removed, until exposing described non-defective unit silicon chip and the substrate surface of described testing sample silicon chip 1.
Step 3, as shown in Figure 3 C, puts respectively by the described non-defective unit silicon chip processed and described testing sample silicon chip 1
Put on a base 5.Described base 5 is aclinic flat base.
Step 4, as shown in Figure 3 D, a selected survey on described non-defective unit silicon chip and described testing sample silicon chip 1 respectively
Attempt shape, the resolution chart on described non-defective unit silicon chip and the resolution chart on described testing sample silicon chip 1 equivalently-sized.
Resolution chart on testing sample silicon chip described in the embodiment of the present invention 1 is a doped region 3.That is selected is described
Resolution chart on non-defective unit silicon chip and described testing sample silicon chip 1 requires: described non-defective unit silicon chip and described testing sample
The region of the resolution chart on silicon chip 1 will smooth and Impurity Distribution uniform, described non-defective unit silicon chip and described testing sample
Length L of the resolution chart on silicon chip 1 is all respectively greater than the needle gage S of described Spreading resistance (SRP), described good
The width W of the resolution chart on product silicon chip and described testing sample silicon chip 1 is respectively greater than described Spreading resistance
The diameter of pin 4.
Step 5, as shown in FIGURE 3 E, bowing when described non-defective unit silicon chip and described testing sample silicon chip 1 are on base 5
View.Before test, the test condition of Spreading resistance to be set for (SRP), the step bag of setting
Including: as shown in Figure 3 D, the step value Δ X of the pin 4 of described Spreading resistance can be from the survey of described Spreading resistance
Arbitrarily selecting one in the multiple step values provided in test system, the inclination angle of described Spreading resistance can be from described extension
The multiple non-zero angle provided in the test system of resistance test arbitrarily select one, the survey of described Spreading resistance
Pilot number is set smaller than the width W step value Δ X divided by the pin 4 of described Spreading resistance of described resolution chart
I.e. < W/ Δ X；The test point of described Spreading resistance will respectively fall in described non-defective unit silicon chip and described testing sample silicon
In resolution chart on sheet, and the original position of the test of described non-defective unit silicon chip and final position are at described non-defective unit silicon chip
In resolution chart, the original position of the test of position and described testing sample silicon chip and final position are at described testing sample
In the resolution chart of silicon chip, position is identical.
Step 6, according to set test condition, respectively to the resolution chart on described non-defective unit silicon chip and described to be measured
Resolution chart on sample silicon chip is extended resistance test, respectively obtain after test described non-defective unit silicon chip resistivity or
The data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration.Described non-defective unit
The resistivity of silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or carrier concentration
Each test point of the unrelated and described Spreading resistance in the inclination angle of data and described Spreading resistance and test point
Quantity is relevant.As shown in Figure 4, being embodiment of the present invention test result curve, curve 11 is described non-defective unit silicon chip
Resistivity curve, curve 11 is the resistivity curve of described testing sample silicon chip 1, and the abscissa of Fig. 4 is test figure
Position in shape, it can be seen that number of test points is 5, step value Δ X is 5 μm；Vertical coordinate is resistivity, and unit is ohm li
Rice.
Step 7, described non-defective unit silicon chip and the described resistivity of testing sample silicon chip 1 or the data of carrier concentration are entered
Row compares, and the most identical with the resistivity of described testing sample silicon chip 1 or carrier concentration according to described non-defective unit silicon chip
Judge whether the doping of described testing sample silicon chip lost efficacy, according to described non-defective unit silicon chip and described testing sample silicon chip
The difference of resistivity or carrier concentration estimates the dopant dose inefficacy size of described testing sample silicon chip.Such as Fig. 4 institute
Showing, curve 11 and curve 12 are the most misaligned, it is possible to judge that the doping of described testing sample silicon chip 1 was lost efficacy.By
Size in resistivity is decided by that the mobility of carrier concentration and carrier, i.e. ρ=1/nq μ, ρ represent resistance
Rate, n represents that carrier concentration, μ represent the mobility of carrier.It can be seen that when the mobility of carrier is constant
Time, resistivity is determined by carrier concentration.So carrier concentration can be conversed by the difference of resistivity
Difference, and have the difference of carrier concentration, then can estimate the dopant dose inefficacy size of described testing sample silicon chip, former
Manage as follows: adulterating ion implantation type, concentration distribution relation is
S is single
Plane amasss ion implantation dosage, and x is the degree of depth, RpFor the projected range on ion implanting direction, σpFor projected range
Statistic fluctuation；The surface carrier concentration that the embodiment of the present invention obtains is directly proportional to implantation dosage under many circumstances,
Through comparing with described non-defective unit silicon chip, can be rough by described non-defective unit silicon chip and described testing sample silicon chip 1 carrier concentration difference
The difference of estimation ion implantation dosage.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (6)
1. the analysis method lost efficacy of adulterating, it is characterised in that comprise the steps:
Step one, the offer one satisfactory non-defective unit silicon chip of doping, this non-defective unit silicon chip is for carrying out testing sample silicon chip
Comparative analysis；
Step 2, processing described non-defective unit silicon chip and described testing sample silicon chip, this process is by described non-defective unit silicon chip
All remove with the film layer structure on the substrate surface of described testing sample silicon chip, until exposing described non-defective unit silicon chip and described
The substrate surface of testing sample silicon chip；
Step 3, the described non-defective unit silicon chip processed and described testing sample silicon chip are individually positioned on a base；
Step 4, respectively a selected resolution chart, described non-defective unit on described non-defective unit silicon chip and described testing sample silicon chip
Resolution chart on silicon chip and the resolution chart on described testing sample silicon chip equivalently-sized；
Step 5, it is set for the test condition of Spreading resistance；
Step 6, according to set test condition, respectively to the resolution chart on described non-defective unit silicon chip and described to be measured
Resolution chart on sample silicon chip is extended resistance test, respectively obtain after test described non-defective unit silicon chip resistivity or
The data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration；
Step 7, data to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or carrier concentration are carried out
Relatively, judge according to comparative result whether the doping of described testing sample silicon chip lost efficacy；According to described non-defective unit silicon chip and institute
State the resistivity of testing sample silicon chip or the difference of carrier concentration to estimate the dopant dose of described testing sample silicon chip
Inefficacy size.
2. the method for claim 1, it is characterised in that: the process technique in step 2 uses Fluohydric acid. to enter
Row corrosion treatmentCorrosion Science.
Method the most according to claim 1, it is characterised in that: the described base in step 3 is aclinic
Flat base.
Method the most according to claim 1, it is characterised in that: the described non-defective unit silicon chip selected in step 4
With the resolution chart requirement on described testing sample silicon chip it is: the survey on described non-defective unit silicon chip and described testing sample silicon chip
Attempt shape region will smooth and Impurity Distribution uniform, the test on described non-defective unit silicon chip and described testing sample silicon chip
The length of figure is all respectively greater than the needle gage of described Spreading resistance, described non-defective unit silicon chip and described testing sample silicon chip
On the width of resolution chart be all respectively greater than the diameter of pin of described Spreading resistance.
Method the most according to claim 1, it is characterised in that: step 5 is set for Spreading resistance
Test condition include: the step value of the pin of described Spreading resistance can be from the test system of described Spreading resistance
In multiple step values of being given arbitrarily select one, the inclination angle of described Spreading resistance can be surveyed from described spreading resistance
The multiple non-zero angle provided in the test system of examination arbitrarily select one, the number of test points of described Spreading resistance
It is set smaller than the width step value divided by the pin of described Spreading resistance of described resolution chart；Described spreading resistance
The test point of test will respectively fall in the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip, and institute
State the original position of the test of non-defective unit silicon chip and final position position and described in the resolution chart of described non-defective unit silicon chip
The original position of the test of testing sample silicon chip and final position position in the resolution chart of described testing sample silicon chip
Identical.
Method the most according to claim 5, it is characterised in that: in step 6, test obtains described non-defective unit silicon chip
Resistivity or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration
Each test point of unrelated and described Spreading resistance and the quantity of test point with the inclination angle of described Spreading resistance
Relevant.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210296921.8A CN103630816B (en) | 2012-08-20 | 2012-08-20 | doping failure analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210296921.8A CN103630816B (en) | 2012-08-20 | 2012-08-20 | doping failure analysis method |
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| CN103630816A CN103630816A (en) | 2014-03-12 |
| CN103630816B true CN103630816B (en) | 2016-12-21 |
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