CN103630816A - Doping failure analysis method - Google Patents
Doping failure analysis method Download PDFInfo
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- CN103630816A CN103630816A CN201210296921.8A CN201210296921A CN103630816A CN 103630816 A CN103630816 A CN 103630816A CN 201210296921 A CN201210296921 A CN 201210296921A CN 103630816 A CN103630816 A CN 103630816A
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Abstract
The invention discloses a doping failure analysis method comprising the following steps: a non-defective silicon chip is provided; the non-defective silicon chip and a sample silicon chip to be tested are processed until substrate surfaces are exposed; the non-defective silicon chip and the sample silicon chip to be tested are arranged on a pedestal; test patterns are selected on the non-defective silicon chip and the sample silicon chip to be tested; conditions of performing an SRP are set; the SRP is respectively performed on the test patterns on the non-defective silicon chip and the sample silicon chip to be tested so that data of resistivity or carrier concentration are acquired; and the data of resistivity or carrier concentration of the non-defective silicon chip and the sample silicon chip to be tested are compared, whether doping of the sample silicon chip to be tested is failed is judged, and doping dose failure size of the sample silicon chip to be tested is estimated. Failure relevant to doping can be accurately and rapidly verified, and difference degree of doping impurities can be confirmed so that time for analyzing chip failure can be greatly saved and accuracy of failure analysis can be ensured, and thus the doping failure analysis method plays a significant role in clearing technology reasons and enhancing yield rate of relevant products.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit) method of manufacturing technology, particularly relate to a kind of doping failure analysis method.
Background technology
In SIC (semiconductor integrated circuit) is manufactured, doping is a kind of general technique, when losing efficacy, doping often causes the inefficacy of the chip product of last formation, therefore how to judge whether doping lost efficacy, and determine that according to judged result whether the inefficacy of chip product is that what to have that doping inefficacy causes is a kind of important analysis method in chip product failure analysis.Existing doping failure analysis method comprises:
1, the electrical testing of device is proved, the method is to apply electric stress by each port or electrode to device, thereby monitors the understanding characteristics such as electric current and voltage of each electrode.The problem that the method exists is:
1.1, to the test of device, need to use complicated nano-probe technology or liner (pad) is used microprobe analysis.
Even if 1.2 clear and definite device electrology characteristics are abnormal, still cannot confirm whether component failure was lost efficacy and caused by doping, because component failure may be to be caused by a plurality of reasons such as doping, etching, aligning, abnormal redundancy things.
2, for the dyeing of dopant species and concentration, process.The problem that the method exists is:
2.1, dyeing and dyeing are closely related with proportioning, the time of liquid, need repetition test, take time and effort;
2.2, when the dosage of abnormal doping or concentration difference hour, be coloured to power and greatly reduce.
3, secondary ion mass spectrum analysis (SIMS).The problem that the method exists is: Analysis of Complex, cost is expensive, and large to the restriction of sample size, is embodied in and requires length and width all more than 100 microns.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of analytical approach of adulterating and losing efficacy, the accurately fast verification relevant inefficacy of adulterating, and the difference degree of confirming impurity, can greatly save the time and the accuracy of guaranteeing failure analysis of chip failure analysis, be clear and definite technological reason and the yield performance significant role that promotes Related product.
For solving the problems of the technologies described above, the analytical approach that doping provided by the invention was lost efficacy comprises the steps:
The test condition of Spreading resistance (SRP) is carried out in step 5, setting.
Step 6, according to the test condition setting, respectively the resolution chart on the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is carried out to Spreading resistance, after test, obtain respectively the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration.
Step 7, described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or the data of carrier concentration are compared, according to the resistivity of described non-defective unit silicon chip and described testing sample silicon chip or whether carrier concentration is identical judges whether the doping of described testing sample silicon chip lost efficacy, according to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or the difference of carrier concentration, estimate the dopant dose of the described testing sample silicon chip size that lost efficacy.
Further improve is that the treatment process in step 2 adopts hydrofluorite to carry out corrosion treatment.
Further improving is that the described base in step 3 is aclinic flat base.
Further improve and be, described non-defective unit silicon chip and the requirement of the resolution chart on described testing sample silicon chip selected in step 4 are: the region of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip all wants smooth and Impurity Distribution is even, the length of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all greater than respectively the needle gage of described Spreading resistance, and the width of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all greater than respectively the diameter of the pin of described Spreading resistance.
Further improve and be, in step 5, setting the test condition carry out Spreading resistance comprises: in a plurality of step values that the step value of the pin of described Spreading resistance can provide from the test macro of described Spreading resistance, select one arbitrarily, in a plurality of non-zero angle that the inclination angle of described Spreading resistance can provide from the test macro of described Spreading resistance, select one arbitrarily, the number of test points of described Spreading resistance is set as being less than the width of described resolution chart divided by the step value of the pin of described Spreading resistance; The test point of described Spreading resistance all will drop on respectively in the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip, and the reference position of the test of described non-defective unit silicon chip and the final position reference position of position and the test of described testing sample silicon chip in the resolution chart of described non-defective unit silicon chip is identical with final position position in the resolution chart of described testing sample silicon chip.
Further improve and be, it is irrelevant relevant with each test point of described Spreading resistance and the quantity of test point that in step 6, test obtains the inclination angle of the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration and described Spreading resistance.
The present invention directly carries out SRP test by the doped region of sample to be tested, and the test result of the doped region of this test result and the satisfactory non-defective unit silicon chip of a doping is compared, according to the comparative result difference degree that accurately whether fast verification doping was lost efficacy and confirmed impurity, thereby also can directly also judge accurately fast whether chip failure was lost efficacy and caused by doping, therefore can greatly save the time and the accuracy of guaranteeing failure analysis of chip failure analysis, be clear and definite technological reason and the yield performance significant role that promotes Related product.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is SRP test philosophy schematic diagram;
Fig. 2 is embodiment of the present invention method flow diagram;
Fig. 3 A-Fig. 3 E is schematic diagram in each step of embodiment of the present invention method;
Fig. 4 is embodiment of the present invention test result curve.
Embodiment
In the embodiment of the present invention, using SRP test, before the embodiment of the present invention is explained, first introduce SRP test philosophy, as shown in Figure 1, is SRP test philosophy schematic diagram.Existing SRP test is that two probe tests are carried out in the cross section of sample, thereby draws the depth profiles of carrier concentration and resistivity, and the course of work of existing SRP test is as follows:
1, determine sample 102 and base 101.Wherein the figure length and width size of sample 102 will be more than hundreds of microns, to guarantee that testing inclined-plane 103 can cover the required degree of depth.Base 101 is the module with specified angle, as 17 ', and 34 ', 1 ° 9 ', 2 ° 52 ' etc.
2, sample 102 sticks on base 101 and grinds, and obtains the inclined-plane 103 with base same tilt angle.After grinding, expose bevel edge 104, and PN junction interface 105.
3, sample 102 enters SRP board and tests, and wherein two probes 106 of SRP are moved and contacted by step-by-step movement on inclined-plane 103, and two 106 of probes exist 5mv voltage, by current measurement conversion etc., obtain the resistance value of 106 of two probes.
4, measured resistance value is converted to resistivity and carrier concentration through calibration curve, and the probe 106 residing positions of each contact, by angle and distance transform, obtain the depth value of pin correspondence position, above aggregation of data, just can obtain the depth profile curve of resistivity or the carrier concentration of sample.
As shown in Figure 1, be embodiment of the present invention method flow diagram; The analytical approach that embodiment of the present invention doping was lost efficacy comprises the steps:
Step 6, according to the test condition setting, respectively the resolution chart on the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is carried out to Spreading resistance, after test, obtain respectively the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration.The inclination angle of the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration and described Spreading resistance is irrelevant relevant with each test point of described Spreading resistance and the quantity of test point.As shown in Figure 4, be embodiment of the present invention test result curve, curve 11 is the resistivity curve of described non-defective unit silicon chip, curve 11 is the resistivity curve of described testing sample silicon chip 1, the horizontal ordinate of Fig. 4 is position in resolution chart, can find out that number of test points is 5, and step value Δ X is 5 μ m; Ordinate is resistivity, and unit is ohmcm.
Step 7, described non-defective unit silicon chip and the resistivity of described testing sample silicon chip 1 or the data of carrier concentration are compared, and according to the resistivity of described non-defective unit silicon chip and described testing sample silicon chip 1 or whether carrier concentration is identical judges whether the doping of described testing sample silicon chip lost efficacy, according to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or the difference of carrier concentration, estimate the dopant dose of the described testing sample silicon chip size that lost efficacy.As shown in Figure 4, curve 11 and curve 12 do not overlap, so can judge the doping inefficacy of described testing sample silicon chip 1.Because the size of resistivity is decided by the mobility of carrier concentration and charge carrier, i.e. ρ=1/nq μ, ρ represents resistivity, and n represents carrier concentration, and μ represents the mobility of charge carrier.Can find out, when the mobility of charge carrier is constant, resistivity is determined by carrier concentration.So can converse the difference of carrier concentration by the difference of resistivity, and have the difference of carrier concentration, can estimate the dopant dose inefficacy size of described testing sample silicon chip, principle is as follows: to ion implantation type doping, CONCENTRATION DISTRIBUTION is closed and is
s is unit area ion implantation dosage, and x is the degree of depth, R
pfor the projected range in Implantation direction, σ
pstatistic fluctuation for projected range; The surface carrier concentration that the embodiment of the present invention obtains is directly proportional to implantation dosage under many circumstances, and warp and the comparison of described non-defective unit silicon chip, can be by the difference of described non-defective unit silicon chip and the poor rough estimation ion implantation dosage of described testing sample silicon chip 1 carrier concentration.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. the analytical approach of adulterating and losing efficacy, is characterized in that, comprises the steps:
Step 1, provide a doping satisfactory non-defective unit silicon chip, this non-defective unit silicon chip is for comparing analysis to testing sample silicon chip;
Step 2, described non-defective unit silicon chip and described testing sample silicon chip are processed, this processing is all removed the film layer structure on the substrate surface of described non-defective unit silicon chip and described testing sample silicon chip, until expose the substrate surface of described non-defective unit silicon chip and described testing sample silicon chip;
Step 3, the described non-defective unit silicon chip of processing and described testing sample silicon chip are placed on respectively on a base;
Step 4, a selected resolution chart on described non-defective unit silicon chip and described testing sample silicon chip respectively, the resolution chart on the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip measure-alike;
The test condition of Spreading resistance is carried out in step 5, setting;
Step 6, according to the test condition setting, respectively the resolution chart on the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is carried out to Spreading resistance, after test, obtain respectively the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration;
Step 7, described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or the data of carrier concentration are compared, when the resistivity of described testing sample silicon chip or carrier concentration be described non-defective unit silicon chip resistivity or carrier concentration 95%～105% time, the doping of described testing sample silicon chip is effective; When the resistivity of described testing sample silicon chip or carrier concentration are outside 95%～105% scope of described non-defective unit silicon chip resistivity or carrier concentration time, the doping of described testing sample silicon chip was lost efficacy; According to described non-defective unit silicon chip and the resistivity of described testing sample silicon chip or the difference of carrier concentration, estimate the dopant dose of the described testing sample silicon chip size that lost efficacy.
2. the method for claim 1, is characterized in that: the treatment process in step 2 adopts hydrofluorite to carry out corrosion treatment.
3. method according to claim 1, is characterized in that: the described base in step 3 is aclinic flat base.
4. method according to claim 1, it is characterized in that: described non-defective unit silicon chip and the requirement of the resolution chart on described testing sample silicon chip selected in step 4 are: the region of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip all wants smooth and Impurity Distribution is even, the length of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all greater than respectively the needle gage of described Spreading resistance, and the width of the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip is all greater than respectively the diameter of the pin of described Spreading resistance.
5. method according to claim 1, it is characterized in that: in step 5, set the test condition carry out Spreading resistance and comprise: in a plurality of step values that the step value of the pin of described Spreading resistance can provide from the test macro of described Spreading resistance, select one arbitrarily, in a plurality of non-zero angle that the inclination angle of described Spreading resistance can provide from the test macro of described Spreading resistance, select one arbitrarily, the number of test points of described Spreading resistance is set as being less than the width of described resolution chart divided by the step value of the pin of described Spreading resistance, the test point of described Spreading resistance all will drop on respectively in the resolution chart on described non-defective unit silicon chip and described testing sample silicon chip, and the reference position of the test of described non-defective unit silicon chip and the final position reference position of position and the test of described testing sample silicon chip in the resolution chart of described non-defective unit silicon chip is identical with final position position in the resolution chart of described testing sample silicon chip.
6. method according to claim 5, is characterized in that: it is irrelevant relevant with each test point of described Spreading resistance and the quantity of test point that in step 6, test obtains the inclination angle of the resistivity of described non-defective unit silicon chip or the data of carrier concentration and the resistivity of described testing sample silicon chip or the data of carrier concentration and described Spreading resistance.
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| CN102346152A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Sample failure analysis method |
| CN102495309A (en) * | 2011-11-29 | 2012-06-13 | 苏州华碧微科检测技术有限公司 | Failure analysis method |
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| JPH06265596A (en) * | 1993-03-16 | 1994-09-22 | Fujitsu Ltd | Multi-function device test method |
| CN101452201A (en) * | 2007-11-30 | 2009-06-10 | 上海华虹Nec电子有限公司 | Method for detecting mask printing plate |
| CN101740430A (en) * | 2008-11-11 | 2010-06-16 | 上海华虹Nec电子有限公司 | Epitaxial auto-doping evaluating method |
| CN102346152A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Sample failure analysis method |
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