CN103620954B - power transistor gate driver - Google Patents

Abstract

The invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to first gate voltage. A second charging path may be connected between the gate terminal of the power transistor and the second power supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage higher than the first gate voltage. The voltage of the second power supply voltage is higher than the voltage of the first power supply voltage.

Description

Power Transistor Gate Drivers

technical field

The invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to first gate voltage. A second charging path may be connected between the gate terminal of the power transistor and a second voltage source to charge the gate terminal from a first gate voltage to a second gate voltage higher than the first gate voltage. The voltage of the second power supply voltage is higher than the voltage of the first power supply voltage. Another aspect of the invention relates to a load driving assembly including a plurality of gate drivers electrically coupled to respective power transistors. Load driver components can be used in various power amplification applications, for example, Class D audio amplifiers.

Background technique

Gate drivers for power transistors of the power or output stage of a class D audio amplifier are known in the art. Power transistors generally include N-channel field effect transistors, such as NMOS or IGBTs, which are popular semiconductor components because of their low on-resistance to a given footprint or area consumption on the semiconductor substrate. Since the manufacturing cost of a semiconductor substrate is closely related to its area, reducing the area is an effective way to reduce the cost.

However, the design of a suitable gate driver for such N-channel FETs is challenging for various reasons, for example, the need to greatly increase the instantaneous gate voltage to the drain voltage of the N-channel FET during operation of the power stage above. A higher instantaneous gate voltage is required to fully turn on the N-channel FET. Placing an N-channel FET in a fully on state or a conduction state gives it low on-resistance and minimizes conduction power loss. Since the drain terminals of the outermost power transistors of the power stage in a Class D audio amplifier are connected to the highest directly available DC supply voltage, usually in the form of a positive DC supply voltage or rail, the instantaneous gate voltage must be within the stated The on-state or conduction-state period of the power transistor rises well above this highest DC supply voltage. Bootstrap techniques and circuits for generating such high gate voltages in each gate driver are known in the art. However, it relies on pre-charge capacitors that provide the gate drive voltage to the N-channel field effect transistors of the power stage. When a pre-charged bootstrap capacitor is connected to the gate terminal of an N-channel FET, its voltage is greatly reduced by the intrinsic gate capacitance of the N-channel FET due to charge sharing, unless the bootstrap capacitance of the bootstrap capacitor is greater than The intrinsic gate capacitance is much larger, eg 10 or 20 times. However, the intrinsic gate capacitance of N-channel FETs suitable for many types of power stages can be very large, e.g., several hundred pF, leading to inappropriately sized integrated bootstrap capacitor capacitances based on the above rule of thumb. Actual very large values, ie capacitance values ranging from a few nF to over 20nF. Alternatively, the bootstrap capacitor may be provided outside the semiconductor chip of the fixed gate driver. However, this solution is not desirable because the power stage topology, for example, a multilevel H-bridge power stage typically consists of multiple cascaded or stacked power transistors with associated gate drivers, each requiring an external self-transistor. Lift the capacitor. This multiple external bootstrap capacitors adds cost to the overall Class D amplifier solution, requires allocation of high-value printed circuit board space, and potentially jeopardizes reliability.

Thus, there is a strong need for gate drivers for power transistors, especially N-channel field effect transistors, that can boost the gate voltage above the positive DC supply voltage or rail with minimal external capacitor requirements. In addition, the higher power efficiency of gate drivers is of great advantage in a variety of applications, such as Class D audio amplifiers for portable and/or battery-powered communication and entertainment devices, such as mobile phones, MP3 players, etc.

Contents of the invention

A first aspect of the invention relates to a gate driver for a power transistor. The gate driver includes a first charging path electrically connectable between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path may be electrically connected between the second voltage source and the gate terminal of the power transistor to charge the gate terminal from the first gate voltage to a second gate voltage higher than the first gate voltage. The voltage of the second voltage source is higher than the voltage of the first voltage source.

An advantage of this application of charging the gate terminal of the power transistor with two separate charging paths is that a major part, e.g. more than 50%, of the total charge required to raise the gate voltage to the second gate voltage, Or 75% or preferably more than 90% can be delivered by a high power efficient DC power supply comprising the first supply voltage. In this way, only the remainder of the total charge needs to be provided by the low power efficient high voltage supply comprising the second supply voltage. The high voltage is typically provided by a voltage pump or voltage multiplier capable of boosting the high voltage supply to a voltage level above the highest available positive DC supply voltage. As mentioned above, the gate input or terminal of an N-channel field effect transistor (FET) is required to have a high voltage level for high supply voltage transmission to switch the N-channel FET into its conductive state. When the gate voltage is lower than the first gate voltage, the first and second charging paths can be used to supply the charging current to the gate terminal of the power transistor, but in this case, the charging current provided by the first charging path is preferably higher than The charging current provided through the second charging path is much higher. In a preferred embodiment, when the gate voltage is lower than the first gate voltage, the charging current transmitted by the second charging path to the gate terminal of the power transistor is substantially zero or extremely small, for example, 10 μA or below 1 μA. This can be achieved, for example, by placing a controllable MOS transistor switch in series in the second charging path, the very large turn-off resistance of the MOS transistor switch being used to substantially interrupt any charging current through the second charging circuit. When the gate voltage of the power transistor is higher than the first gate voltage, the charging current provided through the first charging path is preferably substantially zero, because the first charging path is connected to the first voltage source, the voltage level of the first voltage source can be close to the level of the first gate voltage. The level of the first gate voltage is preferably set to approximately the same level as the voltage level of the first power supply voltage so that the first charging path provides The charging current reaches the maximum. In this condition, the first charging path cannot provide further charging current to the gate terminal because the charging current flows back. Subsequently, a charging current is further provided to the gate terminal through the second charging path to increase the gate voltage of the power transistor from the first gate voltage to the second gate voltage. Since the remote node of the second charging path is connected to a second supply voltage, the second supply voltage being higher than the first supply voltage and the first gate voltage, a charging current can flow at least from the second supply voltage to the gate terminal of the power transistor, until the gate voltage approaches the second supply voltage.

The gate driver of the present invention is very effective for driving the gates of N-channel FETs of switching power stages or load drivers. The gate driver of the present invention can be used in a single-end or H-bridge load driving circuit of a Class D audio amplifier. Class D audio amplifiers can include 2-level AD or BD class PDM or multi-level PWM in various power stage topologies.

According to a preferred embodiment, the first voltage supply comprises the drain voltage of the power transistor to electrically couple the drain terminal of the power transistor with its gate terminal via the first charging path. In some embodiments, certain drain terminals of the power transistors may be directly coupled to a positive DC supply voltage of an output stage comprising the power transistors. In other embodiments, the drain terminal of the power transistor may be coupled to an intermediate supply voltage, for example, the drain terminal is coupled to a flying capacitor in a multilevel PWM output stage topology, and the drain terminal voltage equals level is set by the voltage across the flying capacitor. Depending on the requirements of a particular application, the gate driver can be used to operate between a wide range of DC supply voltages, ie the voltage difference between the second supply voltage of the gate driver and the lowest supply voltage. In many useful applications, the DC supply voltage can be set to a value of 5 volts to 120 volts. The DC supply voltage is provided as a unipolar or bipolar DC voltage of eg +40 volts or +/−20 volts with respect to ground (GND).

The gate driver preferably comprises a voltage multiplier or a charge pump for generating a second supply voltage based on a DC supply voltage of the gate driver. The DC supply voltage may include, for example, a standard CMOS power rail with a DC voltage of 3.0 to 5.0 volts. A voltage doubler or charge pump can charge the flying capacitor to the latter DC voltage and stack the charged capacitor above the first supply voltage to generate a second supply voltage 3 to 5V higher than the first supply voltage.

The gate driver further preferably comprises a controllable discharge path for switching the power transistor into an off state or a non-conducting state, wherein the controllable discharge path is connectable between the gate terminal of the power transistor and the source terminal of the power transistor . The discharge path may include a MOS switch, which is switched between conducting and non-conducting states by controlling the gate voltage of the MOS switch. The discharge path removes charge provided on the gate terminal via the first and second charge paths for turning on the power transistor, thereby ensuring that the power transistor quickly enters a non-conductive state, as described above.

According to another preferred embodiment, the gate driver comprises a controller or a sequencer for controlling charging current to be supplied to the gate terminal via the first charging path and controlling charging current to be supplied to the gate terminal via the second charging path. Optionally, the controller can control the off-state and on-state of the controllable discharge path. The controller can be a relatively simple circuit based on combinational logic that operates asynchronously to whatever clock signal is available to the gate driver. In this embodiment, the controller operates according to a self-timed mechanism and includes a plurality of suitably configured transistors and circuits to define the voltage level of the first voltage. However, in other embodiments, the controller may include clock timing logic that operates synchronously with the main system clock signal or other system clock signals available to the gate driver. In the latter embodiment, the controller may comprise, for example, a programmable logic circuit or a software programmable or hardwired digital signal processor (DSP) or a general purpose microprocessor.

In one embodiment, the predetermined threshold voltage is provided to the controller to set the first voltage, and the controller is used to control the charging current to be supplied to the first and second charging paths by comparing the gate voltage of the power transistor with the predetermined threshold voltage gate terminal. The predetermined threshold voltage may be derived, for example, from a drain voltage of a power transistor electrically coupled to the first charging path. The predetermined threshold voltage may be set to a voltage level lower than the drain voltage of the power transistor by about one MOS threshold voltage. In practice, the predetermined threshold voltage is generally 0.5 to 1.0 V, lower than the drain voltage of the power transistor. This embodiment enables conveniently specifying the first voltage of the gate driver for the actual voltage level of its associated power transistor.

In another embodiment, the first voltage may be defined by a timing scheme rather than a specific predetermined threshold voltage. According to a timing-based scheme, the controller is configured to provide a charging current to the gate terminal of the power transistor through the first charging path for a predetermined charging time period, for example, a charging time period of 5 to 100 nanoseconds, to reach the first gate Voltage. Subsequently, the controller supplies a charging current to the gate terminal through the second charging path for a predetermined period of time. The approximate charging time period can be calculated based on knowledge of the approximate impedance of the first charging path and the approximate value of the capacitance on the gate terminal of the power transistor. This capacitance generally includes the capacitance for the gate terminal and the gate-drain capacitance.

The flow of charging current through the first and second charging paths may conveniently be controlled by series coupling switching elements (eg implemented as controllable semiconductor switches, eg FET transistors controlled by a controller or sequencer). The controllable FET transistor may include one or more NMOS or PMOS transistors, and the NMOS or PMOS transistors may be conveniently integrated on a semiconductor substrate, and have lower on-resistance and higher off-resistance.

In one embodiment, the controller is configured to interrupt the charging current provided by the second voltage source until the gate voltage reaches the first gate voltage. The advantage of this approach is that it generally ensures that the major part of the required charge on the gate terminal is transferred through the high power efficient first voltage supply, eg a positive DC supply. Therefore, only a relatively small fraction of the total gate charge is provided by the low power efficiency high voltage supply providing the second supply voltage.

In the conducting state or on state of the power transistor, the voltage or voltage level of the second supply voltage is preferably at least one gate-source voltage drop of the power transistor higher than the voltage of the first voltage supply. In order to ensure that the voltage level of the second supply voltage is high enough to ensure that the power transistor is properly in its conducting state, in the conduction or on state of the power transistor, the voltage of the second supply voltage may be at least The voltage is 2 volts higher, preferably 3 volts, more preferably 5 volts.

The first charging path is preferably used to charge the gate terminal of the power transistor to the first gate voltage within 100 nanoseconds, preferably within 50 nanoseconds, more preferably within 20 nanoseconds. This charging time range is suitable for controlling the switching power transistors of the power stage to operate at a PWM or PDM switching frequency of 100kHz to 10MHz.

Since the voltage level of the first voltage supply may fluctuate considerably during gate driver operation, the second supply voltage is preferably an adapted voltage, always at least 2.5 volts higher than the voltage of the first voltage supply, during gate driver operation. This ensures that there is always sufficient voltage available to switch the power transistor into its conductive state and to keep the power transistor in this state during the intended operation of the gate driver.

In a particularly advantageous embodiment, the invention relates to a load driving assembly comprising a plurality of gate drivers according to any one of the above embodiments. The load driving assembly further includes a plurality of power transistors having gate terminals electrically connected to the first node of the first charging path and the first node of the second charging path of the gate driver, respectively. The drain terminal of each power transistor is electrically coupled to the second node of the first charging path to provide the power transistor with the first power supply voltage. A plurality of component input terminals is coupled to respective inputs of the plurality of gate drivers to provide modulated input signals thereto. A plurality of power transistors are cascadedly coupled to an upper pin formed between the first DC power supply voltage and the output terminal and a lower pin formed between the output terminal and the second DC power supply voltage such that the output terminal is electrically coupled to between the upper and lower pins.

The load driver assembly can be directly connected to a loudspeaker load coupled to the output. The load drive assembly may include, for example, 2 to 8 cascaded power transistors, each power transistor having drain and gate terminals coupled to a separate gate driver. According to a preferred embodiment of the load driving assembly, the second voltage supply of the plurality of gate drivers is electrically connected to a common charge pump capacitor of the second voltage supply. This embodiment enables multiple second charging paths to receive individual charging currents from a single common high voltage supply requiring only a single capacitor. Therefore, since a typical load drive assembly may include more than 4 cascaded power transistors, for example, 6, 8 or more, the ability to share the second voltage from a single capacitor based high voltage supply reduces the need for bootstrap capacitor driven power transistors. The gate terminal is necessary. Thus, only a single capacitor component is required, although the capacitance value of the shared charge pump capacitor may be quite large, eg, 10nF to 100nF, requiring it to be an external component of the load drive assembly.

Because of the utilization of multiple stacked or cascaded power transistors, the load drive assembly of the present invention is particularly suitable for applications in multi-level PWM or PDM outputs or power stages. The load drive assembly is operable to operate on a 5 volt to 120 volt DC differential between the first and second DC supply voltages. According to one embodiment of a load drive assembly used as a multi-level PWM power stage, a DC voltage source is used to set a predetermined DC voltage difference between a first node and a second node, the first node being located at the upper pin of a pair of stages between the cascaded power transistors, and the second node is located between a pair of cascaded power transistors at the lower pin. The DC voltage source may conveniently comprise at least one device or component selected from a charging capacitor, a floating DC power rail, a battery. The predetermined DC voltage difference is preferably substantially equal to half the DC voltage difference between the first and second DC supply voltages to generate a 3-level output signal at the output. In one embodiment, the DC voltage source includes a charging capacitor with a capacitance of 100 nF to 10 μF. The plurality of power transistors preferably comprises at least one N-channel field effect transistor, eg NMOS or IGBT, arranged on a semiconductor substrate, eg silicon, gallium nitride or silicon carbide. Preferably, all power transistors of the load drive assembly are implemented as N-channel field effect transistors.

According to another advantageous embodiment of the invention, the load driving assembly is preferably formed in a semiconductor process supporting high voltage devices or integrated on a semiconductor substrate, eg a CMOS integrated circuit. Semiconductor substrates provide a robust, low-cost single-chip solution for the manufacture of load-driven components particularly suited for high-volume consumer-oriented audio applications where cost is an essential parameter, such as televisions, mobile phones, and MP3 players. The semiconductor substrate preferably comprises a voltage supply connection electrically connected to an external charge pump capacitor of an energy store as a second voltage supply.

Another aspect of the invention provides a Class D audio amplifier comprising one of the above embodiments of the load driving assembly. As mentioned above, a Class D audio amplifier may include modulators for bi-level or multi-level PWM or PDM.

Description of drawings

Preferred embodiments of the present invention are described in detail below according to the accompanying drawings, in the accompanying drawings:

1 is a schematic diagram of a load driving assembly including a plurality of gate drivers electrically coupled to respective gate terminals of a plurality of power transistors according to a preferred embodiment of the present invention,

2 is a schematic diagram of a single gate driver coupled to a gate terminal of an associated power transistor according to a preferred embodiment,

Figure 3 is a hybrid block and transistor level diagram of a single gate driver schematically shown in Figures 1 and 2; and

4 is a schematic diagram of a load driving assembly including a plurality of gate drivers electrically coupled to respective gate terminals of a plurality of power transistors according to a second preferred embodiment of the present invention.

detailed description

FIG. 1 schematically shows a load driver assembly 100 connected to a loudspeaker load 133 . The load drive assembly 100 comprises a gate drive circuit 101 comprising four individual gate drivers 111, 113, 115, 117 according to a preferred embodiment of the present invention. Each gate driver has an output electrically connected to the gate terminal of one of the NMOS transistors SW1, SW2, SW3, SW4. The NMOS transistors SW1 , SW2 , SW3 , SW4 are cascadedly coupled between the first or positive DC supply voltage VS and the second DC supply voltage in the form of ground (GND). Cascaded NMOS transistors SW1 , SW2 , SW3 , SW4 form a load driver for a loudspeaker load 133 coupled via a load inductor 137 and a load capacitor 135 to the output V _PWM of the load driver. The combined operation of the load capacitors and load inductors 135, 137 low pass filters the multi-level pulse width modulated output signal waveform provided at the output V _PWM to suppress carrier or switching frequency components in the audio signal at the speaker load 133 .

In the current embodiment of the present invention, the gate drive circuit 101 and the load driver including cascaded NMOS power transistors SW1, SW2, SW3, SW4 are integrated on a common semiconductor substrate or chip, so that each of the The electrical connections between the gate drivers 111, 113, 115, 117 and their associated NMOS power transistors are made on the semiconductor substrate. However, those skilled in the art should understand that the load driver can be formed as a completely independent circuit from the gate driving circuit 101 , for example, a separate semiconductor substrate or an integrated circuit. In the latter embodiment, the electrical connections between each gate driver 111, 113, 115, 117 shown in FIG. on the electrical traces provided. Those skilled in the art should understand that each cascaded NMOS transistor SW1, SW2, SW3, SW4 can be composed of a single MOS transistor schematically shown in FIG. 1, or, in other embodiments of the present invention, can include multiple smaller The parallel coupling of independent NMOs transistors.

The skilled person will appreciate that the illustrated single-ended multilevel load driver assembly 100 may be extended based on a pair of substantially identical load driver circuit assemblies 100 connected to opposite terminals of the speaker load 133 to provide an H-bridge load driver assembly. Likewise, the skilled person will understand that the four gate drivers 111, 113, 115, 117 may be used to drive the gate terminals of other topologies of switching power stages (eg, PDM or 2-level AD or BD level PWM modulation) .

In the current embodiment, the load driver includes an upper pin A and a lower pin B, the upper pin A includes a pair of cascaded NMOS transistors SW1, SW2, and the lower pin B includes a pair of cascaded NMOS transistors SW3, SW4. The cascaded NMOS transistors SW1, SW2 are coupled at the drain terminal of SW1 to VS and at the source terminal of SW2 to the output or node V _PWM . The drain terminal of the NMOS transistor SW3 is coupled to the output terminal or node V _PWM , and the source terminal of SW4 is coupled to GND. The load driver also includes a charging flying capacitor C _fly 125 for generating a third output level on the output node V _PWM between V _S and GND to provide a multi-level PWM signal, as specified in Applicant's 61/407,262 Co-pending U.S. Patent Application No. During the operation of the load driving assembly 100, the signal generator or modulator is used to apply the first signal of appropriate amplitude and phase to the first, second, third and fourth input terminals PWM_1, PWM_2, PWM_3, PWM_4 of the gate drivers 111, 113, 115, 117, respectively. , second, third and fourth pulse width modulation control signals to control the respective states of the cascaded NMOS transistors SW1, SW2, SW3 and SW4. Thus, each of the NMOS transistors SW1 to SW4 is switched between the on state and the off state according to the transition of the pulse width modulation control signal. The on-resistance of each NMOS transistor SW1 , SW2 , SW3 , SW4 may vary widely depending on the requirements of a particular application, particularly the impedance of the speaker load 133 or another type of inductive and/or capacitive load. In the current embodiment, each NMOS transistor is preferably designed such that its on-resistance is 0.01 to 5 ohm, for example, 0.05 to 0.5 ohm.

The load drive assembly 100 includes a voltage multiplier or charge pump 120 , HV _boot , for generating a high supply voltage based on a positive DC supply voltage V _S . The positive DC supply voltage V _S can vary widely depending on the requirements of a particular application, for example between 5 and 100 volts, but in the current embodiment of the invention it is fixed at about 40 volts. The high voltage generated by the charge pump 120 is preferably set at about 5 volts above the positive DC supply voltage V _S and distributed to each of the gate drivers 111 , 113 , 115 , 117 . In each gate driver, a high voltage is used to generate a gate drive signal or a gate voltage above the positive DC supply voltage _VS to drive each NMOS transistors SW1, SW2, SW3, SW4 are driven to a low resistance conduction state as described below. A power supply or pump capacitor 123, C _boot , is coupled at one end to the high supply voltage and at the other end to the positive DC supply voltage to provide energy storage for the high supply voltage HV _boot . The charge pump 120 includes a flying capacitor (not shown) that is intermittently charged from the appropriate DC supply voltage of the load drive assembly 100 to a voltage of approximately 3 or 5 volts above ground. The flying capacitor is intermittently disconnected from the DC supply voltage and electrically connected to the C _boot to dump the captured charge onto it, thus raising the high voltage at the HV _boot to about 3 volts or 5 volts above the positive DC supply voltage VS volt. The supply capacitor 123 may be an external component of the load drive assembly 100 or integrated on the semiconductor substrate of the fixed gate drive circuit 101 , depending on the size and cost specified by the particular application. The capacitance of the external power supply capacitor 123 is preferably set to a value of 10 nF to 100 nF.

As shown in FIG. 1 , each gate driver 111 , 113 , 115 , 117 includes three separate electrical connection lines to respective drains, gates and sources of NMOS transistors SW1 , SW2 , SW3 , SW4 . For the uppermost gate driver 111 , GD1 , the electrical conductors 119 , 121 and 122 are connected to the drain, gate and source nodes of the NMOS transistor SW1 . The gate terminal of SW1 is charged through two independent charging paths provided within the gate driver GD1 , namely, a first charging path and a second charging path, as described below with reference to FIGS. 2 and 3 .

FIG. 2 is a schematic diagram of a single gate driver 111 ( GD1 ) coupled to a gate terminal of a power transistor. The gate driver 111 includes the above-mentioned input terminal for the pulse width modulated audio signal PWM_1. The PWM audio signal is applied to a level shifter 203, which can shift the DC voltage level of the PWM audio signal and/or increase its amplitude to provide a voltage suitable for driving the NMOS through the remaining gate driver circuit. Output signal of power transistor SW1. The output signal is applied to a controller or sequencer 205 for controlling the charging current supplied to the gate terminal 121 via the first charging path 211 and for controlling the charging current supplied to the gate terminal 121 via the second charging path 209. gate terminal 121 . Additionally, a controller or sequencer 205 is used to control the off state and on state of a controllable discharge path 207 electrically connected between the gate terminal 121 and the source terminal 122 of the NMOS power transistor SW1 . The charging current is supplied from the drain terminal 119 to the gate terminal 121 through the first charging path 211 according to a control signal of the controller 205 . Since the drain terminal of SW1 is electrically coupled to the positive DC supply voltage _VS , the charging current is supplied from a low impedance voltage source with high power. In the current embodiment, the controller 205 is configured to control the charging current to be supplied to the gate terminal through the first and second charging paths by comparing the gate voltage on the gate terminal 121 with a predetermined threshold voltage. When the gate voltage is lower than a predetermined threshold voltage, the controller 205 activates the first charging path 211 and interrupts the charging current supplied from the high power supply voltage HV _boot through the second charging path 209 . When the gate voltage reaches a predetermined threshold voltage, the first charging path 211 is interrupted or disconnected by the controller 205, and the second charging path 209 is activated so that additional charging current is supplied to the gate terminal from the high supply voltage through the second charging path 209. In this way, the second charging path 209 can greatly increase the gate voltage of the NMOS power transistor SW1 above the positive DC supply voltage. In practice, the threshold voltage is very freely selectable and can be defined by any of a number of different mechanisms. However, in the current embodiment, the predetermined threshold voltage of each gate driver is derived from the drain voltage of the associated NMOS power transistor. The predetermined threshold voltage is substantially fixed at a single MOS transistor threshold voltage below the drain voltage of said NMOS power. This single threshold voltage may correspond to a voltage of 0.5 to 1.5 volts for typical CMOS integrated circuit technology. It is generally advantageous to set the predetermined threshold voltage to a voltage close to the drain voltage of the associated power transistor. This setup ensures that the power transistor operates close to its conductive state when the drain voltage is approximately equal to the gate voltage. This scheme generally ensures that the major part of the charging current required at the gate terminal is delivered by the high power efficient DC supply of the output stage, i.e., the positive DC supply voltage _VS in the current embodiment, while the low power efficient high supply voltage Only a relatively small fraction of the total gate charging current is supplied. The time period for charging the gate terminal of the NMOS power transistor SW1 to a voltage approximately of the high power supply voltage HV _boot may be 1 to 20 ns. When the NMOS power transistor SW1 is switched to a conductive state by the combined operation of the first and second charging paths, the time period it remains in this state is defined by the pulse width of the pulse width modulated audio signal PWM_1 . The controller 205 activates the discharge path 207 upon detection of a falling edge or transition in the pulse width modulated audio signal, effectively shorting the gate terminal 121 to the source terminal 122 through a low resistance path. Thus, activation of the discharge path 207 discharges the gate voltage and switches the NMOS power transistor SW1 to a non-conducting state.

FIG. 3 is a hybrid block and transistor level diagram of a single gate driver 111 and GD1 schematically shown in FIG. 1 and FIG. 2 . For simplicity, the first charging path 211 and the second charging path 209 on FIG. 2 are shown here at transistor level, while the level shifter 203 and the linear voltage regulator 330 are shown as circuit blocks. Skilled persons should understand that the controller 205 in FIG. 2 is composed of MOS transistors P1 , N3 , N4 and N5 . The gate driver 111 is implemented as a floating circuit block with respect to ground, suitable for integration in a high voltage portion of a CMOS semiconductor substrate, eg, a high voltage isolation well. A linear voltage regulator 330 or LDO is coupled to the high supply voltage HV _boot , preferably adapted to generate a regulated DC power supply of 3 volts to 5 volts between output terminals V _REG1 and V _REG2 . A start-up current, eg, 0.1 to 1 mA, is provided through the input terminal Is to turn on or activate the linear voltage regulator 330 . The operation of the first charging path 211 is controlled by switching the NMOS transistor N1 which can be controlled by manipulating its gate terminal. The gate terminal of N1 is coupled to the drain of NMOS transistor N4 so that N4 can switch N1 between conducting and non-conducting states. N4 is controlled by the output signal of level shifter 203, which is a pulse width modulated audio signal switched between the regulated voltage levels V _REG1 and V _REG2 described above. Since N4 is in the non-conducting or disconnected state and P1 is in the conducting state, when the output signal is logic low, i.e., voltage V _REG2 , while N1 is in its conducting state, the gate terminal of N1 is dropped to V _REG1 to provide a positive voltage to N1. gate-source voltage. Since N1 is in a conductive state, the gate terminal of NMOS power transistor SW1 is charged by the charging current provided by the positive DC supply voltage _VS through N1 and forward biased series diode D1. Since the capacitance of the gate terminal of N1 in the current embodiment of the invention is very large, eg, 50 pF to 500 pF or about 100 pF, the charging current can reach a peak value of 150 mA or more. The charging current raises the gate voltage on the gate terminal of NMOS transistor SW1 until it reaches a voltage about one diode drop below the positive DC supply voltage, i.e., equal to the drain voltage of SW1 in gate driver 111 in the current embodiment. Pole voltage voltage. Subsequently, N1 switches to a non-conducting state as the gate-source voltage approaches zero. Thus, this voltage is the threshold voltage. During the period of time that the gate terminal of SW1 is being charged by the first charging path, the second charging path comprising NMOS transistor N2 also supplies charging current to the gate terminal of SW1 because N2 is placed in a conductive state by PMOS transistor P1, PMOS Transistor P1 drops the gate terminal of N2 to the regulated supply voltage V _REG1 . However, with the gate voltage of SW1 below the threshold voltage mentioned above, the forward biased diode D2, possibly in combination with the relative sizes of N1 and N2, ensures that the gate-source voltage drop on N2 is much smaller than the gate-source voltage drop on N1 voltage drop to ensure that most of the charging current is provided on the gate terminal of SW1 through N1 or the first charging path. A total charge of 1 to 10nC can be supplied to the gate terminal of SW1 to fully charge it. This total charge is used to charge the gate-source capacitance and gate-drain capacitance of SW1.

When the gate voltage on SW1 reaches the threshold voltage, N1 switches to a non-conducting state, while NMOS transistor N2 remains in a conducting state. Thus, a further charging current is supplied to the gate terminal of SW1 from the high supply voltage HV _boot through the drain and source terminals of N2 arranged in the second charging path. In the current embodiment, the voltage of the high supply voltage HV _boot is substantially higher than the positive DC supply voltage V _S , for example, 3 to 5 volts higher, preferably about 4.5 volts higher. During charging of the gate terminal 121 of SW1 through N2, diode D1 blocks any unintended current flow through N1 back into the positive DC supply voltage connected to the drain of SW1. The gate terminal of SW1 is thus charged through N2 until it reaches a voltage of about one diode drop, ie about 0.5-0.8 volts below the regulation voltage V _REG1 due to forward biased diode D2 . Therefore, the gate terminal of SW1 is raised to a voltage approximately equal to one diode drop below the regulation voltage V _REG1 , and since the latter voltage is approximately equal to the voltage level of the high supply voltage _HVboot , the gate terminal of SW1 is driven to A level of about 4 volts above the positive supply voltage. Therefore, SW1 is fully charged and thus has a very low on-resistance.

When SW1 is turned on or conducting through the operation of the first and second charging paths described above, the output signal changes sharply to logic high within a certain period of time set by the pulse width of the output signal of the level shifter 203 level or the voltage level set by V _REG1 . In response, SW1 switches to a non-conductive state, and the charging current provided through N1 and N2 is interrupted. This is accomplished because P1 switches to a non-conductive state after a logic high signal from the output of level shifter 203; since the gate-source voltage on the NMOS device is forced to approximately 4.5 volts (the difference between the terminals, as described above), N4 switches to a conductive state. N4 then lowers the gate of N1 to V _REG2 , which _switches N1 to a non-conducting state because its gate-source voltage is close to zero. The non-conductive state of N1 interrupts the first charging path to cut off the charging current supplied to the gate terminal of SW1. At the same time, N3 drops the gate of N2 to V _REG2 , which _switches N2 to a non-conductive state, since the gate-source voltage on this MOS transistor is also close to zero, thus interrupting the second charging path. Therefore, the charging current supplied to the gate terminal of SW1 through this path is also interrupted. Finally, the gate and source of SW1 are shorted by N5, which is switched to a conductive state by a logic high level applied on its gate terminal. As a result, SW1 switches to a non-conductive or off state, and the charge on the gate terminal is removed.

The skilled artisan will understand that the controller 205 in the current embodiment of the invention is a relatively simple but effective circuit based on combinatorial logic that operates asynchronously to any clock signals of the load driving components. However, the skilled artisan will appreciate that the controller could also be implemented in other ways, for example using clock sequential logic that runs synchronously with the main system clock signal or other system clock signals available to the load driving components. In the latter embodiment, the controller 205 may comprise, for example, a software programmable or hardwired digital signal processor (DSP) or a general purpose microprocessor.

FIG. 4 is a schematic diagram of a load driving assembly 400 including a plurality of gate drivers GD1 , GD2 , GD3 , GD4 411 , 413 , 415 and 417 according to a second preferred embodiment of the present invention. The load driver 403 includes four cascaded NMOS power transistors SW1, SW2, SW3, SW4, similar to that described in the first embodiment of the present invention. In addition, the overall topology of the plurality of gate drivers GD1, GD2, GD3, GD4 in the current embodiment of the load driving assembly and the gate drivers GD1, GD2, GD3, GD4 described in detail in the first preferred embodiment of the present invention above The structure is the same. However, in the current embodiment, each gate driver's LDO 330 (FIG. 3) uses a bootstrap circuit consisting of cascode transistor switches sw433, sw435, sw437, sw439 and bootstrap capacitors C _b1 , C _b2 , C _b3 and C _b4 . Use a ladder circuit instead. Bootstrap ladders are more power efficient than LDOs because current conduction in each transistor switch is avoided when there is any significant voltage drop across the switch. Thus, preferably, current conduction in the transistor switch is avoided when the voltage drop across the switch is higher than 0.5 volts or higher than 1.0 volts. When an associated gate driver is used to drive an NMOS power transistor, each transistor switch sw433, sw435, sw437, sw439 is placed in a conductive state by an appropriate control signal. The cascaded transistor switches sw433, sw435, sw437, _sw439 are electrically coupled between the low DC supply voltage _VDD and the high supply voltage _HVboot , which is provided through the supply line 431, similar to the high supply voltage mentioned above. The high supply voltage HV _boot includes a supply capacitor C _boot 423 . In practice, the low DC supply voltage V _DD may come from an available standard DC supply, eg, 1.8, 3.3 or 5 volts, for CMOS logic circuits including the Class D amplifier of the load driving assembly 400 in the present embodiment. The lowermost gate driver GD4 is directly powered from the DC power supply as shown in FIG. 4 , and the output voltage of the DC power supply uses a high power supply voltage for the second charging path of the gate driver. This is possible because the gate input of power transistor SW4 does not need to be raised or driven to a voltage above the positive DC supply voltage _VS to switch SW4 into a conductive state. Due to the use of a multilevel output stage topology around _{C fly} 425, the drain of SW4 is only charged to about half of VS. The high power supply voltage HV _boot supplies power to the uppermost gate driver GD1 through the power transistor SW43, or Cb2 through the power transistor sw435. The use of SW433 provides an additional supply voltage input to the bootstrap ladder circuit to reduce the total capacitance required for the bootstrap capacitors C _b1 , C _b2 , C _b3 and C _b4 .

Claims (21)

1. A Class D audio amplifier comprising a load drive assembly connectable to a speaker load via an output, wherein the load drive assembly comprises: a first branch formed between the first DC supply voltage and the output terminal and a second branch formed between the output terminal and the second DC supply voltage, the first branch and the second The branch consists of multiple power transistors coupled in cascade, the output terminal is electrically coupled between the first branch and the second branch, Each of the plurality of power transistors has a gate terminal electrically connected to the first node of the first charging path and the first node of the second charging path of the gate driver, each of the plurality of power transistors has a drain terminal electrically coupled to a second node of the first charging path to provide a first supply voltage to the power transistors, a plurality of component input terminals coupled to respective inputs of a plurality of said gate drivers for supplying modulated input signals thereto, and each gate driver includes: the first charging path, electrically connected between a first voltage source and the gate terminal of the power transistor, for charging the gate terminal to a first gate voltage, the second charging path electrically connected between a second voltage source (HV _boot ) and the gate terminal of the power transistor to charge the gate terminal from the first gate voltage to high A second gate voltage relative to the first gate voltage, wherein the voltage of the second voltage source is higher than the voltage of the first voltage source. 2. The class D audio amplifier according to claim 1, wherein the voltage of the first voltage supply of each gate driver is the drain voltage of the power transistor. 3. A class D audio amplifier according to claim 1 or 2, wherein each gate driver comprises: a controller or a sequencer adapted to control the charging current to the power transistor through the first charging path The supply of the gate terminal controls the supply of charging current to the gate terminal of the power transistor through the second charging path. 4. The class D audio amplifier according to claim 3, wherein the controller or sequencer is adapted to control the charging current through the first power transistor by comparing the gate voltage of the power transistor with a predetermined threshold voltage. A charging path and a supply of the second charging path to the gate terminal of the power transistor. 5. The class D audio amplifier of claim 4, wherein the controller or sequencer is adapted to derive from the drain voltage of the power transistor electrically coupled to the first charging path The predetermined threshold voltage. 6. The Class D audio amplifier of claim 3, wherein the controller or sequencer is adapted to charge the gate of the power transistor via the first charging path for a predetermined charging time period. terminal to supply charging current to reach said first gate voltage; and A charging current is then supplied to the gate terminal of the power transistor through the second charging path for a predetermined period of time. 7. The Class D audio amplifier of claim 3, wherein the first charging path and the second charging path of each gate driver include a controllable FET transistors in series. 8. A Class D audio amplifier according to claim 4, wherein said controller or sequencer is adapted to interrupt supply of charging current from said second voltage supply until said gate voltage reaches said predetermined threshold voltage . 9. The Class D audio amplifier of claim 1 , wherein the second voltage supply of each gate driver has a voltage at least higher than that of the first voltage supply in the conductive state or the on state of the power transistor. The voltage supply has a voltage higher than one gate-source voltage drop of the power transistor. 10. The Class D audio amplifier of claim 1, wherein the first charging path of each gate driver is adapted to charge the gate terminal to the first gate within 100 nanoseconds Voltage. 11. The Class D audio amplifier of claim 1 , wherein the voltage level of the second voltage supply is always at least 2.5 times higher than the voltage level of the first voltage supply during operation of the gate driver volt. 12. The class D audio amplifier according to claim 1, wherein the load driving assembly comprises: a DC voltage source configured to set a predetermined DC voltage difference between a first node located between a pair of cascaded power transistors (SW1, SW2) of the first branch and a second node, the The second node is located between a pair of cascaded power transistors of the second branch. 13. The class D audio amplifier of claim 1, wherein the plurality of power transistors comprises at least one N-channel field effect transistor deposited on a semiconductor substrate. 14. The class D audio amplifier of claim 1, wherein the second voltage supply of a plurality of the gate drivers is electrically connected to a common charge pump capacitor of the second voltage supply. 15. The Class D audio amplifier of claim 1, wherein the load driving component is integrated on a semiconductor substrate. 16. The class D audio amplifier of claim 3, wherein the controller or sequencer is further adapted to control the off state and on state of the controllable discharge path. 17. The class D audio amplifier according to claim 6, wherein the predetermined charging time period is a time period between 5 nanoseconds and 100 nanoseconds. 18. The Class D audio amplifier of claim 10, wherein the first charging path of each gate driver is adapted to charge the gate terminal to the first gate within 50 nanoseconds Voltage. 19. The Class D audio amplifier of claim 10, wherein the first charging path of each gate driver is adapted to charge the gate terminal to the first gate within 20 nanoseconds Voltage. 20. The Class D audio amplifier of claim 13, wherein the semiconductor substrate is silicon, gallium nitride or silicon carbide. 21. The class D audio amplifier of claim 13, wherein the at least one N-channel field effect transistor is NMOS or IGBT.