CN116097560A - Driver circuit - Google Patents

Abstract

A switch driver (401) for outputting a drive signal at an output node (402) for driving a load such as a transducer is described. The driver receives respective high-side and low-side voltages (VinH, vinL) defining an input voltage at a first and second input node and has connections for first and second capacitors (403H, 403L). The switched path network is configured to enable each of the first capacitor and the second capacitor to be selectively charged to the input voltage, the first input node being selectively couplable to a first node (N1) through a path that includes or bypasses the first capacitor, and the second input node being selectively couplable to a second node (N2) through a path that includes or bypasses the second capacitor. The output node (402) is switchable between two switching voltages at the first node or the second node. The driver is selectively operable in different modes of operation, wherein the switching voltage is different in each of the modes.

Description

driver circuit

The field of representative embodiments of the present disclosure relates to methods, apparatus, and/or implementations relating to or relating to driver circuits, and in particular switch driver circuits that may be used to drive transducers.

Many electronic devices include transducer driver circuitry for driving a transducer with a suitable drive signal, for example, for driving an audio output transducer of a host device or a connected accessory with an audio drive signal. energy device.

In some applications, the driver circuit may include a switching amplifier stage, such as a class D amplifier stage or the like, for generating a drive signal for driving the transducer. Switching amplifier stages can be relatively power efficient, and thus can be used advantageously in some applications. Switching amplifier stages generally operate to switch the output node between defined high and low voltages at a duty cycle that provides a desired average output voltage over time.

To provide suppression of switching ripple, some series inductance may be included in the output path. In some implementations, the inductance can be provided by the load itself. For example, for audio applications driving conventional cone and voice coil type loudspeakers, the self inductance of the loudspeaker's voice coil may be sufficient. However, in some implementations it may be advantageous to include an inductor in the output path as a component separate from the load. For example, piezoelectric or ceramic transducers may be advantageously used in some applications due, inter alia, to their relatively thin form factors. The capacitive nature of such transducers means that it may generally be beneficial to include an inductor in series with the transducer.

In applications that include an inductor as a separate component in the output path, the inductor will be chosen to allow the peak expected current to flow without saturation. In some cases, this may require the inductance to be relatively large, which may be undesirable.

Embodiments of the present disclosure relate to drive circuits that at least alleviate at least the above-mentioned problems.

According to an aspect of the present disclosure, there is provided a driver circuit, the driver circuit includes a first switch driver for generating a first drive signal, the first switch driver includes:

a first input node and a second input node for connection to respective high-side and low-side voltages defining an input voltage;

a capacitor node for connection to the first capacitor and the second capacitor;

a driver output node for outputting a first drive signal; and

switch path network;

wherein the switch path network is configured such that in use:

Each of the first capacitor and the second capacitor can be selectively connected in series between the first input node and the second input node to charge to the input voltage; either by a path including the first capacitor in series or by bypassing the a path of a first capacitor selectively couples the first input node to the first selective boost node;

The second input node is selectively coupleable to the second selective boost node by a path comprising a second capacitor in series or by a path bypassing the second capacitor; and

a driver output node is selectively coupled to the first selective boost node or the second selective boost node;

wherein the first switch driver is selectively operable in a plurality of different operating modes, wherein in each of the operating modes, the driver output node is switched between two switch voltages, and the switch voltage is at the Each of the above modes is different.

In some examples, the first switch driver may be selectively capable of operating in any two or more of the following modes:

a first mode, wherein the two switching voltages are a high-side voltage and a low-side voltage;

a second mode in which the two switch voltages are a high-side voltage and a boosted high-side voltage that is greater than the high-side voltage by an amount substantially equal to the input voltage; and

A third mode in which the two switch voltages are a low side voltage and a boosted low side voltage that is lower than the low side voltage by an amount substantially equal to the input voltage.

In the first mode, the first switch driver may be capable of operating in two switch states comprising:

A first state of the first mode, wherein the first input node is coupled to the first selective boost node by a path bypassing the first capacitor, the driver output node is connected to the first selective boost node, and the first capacitor connected between the first selective boost node and the second input node; and

A second state of the first mode wherein the second input node is coupled to the second selective boost node by a path bypassing the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor Connected between the first selective boost node and the second input node.

If capable of operating in the second mode, the first switch driver may be capable of operating in two switching states comprising:

A first state of the second mode in which the first input node is coupled to the first selective boost node by a path comprising a series connected first capacitor, the driver output node is connected to the first selective boost node, and the second a capacitor connected between the first selective boost node and the second input node; and

A second state of the second mode, wherein the first input node is coupled to the first selective boost node by a path bypassing the first capacitor, the driver output node is connected to the first selective boost node, and the first capacitor Connected between the first selective boost node and the second input node.

If capable of operating in the third mode, the first switch driver may be capable of operating in two switching states comprising:

A first state of said third mode, wherein the second input node is coupled to the second selective boost node by a path bypassing the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor connected between the first selective boost node and the second input node; and

A second state of the third mode, wherein the second input node is coupled to the second selective boost node by a path comprising a second capacitor in series, the driver output node is connected to the second selective boost node, and the first A capacitor is connected between the first selective boost node and the second input node.

The capacitor nodes may include first and second capacitor nodes for connecting to opposite sides of the first capacitor and third and fourth capacitor nodes for connecting to opposite sides of the second capacitor, and wherein the first The capacitor node is connected to the first selective boost node, and the fourth capacitor node is connected to the second selective boost node. In some examples, the second capacitor node and the third capacitor node may be connected to each other.

In some implementations, the switch path network can include:

a first input switch path for connecting the first input node to the first selective boost node;

a second input switch path for connecting the first input node to the second capacitor node;

a third input switch path for connecting the second input node to the third capacitor node;

A fourth input switch path for connecting the second input node to the second selective boost node.

In some examples, each of the first input switch path, the second input switch path, the third input switch path, and the fourth input switch path may include respective FET switches.

In some examples, the switch path network may include a first output switch path for connecting the driver output node to the first selective boost node, and a second output switch path for connecting the driver output node to the second selective boost node. Two output switch paths. Each of the first output path and the second output path may include a plurality of FET switches connected in series. In some examples, there may be a bias controller for each of the first and second output switching paths. Each bias controller may be configured to control the plurality of FETs of the associated first or second output switching path when the associated one of the first or second output switching paths is non-conducting The bias voltage between the two. In some examples, the bias controller for the first output switch path may include a device for selectively connecting the midpoint node between the first capacitor and the second capacitor at a point between the two FETs to the transistor of the relevant one of the first output switch path or the second output switch path.

In some examples, the first and second selective boost nodes may include output nodes of a first boost stage, and the switch driver circuit includes at least one additional boost stage. Each additional boost stage may include a first additional capacitor and a second additional capacitor. The switch path network may be operable such that said first additional capacitor and said second additional capacitor are selectively connected in series at the respective first and second voltage inputs to the additional boost stage and The respective first and second selective boost nodes of the additional boost stages are bypassed in or in the connection. Each additional boost stage may be configured to receive at its first and second inputs the voltage at the first and second selective boost nodes of the preceding boost stage, and The switch path network may be configured to selectively connect the output driver node to a selective boost node of a last one of the additional boost stages.

In some examples, each additional boost stage may also be configured to receive a midpoint voltage at a third input node from the previous boost stage, the midpoint voltage being the first selective boost voltage of the previous boost stage. voltage node and the midpoint between the voltage at the second selective boost node. An additional boost stage may be operable to selectively connect a first additional capacitor between a first input node and a third input node of that additional boost stage to charge said first capacitor, and selectively A second additional capacitor between the third input node and the second input node of that additional boost stage is connected to ground to charge the second additional capacitor.

The driver circuit may also include a controller configured to selectively control the first switch driver to controllably vary the mode of operation and the voltage at which the driver output node switches between associated switch voltages having a certain duty cycle. duty cycle.

In some implementations, the driver circuit may further include a second switch driver for generating a second drive signal, the driver circuit configured to use the first drive signal and the second drive signal in a bridge-tied load configuration to drive load. The second switch driver may have the same structure and be operable in the same manner as the first switch driver.

Aspects also relate to a driver circuit including a load configured to be driven by the first drive signal. In some examples, the load may be connected to the driver output node of the first switch driver via a series inductor. The load may be at least one of an audio output transducer and a tactile output transducer. In some examples, the load may be a piezoelectric transducer or a ceramic transducer.

Aspects also relate to electronic devices comprising the driver circuit of any of the embodiments described herein.

In another aspect, a switch driver for generating a drive signal is provided, the switch driver comprising:

a first voltage input node and a second voltage input node, the first voltage input node and the second voltage input node are used to receive the first voltage input and the second voltage input;

a capacitor node for connection to the first capacitor and the second capacitor;

a driver output node for outputting a first drive signal; and

switch path network;

The switch driver is operable in use to:

selectively driving the first selective boost node to the first voltage input or the first voltage input positively boosted by the voltage of the first capacitor;

selectively driving the second selective boost node to the second voltage input or the second voltage input negatively boosted by the voltage of the second capacitor; and

connecting the driver output node to a selected one of the first selective boost node and the second selective boost node;

wherein the first switch driver is selectively operable in a plurality of different operating modes, wherein in each of the operating modes, the driver output node is switched between two switch voltages, and the switch voltage is at the Each of the above modes is different.

In another aspect, there is provided a switch driver for generating a drive signal within a defined output voltage range for driving a load, the switch driver comprising:

a first voltage input node and a second voltage input node for receiving respective high-side voltage inputs and low-side voltage inputs defining input voltages;

a capacitor node for connection to at least one capacitor;

an output node for outputting a driving signal; and

switch path network;

wherein the switch driver is operable to generate a driver signal by selectively operating in one of a plurality of different modes, wherein in each of said modes the driver output node is switched between two switch between several switch voltages, where the switch voltage is different in each mode, and the switch voltage in each mode provides only a portion of the defined output voltage range.

Aspects also relate to a switching driver for driving a load, the switching driver comprising a switching network for switching the driver output node between different switching voltages and a capacitor node for connecting to a first capacitor and a second capacitor, Wherein the switching network is operable such that the first capacitor is selectively connectable to provide a positively boosted switching voltage and the second capacitor is connectable to provide a negatively boosted switching voltage.

It should be noted that any feature described herein may in fact be implemented in combination with any one or more of the other described features unless expressly indicated to the contrary herein or otherwise clearly incompatible.

In order to better understand the examples of the present disclosure, and to show more clearly how the same may be implemented, reference will now be made, by way of example only, to the following drawings, in which:

Fig. 1 depicts an example of a conventional drive circuit;

FIG. 2 illustrates an output waveform of one of the switch drivers of FIG. 1;

FIG. 3 illustrates exemplary output waveforms of a switch driver according to one embodiment;

Figure 4 illustrates an example of a switch driver according to an embodiment;

Figures 5a and 5b illustrate two states of operation of the switch driver of Figure 4 in a first mode of operation;

Figures 6a and 6b illustrate two states of operation of the switch driver of Figure 4 in the first mode of operation;

Figures 7a and 7b illustrate two states of operation of the switch driver of Figure 4 in a third mode of operation;

Figure 8 illustrates an example of a drive circuit according to one embodiment;

Figure 9 illustrates an example of an implementation of a switch driver in more detail;

Figure 10 illustrates an example of a switch driver with multiple boost stages, according to one implementation; and

Figure 11 illustrates another example of a switch driver with multiple boost stages according to one implementation.

The following description sets forth exemplary embodiments according to the present disclosure. Other exemplary embodiments and implementations will be apparent to those of ordinary skill in the art. Furthermore, those of ordinary skill in the art will recognize that various equivalent techniques may be applied in place of or in combination with the embodiments discussed below, and all such equivalents are considered to be encompassed by this disclosure.

FIG. 1 shows an example of a conventional driver circuit 100 for driving a load 101 . In this example, the load 101 is connected in a bridge-tied load (BTL) configuration, and each side of the load is connected to a respective half-bridge switch driver 102-1 and 102-2 (which may be collectively or individually referred to as is the switch driver 102). However, it will be appreciated that a single-ended drive circuit may be used in some implementations, where one side of the load is connected to the switch driver 102 and the other side of the load is, in use, coupled to a defined voltage, such as ground.

Each switch driver 102 includes switches 103a and 103b, which typically may include MOSFETs, for selectively connecting the output node 104 to a high-side voltage VH or a low-side voltage VL. In some examples, the high side voltage VH may be a supply voltage and the low side voltage may be ground.

The switches 103a and 103b of the switch driver 102 are controlled by switching signals generated by the respective modulators 105-1 and 105-2 (which may be collectively or individually referred to as the modulator 105) based on the input signal Sin The input signal may be, for example, an input audio signal. Those skilled in the art will understand that the modulator 105 can generate PWM or PDM switching signals based on the input signal.

FIG. 1 also shows that the output path from the switch driver 102 - 1 to the load 101 includes a series inductor 106 . A series inductor 106 may be included to suppress switching fluctuations in the output voltage and present a high impedance at the output node 104 of the FET switches 103a and 103b at and above the switching frequency while allowing current flow in the signal frequency band of interest (e.g., at audio frequency) flows to the load 101.

As described above, the sizing of an inductor can be limiting in some cases, especially with respect to the peak current that can flow without saturation.

The skilled artisan will understand that the rate of change of current through an inductor (di/dt) is related to the voltage _V across the inductor and inductor L as follows:

di/dt = V _L /L Equation (1)

So in general, a larger inductance may be needed to limit the maximum rate of current change.

In the example of the conventional driver circuit of FIG. 1 , the high-side voltage VH and the low-side voltage VL are selected to provide each output switch circuit 102 with a specific defined range of output voltages. That is, switch driver 102-1 is operable to provide a voltage between at or just above VL (by connecting output node 104 to VL during substantially the entire duty cycle) to a voltage at or just below VH over time. The average output voltage over a range of voltages (by connecting output node 104 to VH during substantially the entire duty cycle).

2 illustrates an example of switching waveforms at the output node 104 of the switch driver 102-1 along with an average demand voltage 201 (ie, the desired output signal). Output node 104 switches between switching voltages VH and VL with a duty cycle (typically expressed as a proportion of the time spent connecting to high-side voltage VH) that varies according to demand voltage 201 .

As output node 104 switches between switching voltages VH and VL, the inductor current will ramp up or down. The amount of fluctuation in the inductor current will depend on the duty cycle of the switching voltage and also on the difference between the switching voltages VL and VH. A relatively high voltage difference between VL and VH may thus result in current fluctuations of greater magnitude, which may be undesirable.

Embodiments of the present disclosure relate to a driver circuit suitable for driving a transducer, the driver circuit comprising at least one switch driver for generating a drive signal at an output node in a defined output voltage range, wherein the switch driver is capable of operating in a plurality of different operating modes, wherein in each of the different operating modes the output node switches between two voltages that provide only part of a defined output voltage range, that is, at a given The voltage range between the two switching voltages in the fixed mode forms a subset of said defined voltage range.

The switch driver thus switches between two defined switch voltages with a controlled duty cycle to provide a desired average output voltage, which may be within a defined voltage range between the high voltage VH and the low voltage VL internal changes. However, rather than switching between only these peak high and low voltage levels of the output range as discussed with respect to FIGS. only part of the two switching voltages switches between. Therefore, the output node switches between two switching voltages that differ from each other by less than the entire output range.

In effect, a switch driver can be considered to operate at a variable voltage rail that is controllably varied in different operating modes to provide different operating ranges.

Figure 3 illustrates this principle. FIG. 3 illustrates switching waveforms and average voltage requirements 301 at an output node of a switching driver according to an example. In this example, the average voltage demand is the same as that depicted in FIG. 2 and can vary across the output range between low voltage VL and high voltage VH. However, in this example, the switch driver is capable of operating in different modes. In one mode of operation, the output node is switchable between a low voltage VL and a first intermediate voltage VA. In another mode of operation, the output node is switchable between a first intermediate voltage VA and a second intermediate voltage VB. In yet another mode of operation, the output node is switchable between the second intermediate voltage VB and the high voltage VH.

When the average voltage demand is lower than the intermediate voltage VA, the output stage can operate in a mode switched between VL and VA. When the average voltage demand is greater than the first intermediate voltage VA but lower than the second intermediate voltage, the output node can be switched between VA and VB, and if the voltage demand is higher than VB, the switch driver can operate in said mode to The voltage at the output node is switched between VB and a high voltage VH. In each case, the duty cycle is appropriately controlled to provide the desired average voltage.

Operating in this way means that the voltage difference between the two switch voltages in use at any one time is reduced compared to the example of FIG. 2 . This advantageously reduces maximum voltage fluctuations in use.

Figure 3 shows the entire output range between VL and VH provided by three different operating modes. In at least some embodiments, it may be desirable that the voltage ranges of each operating mode, ie, the voltage difference between the associated two switching voltages VL and VA, VA and VB, or VB and VH, be the same as each other. However, in other implementations there may be a different number of operating modes across the entire output range of the switching output stage, eg, in some implementations there may be only two operating modes or there may be more than three operating modes.

FIG. 4 illustrates an example of a switch driver 401 according to an embodiment. The switch driver 401 includes first and second input terminals for connecting to a high-side voltage VinH and a low-side voltage VinL (eg, a positive supply voltage and ground), respectively. It will be understood that references to high and low side voltages (or sometimes just high and low voltages) will indicate that the high side voltage is relatively more positive than the low side voltage, and do not imply the magnitude of such voltages. The difference between the low-side voltage VinL and the high-side voltage VinH defines the input voltage Vin of the output stage. The switch driver 401 also has a driver output node 402 for outputting a drive signal Vout.

The switch driver 401 also includes first and second capacitors 403H and 403L and a switch path network. The switch path network is arranged such that the first and second capacitors 403H and 403L can be selectively charged by the input voltage Vin and in at least one mode of operation said first and second capacitors are selectively Ground is coupled in series with one of the voltage inputs VinH or VinL to the output node 402 for contributing to the output voltage, eg, to provide a positive or negative boost of the associated voltage input. Each switch path includes one or more switches, which may typically be MOSFETs, as will be described in more detail below.

One side of the first capacitor is connected to the first node N1. The switch path network includes a switch path SWHA for selectively connecting the first input terminal to the first node N1 by a path bypassing the first capacitor 403H such that the first node can be driven substantially equal to high side voltage VinH. The switch path SWHB is arranged to selectively connect the first input terminal to the first node N1 via a path comprising a series connected first capacitor 403H such that the voltage on this capacitor contributes to the voltage at node N1. Node N1 can therefore be considered as a selective boost node, which can be selectively boosted to a voltage higher than the high-side input voltage.

Similarly, one side of the second capacitor 403L is connected to the second node N2, and the switch path network includes a switch path SWLA for selectively connecting the second input terminal to the second node N2 bypassing the second capacitor 403L, and The switch path SWLB for connecting the second capacitor 403L in series between the second input terminal and the second node N2, such that the voltage on the second capacitor 403L contributes to the voltage at the node N2, in this case by reducing the voltage or by negatively boosting said voltage. The node N2 can thus be regarded as a second selective boost node which can be selectively controlled to a voltage equal to or lower than the low-side voltage VinL.

Output switch paths SWO1 and SWO2 are provided to allow the driver output node 402 to be selectively connected to the first selective boost node N1 or the second selective boost node N2 .

The switch path network is also operable to allow charging of the first and second capacitors 403H and 403L by the input voltage Vin (ie, the difference between VinH and VinL). In the embodiment of FIG. 3, the capacitors are connected to the common midpoint node N3, and thus the switch paths SWHB and SWLB can be used to selectively connect the first capacitor 403H to the second input terminal or to selectively connect the second capacitor 403L to to the first input, as will be discussed in more detail below. However, in other arrangements there may be additional switching paths for charging the capacitors if required, at the expense of additional circuitry.

It will be appreciated that the switch driver may be implemented as an integrated circuit (IC), but in some embodiments the first and second capacitors may not comprise integrated components and may be separate components connected to the IC in use, i.e., the capacitors may off-chip. The first capacitor 403H may thus be connected between the first capacitor node and the second capacitor node, and the second capacitor may be connected between the third capacitor node and the fourth capacitor node (not separately identified in FIG. 4 ), so The third capacitor node and the fourth capacitor node may be connected to appropriate contacts of the IC for connection to an external capacitor.

The switch driver 401 of FIG. 4 may be capable of operating in three different modes of operation. In the first mode of operation, output node 402 is switchable between VinH and VinL in order to provide an average output voltage in the range between VinL and VinH. The first mode can be considered a non-boost mode of operation. In the second mode of operation, the output node 402 is switchable between VinH and VinH+(VinH-VinL) to provide a voltage in the range between VinH and 2VinH-VinL (i.e., Vin(=VinH-VinL) higher than VinH range) in the average output voltage. The second mode can be considered a positive boost mode of operation. In a third mode of operation, the output node 402 is switchable between VinL and VinL-(VinH-VinL) to provide an average voltage in the range between 2VinL-VinH and VinL (ie, the voltage range of Vin lower than VinL). The output voltage. The third mode can be considered as a negative boost mode of operation.

The output voltage of the switch driver can thus be controlled to have an average value of any value within a voltage range that can take equal to three times the input voltage Vin by selectively operating in the appropriate mode of operation. Each of the operating modes may provide an average output voltage in a different subrange, where the magnitude of each subrange is equal to the input voltage Vin.

Figures 5a and 5b, Figures 6a and 6b, and Figures 7a and 7c respectively illustrate a configuration in which the switch driver is connected to receive a supply voltage VS at a first input and to ground (ie, 0V) at a second input. Operation in the first mode, second mode and third mode of the example.

5a and 5b illustrate the operation in the first mode. In this first mode, the switch driver can be controlled to adopt a first state to provide a voltage equal to +VS at the output node 402 and a second state to provide a voltage equal to 0V at the output node 402 .

Figure 5a shows that in the first state of the first mode, the switches of switch paths SWHA and SWO1 can be closed to connect the first input to the selective boost node N1, which is connected to to the driver output node 402 such that in this example the output voltage Vout is equal to +VS. Additionally, in this first state, the switch of the switch path SWLB is closed to connect the first capacitor 403H between the first voltage input and the second voltage input in order to charge the first capacitor to the voltage VS. The other switch paths are open and thus effectively float the second capacitor 403L and will maintain its charge.

Figure 5b shows that in the second state of the first mode, the switches of switch paths SWLA and SWO2 can be closed to connect the second input to a second selective boost node N2, the second selective The boost node is connected to the driver output node 402, so in this example the voltage at the driver output node is equal to 0V. Additionally, in this second state, the switch of the switch path SWHB is closed to connect the second capacitor 403L between the first voltage input and the second voltage input in order to charge the second capacitor to the voltage VS. This leaves the other switching paths open and thus effectively floats the first capacitor 403L and will maintain its previous charge.

In operation in the first mode of operation, the switch driver can thus be controlled to alternate between the first state and the second state with an appropriate duty cycle to provide via said duty cycle within the average value of the output voltage.

6a and 6b illustrate the operation in the second mode. In this second mode, the switch driver can be controlled to adopt a first state to provide a voltage equal to +2VS at output node 402 and a second state to provide a voltage equal to +VS at output node 402 .

6a shows that in the first state of the second mode, the switch of switch path SWHB can be closed to connect the first input terminal to the selective boost node N1 node via the first capacitor 403H, and switch path SWO1 The switch of is closed to connect the first selective boost node to the driver output node 402 . In use, the first capacitor 403H will be charged to the input voltage VS during a different state, ie one of the second state of the second mode or the state of one of the other modes of operation. In this first state of the second mode, the first capacitor is connected to its positive plate coupled to the selective boost node N1 and thus the output node 402 such that the voltage Vout at the output node is equal to +2VS.

In said first state of said second mode, the switch of switch path SWLA is also closed to connect a second capacitor 403L between the first voltage input and the second voltage input in order to charge the second capacitor to Voltage vs.

Fig. 6b shows that in the second state of the second mode, the switches of switch paths SWHA and SWO1 can be closed to connect the first input terminal to the first selective boost node N1, the first selective The boost node is connected to output node 402, so in this example the output voltage is equal to +VS. Also, in this second state, the switch of switch path SWLB is closed to connect the first capacitor 403H between the first voltage input and the second voltage input in order to (re)charge the first capacitor to voltage VS. This leaves the other switching paths open, and thus effectively floats the second capacitor 403L and will maintain its previous charge.

7a and 7b illustrate the operation in the third mode. In this third mode, the switch driver can be controlled to adopt a first state to provide a voltage equal to 0V at the output node 402 and a second state to provide a voltage equal to -VS at the output node 402 .

Fig. 7a shows that in said first state of said third mode, the switches of switch paths SWLA and SWO2 can be closed to connect the second input terminal to a second selective boost node N2, said second selective The boost node is connected to output node 402, so in this example the output voltage is equal to 0V. Additionally, in this first state, the switch of the switch path SWHB is closed to connect the second capacitor 403L between the first voltage input and the second voltage input in order to charge the first capacitor to the voltage VS. The other switching paths are left open, and thus effectively floats the first capacitor 403H and will maintain any previous charge.

7b shows that in the second state of the third mode, the switch of switch path SWLB can be closed to connect the second input terminal to the second selective boost node via the second capacitor 403L, and switch path SWO2 Close to connect the second selective boost node to driver output node 402 . As noted above, in use, the second capacitor 403L is charged to an input voltage, which in this example is equal to VS, in one of the other states (ie, the first state or one of the other modes of operation) and in this second state of said third mode, the second capacitor is coupled therewith to the second selective boost node N2 and thus the output node 402 The negative plate of is connected such that the voltage Vout at the output node is equal to -VS.

In this second state of the third mode, the switch of the switch path SWHA is also closed to connect the first capacitor 403H between the first voltage input and the second voltage input in order to charge the first capacitor to the voltage vs.

It will thus be appreciated that the switch driver 401 is capable of operating in three different modes of operation to provide an output voltage variable within a voltage range equal to 3VS, ie between a low voltage -VS and a high voltage +2VS. This can be considered as a symmetrical output voltage about the midpoint +0.5VS.

It will be appreciated that providing the same output voltage range using the conventional driver depicted in Figure 1 would require an input voltage VH-VL equal to 3VS. Embodiments of the present disclosure may therefore use lower input voltages than the conventional approach of FIG. 1 to provide a given range of output drive voltages, thus reducing supply voltage requirements.

In each of the second and third modes of operation, one of the capacitors 403H or 403L is coupled in series with the output node 402 in one of the states. Capacitors 403H and 403L may be selected to have capacitance values sufficient to allow the required load current without any significant voltage drop during the switching cycle. The capacitance of capacitor 403H or 403L may also be chosen to provide a suitably low effective impedance (considered a switched capacitor resistor for driving a load). In some cases, where the load is primarily capacitive, the capacitance of capacitor 403H or 403L may be relatively large compared to the capacitance of load 101 .

It will be noted that in this first mode of operation, in the first state, the output node 402 is connected to the supply voltage VS through the switches of the associated switch path, and the capacitors 403H and 403L are not connected in series between the first input terminal and the output node , and thus the output voltage is actually provided directly by the supply voltage VS. This is optimal for highly reactive load impedances where peak currents occur at or near voltage zero crossings.

In each of the operating modes, the first capacitor and the second capacitor are charged to the same voltage, in this example an input voltage equal to VS, in alternating states of the duty cycle. The first and second capacitors 403H and 403L are not used to contribute to the output voltage in this first mode of operation, however, operation in the first mode precharges the capacitors to the correct voltage level. Likewise, in the second mode of operation, the second capacitor 403L is not used to contribute to the output voltage, but is precharged for use in the third mode of operation, and in the third mode of operation, the first capacitor 403H is not used to contribute to output voltage, but is precharged to be ready for use in the second mode of operation. The switch driver can thus easily switch between different modes of operation simply by controlling which switches of the switch path are opened and closed.

It will be noted that the first capacitor 403H is therefore only used to contribute to the output voltage in the second mode to positively boost the voltage at the selective boost node N1 to +2VS, and that the second capacitor is only used in the third mode of operation , to negative boost the voltage at the second selective boost node N2 to -VS. If either of these modes of operation is not required in a particular implementation, the relevant one of the first or second capacitors 403H or 403L may be omitted and the output stage operated in only the other two modes.

Referring again to FIG. 4 , in order to control the operation of the switches to implement the different modes of operation, the driver circuit may include a controller 404 . The controller may receive an input signal Sin and determine an appropriate mode of operation based on the input signal Sin and generate a switch control signal Scon for controlling an associated switch of the switch path. The controller 404 may generate switch control signals to alternate between the associated first state and the second state at an appropriate duty cycle (taking into account switching the switching voltage of the output node between the associated modes of operation) in order to provide the desired the average output voltage.

The drive circuit can be implemented using switching drivers such as the one depicted in FIG. It may eg be equal to +VS/2.

However, in some implementations, the driver circuit may include two switch drivers arranged to drive the load in a BTL configuration. Figure 8 illustrates a drive circuit 800 having respective first and second switch drivers 401-1 and 401-2 for driving a load in a BTL arrangement, according to one embodiment. Each of switch drivers 401 - 1 and 401 - 2 may be a switch driver such as that depicted in FIG. 4 . Each of the switch drivers 401-1 and 401-2 may thus include respective first and second capacitors (this allows the operating modes and duty cycles of the switch drivers 401-1 and 401-2 to be controlled independently of each other) .

In the example of FIG. 8, the two switch drivers 401-1 and 401-2 are supplied with mutually identical voltage inputs VinH and VinL (and thus each of the switch drivers 401-1 and 401-2 receives the same input voltage ). This arrangement is operable to generate a drive voltage across the load 101 of up to a maximum magnitude of substantially 3(VinH−VinL), i.e. three times the input voltage Vin, by operating the load in the second mode The switch driver on one side of the load to provide an output voltage of 2VinH-VinL while operating the switch driver on the other side of the load in a third mode to provide an output voltage of 2VinL-VinH.

Figure 8 illustrates that each switch driver 401-1 and 4021-2 may be controlled by a respective controller 404-1 and 404-2, but it will be appreciated that at least some of the functionality of the controllers 404-1 and 404-2 may be shared sex.

Referring again to FIG. 4 , each of the switch paths of the switch driver 401 may include at least one suitable FET. In some applications, each switch path may include a single FET switch. However, in some applications, particularly for any switch path that in use may experience higher voltage stresses in the off or disconnected state that may be greater than the voltage tolerance of a single FET, it may be desirable to connect two or more FETs in series. FETs implement at least some of the switching paths.

For example, referring again to FIGS. 5a and 5b, in the first state of the first mode, the voltage at the selectively boosted node N1 is +VS, the voltage at the midpoint node N3 is 0V, and the selectively boosted node N2 The voltage at is equal to -VS (since the positive plate of the second capacitor 403L is coupled to 0V). The magnitude of the voltage difference across open switch paths SWHB and SWLA is thus equal to VS, but the magnitude of the voltage difference across switch path SWO2 is 2VS. In the second state of the first mode, the negative plate of the first capacitor 403H is coupled to the input voltage VS, and thus the voltage at node N1 is equal to +2VS, while the voltage at node N3 is +VS and the voltage at node N2 is 0V. In this state, the magnitude of the voltage difference across non-conductive switch paths SWHA and SWLB is equal to VS, but the magnitude of the voltage difference across switch path SWO1 is 2VS.

In the second mode of operation depicted in Figures 6a and 6b, the voltage at the selectively boosted node N1 is +2VS in the first state and +VS in the second state, at the selectively boosted node N2 The voltage at is 0V in the first state and -VS in the second state, and the voltage at the midpoint node N3 is +VS in the first state and 0V in the second state. In this mode of operation, the magnitude of the voltage difference across switch path SWO2 is thus equal to 2VS, while the magnitude of the voltage difference across the other switch paths in the two states is at most equal in magnitude to VS. Likewise, in the third mode of operation depicted in Figures 7a and 7b, the voltages at nodes N1, N2 and N3 vary in the same manner as in the second mode, but in this mode the switching path SWO2 remains closed. The voltage difference across switch path SWO1 is thus equal in magnitude to 2VS, while the magnitude of the voltage difference across the other switch paths in both states is at most equal in magnitude to VS.

Switch paths SWO1 and SWO2 (which may be referred to as output switch paths) connected to output node 402 may therefore experience greater voltage stress in the off state than other switch paths.

In some implementations, the switch driver may be implemented using a FET with a drain-source voltage tolerance that is greater in magnitude than the input voltage, eg, the breakdown voltage may be greater than VS in the examples described above. However, it may not be practical or convenient to implement a FET with a voltage tolerance equal to 2VS in magnitude. For example, in some applications the supply voltage VS may be around 20V or so, and a FET rated for operation at 20V may be implemented, but it may not be practical to provide a FET with a voltage tolerance of 40V.

In this example, switch paths SWHA, SWHB, SWLA, SWLB may each be implemented using a single suitable FET. However, in use, when in the off state, the voltage difference across output switch paths SWO1 and SWO2 may exceed this voltage tolerance. In this case, the output switch paths SWO1 and SWO2 of the switch driver may be implemented by connecting two or more FETs in series, as shown in FIG. 9 .

FIG. 9 shows that the output switch path SWO1 can be implemented by connecting two FETs 901H-1 and 902H-2 in series, and that the switch path SWO1 can be implemented by connecting two FETs 901L-1 and 902L-2 in series. In use, when the associated switch path is in the off state, a voltage difference of magnitude 2VS will be applied across the two FETs in series, and each of the series connected FETs may experience a voltage of magnitude VS stress.

In some applications, to ensure that voltage stress is properly shared across the two FETs of an output path, when the associated output path is in the off state, the midpoint between the two FETs of the associated output path (i.e., respectively The voltage at the node between 901H-1 and 901H-2 and the node between 901L-1 and 901L-2) is controlled to a desired voltage. The voltage at such nodes can be controlled by a bias controller such that the voltage stress across each of FETs 901H-1 and 901H-2 or FETs 901L-1 and 901L-2 is substantially equal. The voltages at these nodes of the associated output paths can be controlled in a variety of ways by suitable bias controllers, but in some embodiments transistors 902H and 902L can be connected between midpoint node N3 and the FETs of output switch paths SWO1 and SWO2. between corresponding nodes. In use, either transistor 902H or 902L may be turned on when the associated switch path is in the off state. This will cause the node between the FETs of the output switch path SWO1 or SWO2 to be regulated to a voltage Vs different from the output voltage, thus ensuring The magnitude of the voltage stress is basically VS. Transistors 902H and 902L can be implemented as relatively small devices because they only need to handle relatively small amounts of current during transitions.

Figure 9 shows that the other switch paths SWHA, SWHB, SWLA, SWLB are each implemented using a single FET, and thus the implementation of Figure 9 uses eight FETs to provide the required switch paths.

Referring again to FIG. 4 , as discussed above, the switch driver 401 is capable of operating in three modes. In a first mode, which may be considered a non-boost mode of operation, capacitors 403H and 403L are not used to contribute to the voltage at output node 402, and output node 402 is alternately connected to the high-side voltage in a manner similar to a conventional switch driver VinH or low side voltage VinL. In a second mode of operation (second mode), which may be considered a positive boost mode of operation, the voltage at the selective boost node N1 may be alternately boosted to VinH+Vin, or connected to VinH only. In a third mode, the node selective boosting voltage at node N2 can be alternately boosted or changed to VinL-Vin, or connected to VinL only.

Capacitors 402H and 402L together with switch paths SWHA, SWHB, SWLA and SWLB can thus be considered to collectively provide an initial selective boost stage of the switch driver, with switch paths SWO1 and SWO2 providing the output path stage.

In some embodiments, the switch driver may include one or more additional selective boost stages to allow for another variation of the voltage supplied to the output node, and thus allow for more modes of operation at a given input voltage and / or wider output voltage range. The switch driver may thus be a multi-level switch driver.

In some examples, one or more additional boost stages may have the same general operating structure as described with reference to FIGS. 4 and 5a-7b.

FIG. 10 illustrates an example of a multi-level switch driver 1000 with multiple selective boost stages according to one implementation. Figure 10 shows an example with two selective boost stages 1001 and 1002 and an output path stage 1003, but it will be understood that one or more other selective boost stages may be added in other implementations.

In this embodiment, the first selective boost stage 1001 has similar components identified by the same reference numerals as discussed above with respect to FIG. 4 . The second selective boost stage 1002 has like components identified by like references suffixed with "2".

In the example of FIG. 10 , the voltages at the selective boost nodes N1 and N2 of the first selective boost stage 1001 are supplied as the respective high-side and low-side voltages VH2 and VL2 of the subsequent selective boost stage 1001 . Assuming that the capacitors 403H and 403L of the first stage 1001 are each charged to the input voltage Vin (=VinH-VinL) and that these capacitors are connected in series between N1 and N2, it will be appreciated that the voltage difference between VH2 and VL2 will in use be Equal to 2Vin.

The switch driver 1000 of FIG. 10 is operable to provide the same output as the first, second, and third modes described above, but is additionally operable to provide an additional boost mode, which may be referred to as a positive double boost mode. boost mode and negative double boost mode.

To provide an output in the first mode (i.e., the non-boost mode of operation), the first stage 1001 and the output stage 1003 may operate together in the same manner as the two states of the first mode described with respect to FIGS. 5a and 5b, while The second stage 1002 switches between the same two states simultaneously. This will alternately connect output node 402 to voltage inputs VinH and VinL while charging capacitors 403H and 403L of the first stage to the input voltage Vin and capacitors 403H-2 and 403L-2 of the second stage to 2Vin.

In order to provide the output of the second mode, the first stage 1001 and the output stage 1003 may be operated in the two states of the second mode described with reference to Figures 6a and 6b. This provides the desired voltage level at node N1. Switch path SWHA- 2 may remain closed to connect node N1 to output node 402 to provide the desired output voltage. Switch path SWLB-2 may also be closed to keep capacitor 403H charged. Similarly, to provide a third mode of output, the first stage 1001 and the output stage 1003 may operate in the two states of the third mode described with reference to Figures 7a and 7b to provide the desired voltage level at node N2, The switch path SWL2-2 of the second stage is closed, and the switch path SWHB-2 is closed to charge the capacitor 403L2.

To provide an additional double boost mode, the first stage 1001 can be operated in both states of the second mode or the third mode while operating the second stage 1002 in the same state. For positive double boost mode, the output node will thus vary between VinH+Vin and VinH+3Vin. For negative double boost mode, the output node will thus vary between VinL - Vin and Vin + 3Vin.

Thus, if the input voltages VinH and VinL are positive supply voltage VS and ground 0V, respectively, the switch driver 1000 of FIG. 10 is selectively operable to provide , 0V to -VS, and -VS to -3VS outputs.

Additional boost stages may be included if desired, allowing additional boosting of the output voltage. However, it will be appreciated that the effective input voltage of each stage is twice that of the preceding stage, and that the voltage range of the additional boost mode is thus doubled at each stage. This may mean that for some modes of operation, the difference between the switch voltages in relevant modes may be relatively high, where associated problems with switching result in relatively high current rates. Also, the voltage stored by the capacitors of the later boost stages may be relatively large, which may result in relatively large voltage stress of some components.

FIG. 11 illustrates another example of a switch driver 1100 with multiple selective boost stages. Figure 11 shows an example with two selective boost stages 1101 and 1102 and output path stage 1003, but it will be understood that one or more other selective boost stages may be added in other implementations.

Switch driver 1100 has similar components to switch driver 1000 discussed with respect to FIG. 10, but in the embodiment of FIG. In addition to the input of , the second stage also receives the voltage at node N3 of the first stage 1101 . The voltage at node N3 is a midpoint voltage VM between the voltages of selectively boosted nodes N1 and N2, and is therefore always lower than the voltage at node N1 by voltage Vin and higher than the voltage at node N2 by voltage Vin. Midpoint voltage VM is used to selectively charge capacitors 403H and 403L such that these capacitors are charged to a voltage equal to Vin.

The switch driver 1000 of FIG. 10 is operable to provide the same output as the first, second, and third modes described above, but is additionally operable to provide an additional boost mode in which the voltage may additionally be boosted or Negative boost voltage equal to the magnitude of Vin.

Thus, if the input voltages VinH and VinL are positive supply voltage VS and ground 0V, respectively, the switch driver 1100 of FIG. 11 is selectively operable to provide , 0V to -VS, and -VS to -2VS outputs.

Additional boost stages may be included if desired, allowing additional boosting of the output voltage.

Thus, in general, embodiments of the present disclosure relate to a switch driver suitable for driving an output transducer operable to provide an output voltage with a voltage within a defined range of output voltages (e.g., between the low-side voltage VL and the high-side voltage VL). Voltage VH) average voltage drive signal. The switch driver is capable of operating in a number of different modes, wherein in each of the modes the driver output node switches between two switch voltages with a controlled duty cycle, wherein the switch voltage is switched between each modes are different, and the switching voltage in each mode provides only a portion, ie, a subset, of the defined output voltage range.

In at least some embodiments, the switch driver can include at least one selective boost stage having a first input and a second input for receiving a high-side input voltage and a low-side input voltage terminal and includes first and second capacitors and a switch path network. The switch path network may include a switch path for connecting the first capacitor in series between the first input terminal and the first selective boost node, and a switch path for connecting the first input terminal directly to the first selective boost node. The switching path of the voltage node (ie, not via the first capacitor or the second capacitor). The first circuit mode can thus be selectively driven to be substantially equal to the high-side input voltage or a high-side input voltage boosted by the voltage of the first capacitor.

The switch path network may also include a switch path for connecting a second capacitor in series between the second input and the second selective boost node, and for connecting the second input directly to the second selective boost node. A switch path to the boost node (ie, not via the first capacitor or the second capacitor). The second selective boost may thus be selectively driven to be substantially equal to the low-side input voltage or a low-side input voltage negatively boosted by the voltage of the second capacitor.

The switch driver may also include an output stage having an output path for selectively connecting the output node of the driver to the first circuit node or the second circuit node of the selective boost stage.

In each of the operating modes, the switch driver is controllable to vary between at least a first state and a second state to provide different switch voltages, wherein the first capacitor is charged in the first state And charging the second capacitor in the second state.

At least some embodiments relate to a switch driver for switching a driver output node between switch voltages, wherein the switch driver includes a first capacitor and a second capacitor, each of the first capacitor and the second capacitor can be selectively Ground is charged to a defined voltage level, which may, for example, be equal to the input voltage. The switch driver is configured such that the first capacitor and the second capacitor are selectively connectable to provide a voltage boost for the switch voltage. In at least some embodiments, a first capacitor can be optionally connected to provide a positive voltage boost, i.e., boost the associated switching voltage to a higher voltage, and a second capacitor can be optionally connected to provide a negative voltage boost. voltage, that is, boosting the associated switching voltage to a lower voltage. Embodiments thus also relate to a switch driver circuit comprising a first capacitor and a second capacitor for positive voltage boosting and negative voltage boosting, respectively.

Embodiments also relate to a driver circuit comprising two switch drivers configured to provide an output drive signal for driving a bridge-tied load.

As mentioned, a switch driver may be adapted to drive the output transducer. In some implementations, the output transducer may be an audio output transducer, such as a loudspeaker or the like. The output transducer may be a tactile output transducer. In a certain implementation, the output transducer may be driven in series with an inductor, ie there may be an inductor in the output path between the output node of the switch driver and the load. In some implementations, the transducer can be a piezoelectric or ceramic transducer.

Embodiments may be implemented as integrated circuits. Embodiments may be implemented in a host device, particularly a portable and/or battery powered host device, such as a mobile computing device (e.g., laptop, notebook, or tablet computer), or a mobile communication device, such as a mobile phone (e.g., smart phone). The device may be a wearable device, such as a smart watch. The host device may be a game console, a remote control device, a home automation controller or home appliance, a toy, a machine such as a robot, an audio player, a video player. It will be appreciated that embodiments may be implemented as part of a system provided in a home appliance or in a vehicle or an interactive display. Host devices incorporating the above-described embodiments are also provided.

The skilled artisan will recognize that some aspects of the above-described apparatus and methods (e.g., aspects of controlling on-off control signals to implement different modes) may be embodied, for example, on a non-volatile carrier medium such as a magnetic disk, CD-ROM or DVD-ROM, Processor control code on a programmed memory such as read only memory (firmware) or on a data carrier such as an optical or electrical signal carrier. For some applications, an embodiment may be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), or FPGA (Field Programmable Gate Array). Thus, the code may comprise conventional program code or microcode, or code for setting up or controlling an ASIC or FPGA, for example. The code may also include code for dynamically configuring a reconfigurable device, such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog ^™ or VHDL (Very High Speed Integrated Circuit Hardware Description Language). A skilled artisan will appreciate that the code may be distributed among multiple coupled components in communication with each other. Where appropriate, the embodiments may also be implemented using code running on a field (re)programmable analog array or similar device to configure the analog hardware.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" does not exclude a plurality, and a single feature or other element may satisfy that recited in a claim. functions of several units. Any reference numerals or signs in the claims shall not be construed as limiting their scope.

Claims (23)

1. A driver circuit comprising a first switch driver for generating a first drive signal, the first switch driver comprising:

a first input node and a second input node for connection to respective high-side and low-side voltages defining an input voltage;

a capacitor node for connection to a first capacitor and a second capacitor;

a driver output node for outputting the first drive signal; and

a switch path network;

Wherein the switch path network is configured such that, in use:

each of the first capacitor and the second capacitor is selectively connectable in series between the first input node and the second input node to charge to the input voltage;

the first input node can be selectively coupled to a first selective boost node through a path including the first capacitor in series or through a path bypassing the first capacitor;

the second input node can be selectively coupled to a second selective boost node through a path including the second capacitor in series or through a path bypassing the second capacitor; and

the driver output node is selectively coupleable to the first selectively boost node or the second selectively boost node;

wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node switches between two switching voltages, and the switching voltages are different in each of the modes.

2. The driver circuit of claim 1, wherein the first switch driver is selectively operable in any two or more of the following modes:

A first mode in which the two switching voltages are the high side voltage and the low side voltage;

a second mode in which the two switch voltages are the high-side voltage and a boosted high-side voltage that is greater than the high-side voltage by an amount substantially equal to the input voltage; and

a third mode in which the two switch voltages are the low side voltage and a boosted low side voltage that is lower than the low side voltage by an amount substantially equal to the input voltage.

3. The driver circuit of claim 2, wherein in the first mode, the first switch driver is operable in two switch states, the two switch states comprising:

a first state of the first mode, wherein the first input node is coupled to the first selectively boost node through the path bypassing the first capacitor, the driver output node is connected to the first selectively boost node, and the first capacitor is connected between the first selectively boost node and the second input node; and

a second state of the first mode, wherein the second input node is coupled to the second selectively boost node through the path bypassing the second capacitor, the driver output node is connected to the second selectively boost node, and the second capacitor is connected between the first selectively boost node and the second input node.

4. The driver circuit of claim 2, wherein in the second mode, the first switch driver is operable in two switch states, the two switch states comprising:

a first state of the second mode, wherein the first input node is coupled to the first selectively boost node through the path including the first capacitor in series, the driver output node is connected to the first selectively boost node, and the second capacitor is connected between the first selectively boost node and the second input node; and

a second state of the second mode, wherein the first input node is coupled to the first selectively boost node through the path bypassing the first capacitor, the driver output node is connected to the first selectively boost node, and the first capacitor is connected between the first selectively boost node and the second input node.

5. The driver circuit of claim 2, wherein in the third mode, the first switch driver is operable in two switch states, the two switch states comprising:

A first state of the third mode, wherein the second input node is coupled to a second selective boost node through the path bypassing the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor is connected between the first selective boost node and the second input node; and

a second state of the third mode, wherein the second input node is coupled to the second selective boost node through the path including the second capacitor in series, the driver output node is connected to the second selective boost node, and the first capacitor is connected between the first selective boost node and the second input node.

6. The driver circuit of claim 1, wherein the capacitor nodes comprise first and second capacitor nodes for connection to opposite sides of the first capacitor and third and fourth capacitor nodes for connection to opposite sides of the second capacitor, and wherein the first capacitor node is connected to the first selective boost node and the fourth capacitor node is connected to the second selective boost node.

7. The driver circuit of claim 6, wherein the second capacitor node and the third capacitor node are connected to each other.

8. The driver circuit of claim 6, wherein the switch path network comprises:

a first input switch path for connecting the first input node to the first selective boost node;

a second input switch path for connecting the first input node to the second capacitor node;

a third input switch path for connecting the second input node to the third capacitor node;

a fourth input switch path for connecting the second input node to the second selectively boost node.

9. The driver circuit of claim 6, wherein each of the first, second, third, and fourth input switch paths includes a respective FET switch.

10. The driver circuit of claim 1, wherein the switch path network comprises a first output switch path for connecting the driver output node to the first selective boost node, and a second output switch path for connecting the driver output node to the second selective boost node.

11. The driver circuit of claim 10, wherein each of the first output path and the second output path comprises a plurality of FET switches in series.

12. The driver circuit of claim 11, further comprising a bias controller for each of the first output switch path and the second output switch path, each bias controller configured to control a bias voltage between two of the plurality of FETs of the associated first output switch path or second output switch path when the associated one of the first output switch path or second output switch path is non-conductive.

13. The driver circuit of claim 12, wherein the bias controller for the first output switch path comprises a transistor for selectively connecting a midpoint node between the first capacitor and the second capacitor to the associated one of the first output switch path or the second output switch path at a point between the two FETs.

14. The driver circuit of claim 1, wherein, in use, the first and second selectively boost nodes comprise output nodes of a first boost stage, and the switch driver circuit comprises at least one additional boost stage,

Wherein each additional boost stage comprises a first additional capacitor and a second additional capacitor, and the switched path network is operable such that the first additional capacitor and the second additional capacitor are selectively connectable in series in or bypassed in a connection between respective first and second voltage inputs to respective first and second selectively boost nodes of the additional boost stages and the additional boost stages; and is also provided with

Wherein each additional boost stage is configured to receive at its first and second inputs the voltages at the first and second selective boost nodes of the previous boost stage; and is also provided with

Wherein the switch path network is configured to selectively connect the output driver node to a selective boost node of a last one of the additional boost stages.

15. The driver circuit of claim 14, wherein each additional boost stage is further configured to receive a midpoint voltage from a previous boost stage at a third input node, the midpoint voltage being a midpoint between the voltages at the first and second selective boost nodes of the previous boost stage, and wherein the additional boost stage is operable to selectively connect the first additional capacitor between the first and third input nodes of that additional boost stage to charge the first capacitor and to selectively connect the second additional capacitor between the third and second input nodes of that additional boost stage to charge the second additional capacitor.

16. The driver circuit of claim 1, further comprising a controller configured to selectively control the first switch driver to controllably vary the operating mode and the duty cycle with which the driver output node switches between associated switching voltages having a certain duty cycle.

17. The driver circuit of claim 1, further comprising a second switch driver for generating a second drive signal, the driver circuit configured to drive a load using the first and second drive signals in a bridged load configuration.

18. The driver circuit of claim 17, wherein the second switch driver has the same structure as the first switch driver and is operable in the same manner as the first switch driver.

19. The driver circuit of claim 1, further comprising a load configured to be driven by the first drive signal.

20. The driver circuit of claim 19, wherein the load is connected to the driver output node of the first switch driver via a series inductor.

21. The driver circuit of claim 19, wherein the load is at least one of: an audio output transducer; a haptic output transducer; piezoelectric transducers and ceramic transducers.

22. A switch driver for generating a drive signal, the switch driver comprising:

a first voltage input node and a second voltage input node, the first voltage input node and the second voltage input node for receiving a first voltage input and a second voltage input;

a capacitor node for connection to a first capacitor and a second capacitor;

a driver output node for outputting the first drive signal; and

a switch path network;

the switch driver is operable in use to:

selectively driving a first selectively boost node to the first voltage input or the first voltage input positively boosted by a voltage of the first capacitor;

selectively driving a second selectively boost node to the second voltage input or the second voltage input negatively boosted by a voltage of the second capacitor; and

Connecting the driver output node to a selected one of the first selective boost node and the second selective boost node;

wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node switches between two switching voltages, and the switching voltages are different in each of the modes.

23. A switch driver for generating a drive signal for driving a load within a defined output voltage range, the switch driver comprising:

a first voltage input node and a second voltage input node for receiving respective high-side and low-side voltage inputs defining an input voltage;

a capacitor node for connection to at least one capacitor;

an output node for outputting the drive signal; and

a switch path network;

wherein the switch driver is operable to generate a driver signal by selectively operating in one of a plurality of different modes, wherein in each of the modes the driver output node switches between two switching voltages with a controlled duty cycle, wherein the switching voltages are different in each mode and the switching voltages in each mode provide only a portion of the defined output voltage range.

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