CN103579498A - Switching device, operating method thereof, and memory array - Google Patents

Abstract

The invention discloses a switching device, an operation method thereof and a memory array. The switching device comprises a first solid electrolyte layer, a second solid electrolyte layer and a switching layer, wherein the switching layer is adjacent to the position between the first solid electrolyte layer and the second solid electrolyte layer. The switching device can control the on-off state of the memory devices in the memory array, thereby avoiding leakage current.

Description

Switching device, operating method thereof, and memory array

technical field

The present invention relates to switching devices and operating methods thereof, and more particularly to memory arrays with switching devices and operating methods thereof.

Background technique

With the advancement of semiconductor technology, the miniaturization capability of electronic components has been continuously improved, enabling electronic products to have more functions while maintaining a fixed size or even a smaller volume. As the amount of information processed is getting higher and higher, the demand for large-capacity and small-volume memory is also increasing.

The current rewritable memory uses a transistor structure to cooperate with memory cells to store information, but with the progress of manufacturing technology, the scalability of this memory architecture has reached a bottleneck. Therefore, advanced memory architectures are constantly being proposed, such as phase change random access memory (phase change random access memory, PCRAM), magnetic random access memory (magnetic random access memory, MRAM), resistive random access memory (resistive random access memory) memory, RRAM). Among them, RRAM has the advantages of fast read and write speed, non-destructive reading, strong tolerance to extreme temperature, and can be integrated with the existing CMOS (complementary metal oxide semiconductor, CMOS) process. Media Potential of Emerging Memory Technologies.

However, current memory arrays still have problems such as leakage current in operation.

Contents of the invention

The invention relates to a switching device, its operation method and memory array. The switching device can be used to control the switching state of the storage devices in the memory array, and can avoid leakage current.

The present invention provides a switching device. The switching device includes a first solid electrolyte layer, a second solid electrolyte layer and a switching layer, and the switching layer is adjacent to the first solid electrolyte layer and the second solid electrolyte layer.

The present invention also provides a memory array, the memory array includes a plurality of storage units; each storage unit includes a switching device and a storage device; the switching device includes a first solid electrolyte layer, a second solid electrolyte layer and a switching layer; the switching layer is adjacent to Between the first solid electrolyte layer and the second solid electrolyte layer; the storage device has multiple contact terminals; one of the first solid electrolyte layer and the second solid electrolyte layer is electrically connected to at least one of the contact terminals of the storage device.

The present invention also provides an operation method of a switching device, the switching device includes a first solid electrolyte layer, a second solid electrolyte layer and a switching layer, and the switching layer is adjacent to between the first solid electrolyte layer and the second solid electrolyte layer; The operation method includes the following steps: applying a first bias voltage to the switching device to change the property of the switching layer from electrical blocking to electrical conducting; applying a second bias voltage different from the first bias voltage to the switching device to Change the properties of the switching layer from electrically conducting to electrically blocking.

The preferred embodiments are specifically cited below, and in conjunction with the attached drawings, the detailed description is as follows:

Description of drawings

FIG. 1 is a cross-sectional view of a switching device according to an embodiment.

FIG. 2A is a cross-sectional view of a switching device according to an embodiment.

FIG. 2B is a cross-sectional view of a switching device according to an embodiment.

FIG. 3A is a cross-sectional view of a switching device according to an embodiment.

FIG. 3B is a cross-sectional view of a switching device according to an embodiment.

FIG. 4 is a schematic diagram of a memory array according to an embodiment.

FIG. 5 is a schematic diagram of a memory array according to an embodiment.

FIG. 6 illustrates a cross-sectional view of a memory structure according to an embodiment.

FIG. 7 illustrates a cross-sectional view of a memory structure according to an embodiment.

[Description of main component symbols]

102, 202～switching device; 104～first solid electrolyte layer; 106～second solid electrolyte layer; 108～switching layer; 110～conductive bridge; 112～storage unit; 114, 214, 314～storage device; 116～the first A contact end; second contact end; 120～current switch; 222, 322～first electrode; 224, 324～second electrode; 226～dielectric layer; 328～first electrode layer; 330～second electrode layer; 332~third electrode layer; 334~fourth electrode layer; 336~fifth electrode layer; 338~protrusion; BL~bit line; WL~word line.

Detailed ways

FIG. 1 shows a cross-sectional view of a switching device 102 according to an embodiment. The switching device 102 includes a first solid electrolyte layer 104 , a second solid electrolyte layer 106 and a switching layer 108 . The switching layer 108 is adjacent to the first solid electrolyte layer 104 and the second solid electrolyte layer 106 and separates the first solid electrolyte layer 104 from the second solid electrolyte layer 106 . The material of the first solid electrolyte layer 104 and the second solid electrolyte layer 106 may respectively include chalcogenides containing metal materials, such as chalcogenides containing copper or silver. In one embodiment, the materials of the first solid electrolyte layer 104 and the second solid electrolyte layer 106 may be tellurium copper (Te—Cu) alloy respectively. However, the present invention is not limited thereto. In other embodiments, the first solid electrolyte layer 104 and the second solid electrolyte layer 106 may respectively include tellurium silver (Te—Ag) alloy, or other suitable materials. The material of the switching layer 108 may include a dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

The switching device 102 can be manufactured by using a self-alignment process without using an additional mask, so the manufacturing cost is low.

Referring to FIG. 1 , when the switching device 102 is not applied with any bias voltage, the switching layer 108 formed of a dielectric material has the property of electrically blocking. In an embodiment, the switching device 102 is used as a current switch.

2A and 2B illustrate the operation method of the switching device 102 according to an embodiment. As shown in FIG. 2A, in one embodiment, a positive switching bias (electric field) (for example, substantially greater than 0V) is applied to the switching device 102, for example, grounding the first solid electrolyte layer 104 of the switching device 102, and applying A positive voltage is applied to the second solid electrolyte layer 106 of the switching device 102, so that the positively charged metal ions in the second solid electrolyte layer 106 move to the switching layer 108 and accumulate in the first solid electrolyte layer 104 and the second solid electrolyte layer 104. An adjacent conductive bridge 110 is formed between the solid electrolyte layers 106, so that the switching layer 108 has the characteristics of electrical conduction, in other words, the current can flow through the conductive bridge 110 in the switching layer 108 in the first solid electrolyte layer 104 and the second solid electrolyte layer 106. In one embodiment, a positive switching bias is used to turn the switching layer 108 into electrical conduction. In an example where the first solid electrolyte layer 104 and the second solid electrolyte layer 106 are Te-Cu alloys, the movable metal ions are copper ions.

As shown in FIG. 2B , in one embodiment, after removing the positive switching bias voltage that turns the switching layer 108 into electrical conduction, for example, no voltage is provided to the first solid electrolyte layer 104 and the second solid electrolyte layer 106 , or after making the electric field between the first solid electrolyte layer 104 and the second solid electrolyte layer 106 zero (for example, substantially equal to 0V), in the conductive bridge 110 close to the first solid electrolyte layer 104 and the second solid electrolyte layer 106 The metal ions will be attracted to move into the first solid electrolyte layer 104 and the second solid electrolyte layer 106, and automatically break in the first solid electrolyte layer 104 and the second solid electrolyte layer 106, so the properties of the switching layer 108 are converted into electrical In other words, current cannot flow between the first solid electrolyte layer 104 and the second solid electrolyte layer 106 .

3A and 3B illustrate the operation method of the switching device 102 according to an embodiment. As shown in FIG. 3A, in one embodiment, a negative switching bias (electric field) (for example, substantially less than 0V) is applied to the switching device 102, such as grounding the first solid electrolyte layer 104 of the switching device 102, and applying A negative voltage is applied to the second solid electrolyte layer 106 of the switching device 102, so that the positively charged metal ions in the first solid electrolyte layer 104 move to the switching layer 108 and accumulate in the first solid electrolyte layer 104 and the second solid electrolyte layer 104. An adjacent conductive bridge 110 is formed between the solid electrolyte layers 106, so that the switching layer 108 has the characteristics of electrical conduction, in other words, the current can flow through the conductive bridge 110 in the switching layer 108 in the first solid electrolyte layer 104 and the second solid electrolyte layer 106. In one embodiment, a negative switching bias is used to turn the switching layer 108 into electrical conduction. In an example where the first solid electrolyte layer 104 and the second solid electrolyte layer 106 are Te-Cu alloys, the movable metal ions are copper ions.

As shown in FIG. 3B , in one embodiment, after removing the negative switching bias voltage that turns the switching layer 108 into electrical conduction, for example, no voltage is provided to the first solid electrolyte layer 104 and the second solid electrolyte layer 106 , or after making the electric field between the first solid electrolyte layer 104 and the second solid electrolyte layer 106 zero (for example, substantially equal to 0V), in the conductive bridge 110 close to the first solid electrolyte layer 104 and the second solid electrolyte layer 106 The metal ions will be attracted to move into the first solid electrolyte layer 104 and the second solid electrolyte layer 106, and automatically break in the first solid electrolyte layer 104 and the second solid electrolyte layer 106, so the properties of the switching layer 108 are converted into electrical In other words, current cannot flow between the first solid electrolyte layer 104 and the second solid electrolyte layer 106 .

The switching device 102 is electrically connected to a storage device (not shown) to control switching of the storage device. For example, the switching device 102 is an electrical series memory device. In one embodiment, the method for operating a semiconductor device includes programming, erasing and reading a memory device. During the process of programming, erasing and reading, the switching device 102 can be used to turn on the selected memory device and turn off the unselected memory device at the same time to avoid leakage current.

In one embodiment, a positive programming bias Vp is provided to the storage device, and the positive programming bias Vp causes a positive switching bias Vs in the switching device 102 electrically connected to the storage device, so that the switching layer 108 has an electrical The nature of sexual conduction, as shown in Figure 2A. Then, the positive programming bias Vp can be removed, so that the switching layer 108 of the switching device 102 has an electrical blocking property, as shown in FIG. 2B , while the memory device is maintained in a programmed state. Then, a positive read bias voltage Vr can be provided to read the programmed state of the memory device, wherein the positive read bias voltage Vr will cause a positive switching bias voltage Vs in the switching device 102 electrically connected to the memory device, so that The switching layer 108 is electrically conductive, as shown in FIG. 2A . In an embodiment, the relationship between the programming bias Vp, the switching bias Vs and the reading bias Vr can be represented by the following formula:

2*Vs＞Vp＞Vr＞Vs

In one embodiment, a negative erasing bias Ve is provided to the storage device, and the negative erasing bias Ve causes a negative switching bias Vs in the switching device 102 electrically connected to the storage device, so that the switching layer 108 It has the property of electrical conduction, as shown in Fig. 3A. Then, the negative erase bias Ve can be removed, so that the switching layer 108 of the switching device 102 has an electrical blocking property, as shown in FIG. 3B , and meanwhile, the storage device is maintained in an erased state. Next, a positive read bias voltage Vr can be provided to read the erased state of the storage device, wherein the positive read bias voltage Vr will cause a positive switching bias voltage Vs in the switching device 102 electrically connected to the storage device, The switching layer 108 has the property of electrical conduction, as shown in FIG. 2A . In an embodiment, the relationship between the erasing bias Ve, the switching bias Vs, and the reading bias Vr can be represented by the following formula:

2*|Vs|＞|Ve|＞Vr＞|Vs|

FIG. 4 is a schematic diagram of a memory array according to an embodiment. The memory array is a cross-point array device. The memory array includes a plurality of memory cells 112 . The storage units 112 each include a switching device 102 and a storage device 114 . The switching device 102 can be electrically connected in series with the storage device 114 . The switching device 102 may be similar to the switching device 102 shown in FIG. 1 . Referring to FIG. 4 , in one embodiment, the storage device 114 has a first contact end 116 and a second contact end 118 opposite to each other. For example, the first contact terminal 116 of the storage device 114 can be electrically connected to the second solid electrolyte layer 106 ( FIG. 1 ) of the switching device 102 , and the second contact terminal 118 of the storage device 114 can be electrically connected to the bit line BL. , the first solid electrolyte layer 104 ( FIG. 1 ) of the switching device 102 can be electrically connected to the word line WL. In an embodiment, the switch device 102 is used to control the switch storage device 114 and can be represented by a current switch 120 as shown in FIG. 5 .

FIG. 6 illustrates a cross-sectional view of a memory structure according to an embodiment. The memory structure includes a switching device 202 and a memory device 214 located between a first electrode 222 and a second electrode 224 . The switching device 202 and the storage device 214 of different layers are separated from each other by a dielectric layer 226 . The switching device 202 may be similar to the switching device 102 shown in FIG. 1 . The first electrode 222 and the second electrode 224 may include metals such as tungsten, titanium nitride and the like. For example, the first electrode 222 is an upper electrode, and the second electrode 224 is a lower electrode. In one embodiment, memory device 214 includes resistive memory, including tungsten oxide (WOx). For example, the memory structure may have a sidewall structure, such as the memory device 214 with a single sidewall.

FIG. 7 illustrates a cross-sectional view of a memory structure according to an embodiment. The difference between the memory structure shown in FIG. 7 and the memory structure shown in FIG. 6 is that the first electrode 322 includes a first electrode layer 328 and a second electrode layer 330 . The second sub-electrode layer 330 is located between the first electrode layer 328 and the switching device 202 . The second electrode 324 includes a third sub-electrode layer 332 , a fourth sub-electrode layer 334 and a fifth sub-electrode layer 336 . The fourth sub-electrode layer 334 is located between the third sub-electrode layer 332 and the fifth sub-electrode layer 336 . Different materials can be used for the first electrode layer 328 and the second electrode layer 330 . In one embodiment, for example, the first electrode layer 328 includes tungsten, and the second electrode layer 330 includes titanium nitride. Different materials can be used for the third sub-electrode layer 332 , the fourth sub-electrode layer 334 and the fifth sub-electrode layer 336 . In one embodiment, for example, the fourth sub-electrode layer 334 includes tungsten, and the third sub-electrode layer 332 and the fifth sub-electrode layer 336 include titanium nitride. The memory device 314 may have a protrusion 338 interposed between the third sub-electrode layer 332 , the fourth sub-electrode layer 334 and the fifth sub-electrode layer 336 .

The switching device in the embodiment can be applied to variable resistance memory (ReRAM), programmable metallization cell (Programmable Metallization Cell; PMC) ReRAM, phase change memory (Phase Change Memory; PCM), magnetic random access memory (MagnetoresistiveRandom) Access Memory; MRAM) such as spin transfer torque magnetic random access memory (Spin Transfer Torque Magnetoresistive Random Access Memory; STT-MRAM). The switching device in the embodiment can be used to implement three dimensional ReRAM. Simple integration with bipolar ReRAM using switching devices. The switching device may be suitable for a cross-point array device.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the appended claims.

Claims (10)

1. A switching device, comprising: a first solid electrolyte layer; a second solid electrolyte layer; and A switching layer is adjacent to the first solid electrolyte layer and the second solid electrolyte layer. 2. The switching device according to claim 1, wherein the materials of the first solid electrolyte layer and the second solid electrolyte layer respectively include chalcogenide (chalcogenide) containing metal materials, and the switching layer includes silicon oxide, nitride silicon or silicon oxynitride. 3. The switching device according to claim 1, wherein the first solid electrolyte layer and the second solid electrolyte layer are separated from each other by the switching layer. 4. A memory array comprising a plurality of memory cells, wherein each of the plurality of memory cells comprises: A switching device as claimed in any one of claims 1 to 3; and A storage device has a plurality of contact terminals, wherein one of the first solid electrolyte layer and the second solid electrolyte layer is electrically connected to at least one of the plurality of contact terminals of the storage device. 5. The memory array according to claim 4, wherein the memory device has a first contact terminal and a second contact terminal opposite, the first contact terminal of the memory device is electrically connected to the switching device the second solid electrolyte layer. 6. The memory array according to claim 4, further comprising a plurality of word lines and bit lines, wherein the first solid electrolyte layer of the switching device is electrically connected to one of the plurality of word lines, the memory device The second contact terminal is electrically connected to one of the plurality of bit lines. 7. The memory array according to claim 4, wherein the memory device comprises variable resistance memory (ReRAM), Programmable Metallization Cell (PMC) ReRAM, Phase Change Memory (PCM), and MRAM 8. The memory array of claim 4, wherein the storage device and the switching device are electrically connected in series. 9. The memory array of claim 4, wherein the switching device is used as a current switch. 10. A method of operating a switching device, comprising: applying a first bias voltage to the switching device according to any one of claims 1 to 3, so that the property of the switching layer changes from electrically blocking to electrically conducting; and A second bias voltage different from the first bias voltage is applied to the switching device, so that the property of the switching layer changes from electrically conducting to electrically blocking.

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