CN103579074A - Semiconductor structure forming method - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate having a first region and a second region; forming a first material layer covering the surface of the semiconductor substrate; A second material layer is formed on the surface of the material layer, and the first material layer and the second material layer in the first region form a stacked structure; a mask layer is formed on the stacked structure and the surface of the first material layer in the second region; Etching the first material layer by an etching process to form a third opening exposing the surface of the semiconductor substrate, and at the same time etching a partial thickness of the stacked structure to form a number of fourth openings; using a second plasma etching process to etch In the semiconductor substrate, a first groove is formed, and the stacked structure and the semiconductor substrate are etched simultaneously to form a plurality of second grooves, and the depth of the second grooves is smaller than that of the first grooves. The first groove and the second groove are formed in the same etching step, and the process is simple.

Description

Formation method of semiconductor structure

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background technique

With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. But when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the multi-gate device has been adopted as a substitute for the conventional device. Widespread concern.

Fin field effect transistor (Fin FET) is a common multi-gate device. Figures 1 to 4 are schematic cross-sectional structure diagrams of the formation process of the existing fin field effect transistor.

Referring to FIG. 1 , a semiconductor substrate 100 is provided, and the semiconductor substrate 100 includes a first region I and a second region II; a first hard mask layer 101 is formed on the semiconductor substrate 100, and the second region II of the second region A hard mask layer 101 has a first opening 102 , and a portion of the semiconductor substrate 100 is etched along the first opening 102 to form a first groove 103 .

Referring to FIG. 2 , a first isolation material layer (not shown) is formed on the surface of the first hard mask layer 101 (refer to FIG. 1 ), and the first isolation material layer fills the first opening 102 and the first recess. Groove 103 (refer to FIG. 1 ); chemical mechanical polishing of the first isolation material layer and the first hard mask layer 101, using the surface of the semiconductor substrate 100 as a stop layer, forming a first isolation structure 104 in the first groove 103 , the first isolation structure 104 is used to isolate adjacent active regions.

Referring to FIG. 3, a second hard mask layer 105 is formed on the semiconductor substrate 100. The hard mask layer 105 in the first region I has a plurality of second openings 106, and the semiconductor is etched along the second openings 106. The substrate 100 forms several fins 108, and there are second grooves 107 between adjacent fins 108 and between the fins and the semiconductor substrate 100, and the positions of the second grooves 107 correspond to the positions of the second openings 106. , the depth of the second groove 107 is smaller than the depth of the first groove 103 (refer to FIG. 1 ), and the second isolation material layer is filled in the second groove 107 to form a second isolation structure, which is used between adjacent fins. electrical isolation.

Referring to FIG. 4 , a second isolation material layer (not shown in the figure) is formed on the second hard mask layer 105 (refer to FIG. 3 ), and the second isolation material layer fills the second opening 106 and The second groove 107 (refer to FIG. 3 ); the second isolation material layer and the second hard mask layer 105 are chemically mechanically polished to form a second isolation structure 109 in the second groove 107, the second isolation structure 109 is used to electrically isolate adjacent fins 108 .

When forming the first isolation structure 104 and the second isolation structure 109 in the existing process, the first isolation structure 104 and the second isolation structure 109 and the corresponding first groove 103 and the second groove 107 are all processed in different process steps. Formation, the process is relatively complicated.

For more information about FinFETs, please refer to US Patent Publication No. US2011/0068431A1.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor structure with a simple process.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

A semiconductor substrate is provided, the semiconductor substrate has a first region and a second region adjacent to the first region; forming a first material layer covering the surface of the semiconductor substrate; forming on the surface of the first material layer in the first region The second material layer, the first material layer and the second material layer in the first region constitute a stacked structure; a mask layer is formed on the surface of the stacked structure and the first material layer in the second region, and the mask layer in the first region has several exposures. The first opening on the surface of the stack structure, the mask layer in the second region has a second opening exposing the surface of the first material layer; the first material layer is etched along the second opening by using the first plasma etching process to form an exposed The third opening on the surface of the semiconductor substrate is simultaneously etched along a plurality of first openings to form a partial thickness of the stack structure to form a plurality of fourth openings; the second plasma etching process is used to etch the semiconductor along the third opening. substrate, forming first grooves in the semiconductor substrate, and simultaneously etching the stacked structure and the semiconductor substrate along several fourth openings, forming several second grooves in the semiconductor substrate, between adjacent second grooves There are fins in between, and the depth of the second groove is smaller than that of the first groove.

Optionally, the materials of the first material layer and the second material layer are different, and the etching selectivity ratio of the first material layer relative to the second material layer is greater than 1:1 and less than or equal to 5:1.

Optionally, the etching selectivity ratio of the semiconductor substrate relative to the first material layer and the second material layer is 2:1˜15:1.

Optionally, the material of the first material layer is silicon dioxide, and the material of the second material layer is silicon nitride.

Optionally, the thickness of the first material layer is 20-100 nanometers, and the thickness of the second material layer is 20-100 nanometers.

Optionally, the gases used in the first plasma etching process are _CHF3 and Ar, the etching chamber pressure is 5-20 mTorr, the radio frequency power is 200-400 watts, the bias power is 20-40 watts, and the engraving The corrosion temperature is 5-30 degrees Celsius.

Optionally, the gases used in the second plasma etching process are _CCl4 and Ar, the etching chamber pressure is 5-20 mtorr, the radio frequency power is 500-700 watts, and the bias power is 20-40 watts, The etching temperature is 5-30 degrees Celsius.

Optionally, the depth of the first groove is 100-500 nanometers.

Optionally, the second groove has a depth of 50-300 nanometers.

Optionally, the width of the fins is 10-50 nanometers, and the distance between adjacent fins is 10-60 nanometers.

Optionally, the method further includes: rounding the opening of the first groove.

Optionally, the arcing treatment adopts isotropic microwave dry etching power.

Optionally, the frequency of the microwave dry etching process is 2.3-2.5 GHz, the power is 900-1100 watts, and the etching gas is CF ₄ , O ₂ and N ₂ .

Optionally, the method further includes: filling the first groove and the second groove with an isolation material to form a first isolation structure and a second isolation structure.

Optionally, the material of the mask layer is photoresist.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Using the first material layer and the second material layer, the semiconductor substrate in the first region has a stacked structure of the first material layer and the second material layer, the second region has a single-layer structure of the first material layer, and the first plasma etching When the etching process etches the first material layer in the second region to form a third opening exposing the surface of the semiconductor substrate, at the same time, the stacked structure in the first region will only be etched to remove part of the thickness, using the second plasma The etching process etches the semiconductor substrate in the first region along the third opening, forming a first groove in the semiconductor substrate, and simultaneously etching the remaining stacked structure and the semiconductor substrate in the first region, in the semiconductor substrate Several second grooves are formed. During the second plasma etching process, due to the obstruction of the remaining stack structure, the depth of the second grooves is smaller than the depth of the first grooves. The first grooves and the second grooves are formed at the same moment. It is formed simultaneously in the etching process. Compared with the existing multiple hard mask, etching and photolithography processes, the process is simple.

Further, when the materials of the first material layer and the second material layer are different, the etching selectivity ratio of the first material layer relative to the second material layer is greater than 1:1 and less than or equal to 5:1. During plasma etching, more accurately control the remaining thickness of the stacked structure of the first material layer and the second material layer in the first region I, so that during the second plasma etching process, more accurately control the thickness of the first region I The difference between the depth of the second groove formed in the semiconductor substrate and the depth of the first groove formed in the semiconductor substrate of the second region II.

Furthermore, the opening of the first groove is rounded to form an arc opening. When the fin field effect transistor is working, the accumulated charges will be evenly distributed along the arc of the arc opening, and the semiconductor substrate at the arc opening will The density of charges accumulated in the bottom is small, thereby avoiding the generation of leakage current.

Description of drawings

1 to 4 are schematic cross-sectional structural diagrams of the formation process of an existing fin field effect transistor;

5 is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

6 to 11 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure of the present invention.

Detailed ways

In order to achieve a better isolation effect between adjacent active regions, the first The depth of the first groove corresponding to the isolation structure is greater than the depth of the second groove corresponding to the second isolation structure. Since the depth of the first groove is different from the depth of the second groove, two hard mask processes are required. 1. The photolithography process corresponding to the patterning of the hard mask and the two deposition processes, the process steps are relatively complicated, which increases the production cost.

In order to solve the above problems, the inventor proposes a method for forming a semiconductor structure, using a first material layer and a second material layer, the semiconductor substrate in the first region is a stacked structure of the first material layer and the second material layer, the second The second region is a single-layer structure of the first material layer, and the first plasma etching process etches the first material layer in the second region to form a third opening exposing the surface of the semiconductor substrate, while the first region The stacked structure will only be etched to remove part of the thickness, and the second plasma etching process is used to etch the semiconductor substrate in the first region along the third opening to form a first groove in the semiconductor substrate, and at the same time etch the second The remaining stacked structure and the semiconductor substrate in a region form several second grooves in the semiconductor substrate. During the second plasma etching process, due to the blocking of the remaining stacked structure, the depth of the second grooves is smaller than that of the first grooves. The depth of the groove, the first groove and the second groove are simultaneously formed in the same etching process. Compared with the existing multiple hard mask, etching and photolithography processes, the process is simple.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 5, FIG. 5 is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention, including:

Step S201, providing a semiconductor substrate, the semiconductor substrate has a first region and a second region adjacent to the first region;

Step S202, forming a first material layer covering the surface of the semiconductor substrate; forming a second material layer on the surface of the first material layer in the first region, where the first material layer and the second material layer in the first region form a stacked structure;

Step S203, forming a mask layer on the stack structure and the surface of the first material layer in the second region, the mask layer in the first region has several first openings exposing the surface of the stack structure, and the mask layer in the second region has a number of first openings exposing the first a second opening in the surface of the material layer;

Step S204, using the first plasma etching process to etch the first material layer along the second opening to form a third opening exposing the surface of the semiconductor substrate, and at the same time, etching a part of the thickness of the first opening along several first openings. stacking structures to form a plurality of fourth openings;

Step S205, using a second plasma etching process to etch the semiconductor substrate along the third opening, forming a first groove in the semiconductor substrate, and simultaneously etching the stack structure and the semiconductor substrate along several fourth openings , forming a plurality of second grooves in the semiconductor substrate, fins are formed between adjacent second grooves, and the depth of the second grooves is smaller than the depth of the first grooves;

Step S206, performing arc processing on the opening of the first groove;

Step S207, filling the first groove and the second groove with an isolation material to form a first isolation structure and a second isolation structure.

6 to 11 are schematic cross-sectional structure diagrams of the formation process of the semiconductor structure of the present invention.

Referring to FIG. 6, a semiconductor substrate 300 is provided, the semiconductor substrate 300 has a first region I and a second region II adjacent to the first region I; a first material layer 301 covering the surface of the semiconductor substrate 300 is formed; A second material layer 302 is formed on the surface of the first material layer 301 in the first region I, and the first material layer 301 and the second material layer 302 in the first region I form a stacked structure.

The material of the semiconductor substrate 300 can be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide.

The material of the semiconductor substrate 300 in this embodiment is single crystal silicon, the semiconductor substrate 300 in the first region I is used to form a fin field effect transistor, and the semiconductor substrate 300 in the second region II is used to form the first isolation structure, the first isolation structure is used for isolating adjacent active regions and preventing the fin field effect transistors formed in the adjacent active regions from being electrically connected.

The first material layer 301 and the second material layer 302 are used to control the depth of the first groove and the second groove formed in the semiconductor substrate 300 during subsequent etching, so that the first groove and the second groove The depth of the groove is not the same, because the depth of the first groove and the second groove of the subsequent etching is relatively deep, when the photoresist layer used as the mask layer is consumed, the first material layer 301 and the second material layer 302 are still It can be used as a mask when etching continues.

The materials of the first material layer 301 and the second material layer 302 are different, and the etching selectivity ratio of the first material layer relative to the second material layer is greater than 1:1 and less than or equal to 5:1. During plasma etching, the remaining thickness of the stacked structure of the first material layer 301 and the second material layer 302 in the first region I is more accurately controlled, so that during the second plasma etching process, the first region I is more accurately controlled The difference between the depth of the second groove formed in the semiconductor substrate of the second region II and the depth of the first groove formed in the semiconductor substrate of the second region II.

The etching selectivity ratio of the semiconductor substrate relative to the first material layer and the second material layer is 2:1 to 15:1, so when the second plasma etching process starts to etch the semiconductor substrate 300 in the first region I , the groove formed by etching in the second region II already has a certain depth, and this depth is greater than the remaining thickness of the stack structure, so that the depth of the second groove formed in the semiconductor substrate in the first region I is finally less than The depth of the first groove formed in the semiconductor substrate in the second region II.

In this embodiment, the material of the first material layer 301 is silicon oxide, the material of the second material layer 302 is silicon nitride, the thickness of the first material layer 301 is 20~100 nanometers, and the thickness of the second material layer is 20~100 nanometers. 100 nanometers, during the first plasma etching, the stacked structure of the first material layer 301 and the second material layer 302 in the first region I remains with sufficient thickness, so that during the second plasma etching, the first region The depth of the second groove formed in the semiconductor substrate of I is less than the depth of the first groove formed in the semiconductor substrate of the second region II, and the difference between the depth of the first groove and the depth of the second groove is greater than or equal to 50 nm.

The formation process of the first material layer 301 is a thermal oxidation process or a chemical vapor deposition process, and the formation process of the second material layer 302 is a chemical vapor deposition process.

Referring to Fig. 7, a mask layer 303 is formed on the surface of the first material layer 301 in the stacked structure and the second region II, the mask layer 303 in the first region I has a plurality of first openings 304 exposing the surface of the stacked structure, and the second region II The mask layer 303 has a second opening 305 exposing the surface of the first material layer 301 . The position of the first opening 304 corresponds to the position of the second groove subsequently formed in the semiconductor substrate 300 in the first region I, and the second opening 305 corresponds to the position of the first recess formed subsequently in the semiconductor substrate 300 in the second region II. corresponding to the position of the groove.

The material of the mask layer 303 is a photoresist layer, and the first opening 304 and the second opening 305 are formed in the mask layer 303 through exposure and development processes.

Referring to FIG. 8, the first material layer 301 is etched along the second opening 305 by using a first plasma etching process to form a third opening 306 exposing the surface 300 of the semiconductor substrate, and simultaneously along several first openings 304, A partial thickness of the stack structure is etched to form a plurality of fourth openings 307 .

The gas used in the first plasma etching process is CHF ₃ and Ar, the etching chamber pressure is 5-20 millitorr, the radio frequency power is 200-400 watts, the bias power is 20-40 watts, and the etching temperature is 5 ~30 degrees Celsius, by adjusting the etching temperature, the first material layer 301 has different etching selectivity relative to the second material layer 302, and the etching selectivity ratio of the first material layer 301 relative to the second material layer 302 Greater than 1:1 and less than or equal to 5:1, when forming the third opening 306, the depth of the fourth opening 307 can be accurately controlled, so that the depth of the fourth opening 307 can be less than the thickness of the second material layer 302, or can be equal to The thickness of the second material layer 302 can also be greater than the thickness of the second material layer 302, that is, the thickness of the remaining stacked structure at the bottom of the fourth opening 307 can be accurately controlled, and the thickness of the remaining stacked structure at the bottom of the fourth opening 307 is related to the subsequent formation. The depth difference between the first groove and the second groove is directly related, the thicker the thickness of the remaining stacked structure is, the larger the depth difference between the first groove and the second groove is, the thinner the thickness of the remaining stacked structure is, and the thickness of the remaining stacked structure is thinner. The smaller the depth difference between the first groove and the second groove, the smaller the depth difference between the first groove and the second groove can be accurately controlled, so as to improve the performance of the formed semiconductor structure. In this embodiment, the depth of the fourth opening 307 is equal to the thickness of the second material layer.

Referring to FIG. 9 , the semiconductor substrate 300 is etched along the third opening 306 by a second plasma etching process, a first groove 308 is formed in the semiconductor substrate, and the stack is etched along several fourth openings 307 at the same time. structure and a semiconductor substrate 300 , several second grooves 309 are formed in the semiconductor substrate 300 , fins are formed between adjacent second grooves 309 , and the depth of the second grooves 309 is smaller than that of the first grooves 308 .

Since the bottom of the fourth opening 307 also has a partial-thickness stack structure, when the semiconductor substrate 300 in the second region II is etched by the second plasma etching process, the remaining partial-thickness stack structure in the first region I will be etched simultaneously. , after etching the remaining part of the stack structure and exposing the semiconductor substrate 300 in the first region I, a groove with a certain depth has been formed in the semiconductor substrate 300 in the second region II, and then continue to etch the first region I and the semiconductor substrate 300 in the second region II, until the second groove 309 is formed in the semiconductor substrate 300 in the first region I, the first groove 308 is formed in the semiconductor substrate 300 in the second region II, and the second groove 308 is formed in the semiconductor substrate 300 in the second region II. The depth of the groove 309 is smaller than the depth of the first groove 308 . Subsequently, an isolation material is filled in the first groove 308 to form a first isolation structure, and the first isolation structure is used to isolate adjacent active regions, and an isolation material is filled in the second groove 309 to form a second isolation structure, and the second isolation The structure is used for the isolation between adjacent fins and the isolation between the gate of the fin field effect transistor and the semiconductor substrate 300. The depth of the first isolation structure is greater than the depth of the second isolation structure, so as to better isolate the phase adjacent active area.

The gases used in the second plasma etching process are _CCl4 and Ar, the etching chamber pressure is 5-20 millitorr, the radio frequency power is 500-700 watts, the bias power is 20-40 watts, and the etching temperature is 5~30 degrees Celsius, by adjusting the etching temperature, the etching selectivity ratio of the semiconductor substrate relative to the first material and the second material can be 2:1~15:1, and the remaining thickness of the stacked structure at the bottom of the fourth opening 307 Under certain circumstances, the depth difference between the first groove 308 and the second groove 309 can be adjusted, and the thickness of the remaining stacked structure at the bottom of the fourth opening 307 can be adjusted, so as to accurately control the first groove 308 and the second groove 308. The depth of the groove 309 is different.

The depth of the first groove 309 is 100-500 nanometers, the depth of the second groove 308 is 50-300 nanometers, the width of the fin between the adjacent second grooves 308 is 10-50 nanometers, adjacent The distance between the fins is 10-60 nm.

Referring to Fig. 10, a photoresist layer 310 is formed on the surface 302 of the second material layer in the first region I, and the photoresist layer 310 fills the first opening, the fourth opening, and the second groove; for the second region The opening of the first groove 308 (please refer to FIG. 9 ) in the semiconductor substrate 300 of II is rounded to form a first groove 314 with an arc opening 311 .

When the opening of the first groove 308 is a right-angle opening, when the fin field effect transistor is working, the charge will accumulate in the semiconductor substrate at the right angle, and the charge density is relatively high. When the first isolation structure is subsequently formed, the first concave The charges accumulated at both ends of the opening of the groove 308 are likely to form a leakage current between adjacent active regions through the surface of the first isolation structure, so that the effect of the electrical isolation of the first isolation structure is weakened, and the opening of the first groove 308 Carry out arc treatment to form arc opening 311. When the fin field effect transistor is working, the accumulated charge will be evenly distributed along the arc of the arc opening 311. The density of the charge accumulated in the semiconductor substrate at the arc opening 311 is Smaller, so as to avoid the generation of leakage current.

The process used in the arcing treatment is isotropic microwave dry etching power, the frequency of the microwave dry etching process is 2.3-2.5 GHz, the power is 900-1100 watts, and the etching gas is CF ₄ , O ₂ and N ₂ , to better control the radian of the opening, so that the charge accumulated at the opening is more uniform.

Referring to FIG. 11 , removing the photoresist layer 310 (please refer to FIG. 10 ); forming an isolation material layer covering the surface of the second material layer 302 (please refer to FIG. 10 ) and the first material layer 301 (please refer to FIG. 10 ), The isolation material fills the first groove and the second groove; chemical mechanical grinding the isolation material layer, the second material layer 302 and the first material layer 301, with the semiconductor substrate surface 300 as a stop layer, in the first region I A second isolation structure 312 is formed in the semiconductor substrate 300 in the second region, and a first isolation structure 313 is formed in the semiconductor substrate 300 in the second region.

The depth of the second isolation structure 312 is smaller than the depth of the first isolation structure 313, and the second isolation structure 313 is used for the isolation between the fins and the electrical connection between the gate of the subsequently formed FinFET and the semiconductor substrate 300. Electrical isolation, the first isolation structure 313 is used for electrical isolation between the active regions.

After forming the first isolation structure 313 and the second isolation structure 312, it also includes: etching back the second isolation structure 312 with a partial thickness to expose the fins with a partial height; forming a gate across the several fins The gate structure includes a gate oxide layer on the surface and side walls of the fin and a gate electrode on the surface of the gate oxide layer; source/drain regions of the fin field effect transistor are formed at both ends of the fin.

To sum up, the method for forming a semiconductor structure provided by the embodiment of the present invention utilizes the first material layer and the second material layer, and the semiconductor substrate in the first region has a stacked structure of the first material layer and the second material layer, and the second material layer The region is a single-layer structure of the first material layer, and the first plasma etching process etches the first material layer of the second region to form a third opening exposing the surface of the semiconductor substrate, while the stack of the first region The structure will only be etched to remove part of the thickness, and the second plasma etching process is used to etch the semiconductor substrate in the first region along the third opening to form a first groove in the semiconductor substrate, and at the same time etch the first The rest of the stacked structure and the semiconductor substrate in the region form several second grooves in the semiconductor substrate. During the second plasma etching process, due to the blocking of the remaining stacked structure, the depth of the second grooves is smaller than that of the first grooves. The depth of the first groove and the second groove are simultaneously formed in the same etching process. Compared with the existing multiple hard mask, etching and photolithography processes, the process is simple.

Further, when the materials of the first material layer and the second material layer are different, the etching selectivity ratio of the first material layer relative to the second material layer is greater than 1:1 and less than or equal to 5:1. During plasma etching, the remaining thickness of the stacked structure of the first material layer and the second material layer in the first region I is more accurately controlled, so that during the second plasma etching process, the semiconductor in the first region is more accurately controlled The difference between the depth of the second groove formed in the substrate and the depth of the first groove formed in the semiconductor substrate in the second region.

Furthermore, the opening of the first groove is rounded to form an arc opening. When the fin field effect transistor is working, the accumulated charges will be evenly distributed along the arc of the arc opening, and the semiconductor substrate at the arc opening will The density of charges accumulated in the bottom is small, thereby avoiding the generation of leakage current.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (16)

1. A method for forming a semiconductor structure, comprising: providing a semiconductor substrate having a first region and a second region adjacent to the first region; forming a first material layer covering the surface of the semiconductor substrate; forming a second material layer on the surface of the first material layer in the first region, the first material layer and the second material layer in the first region form a stacked structure; A mask layer is formed on the stack structure and the surface of the first material layer in the second region, the mask layer in the first region has a plurality of first openings exposing the surface of the stack structure, and the mask layer in the second region has a surface exposed to the first material layer the second opening of Etching the first material layer along the second opening by using a first plasma etching process to form a third opening exposing the surface of the semiconductor substrate, and etching the stacked structure partially thick along the first openings, forming a plurality of fourth openings; Etching the semiconductor substrate along the third opening by using a second plasma etching process to form a first groove in the semiconductor substrate, and simultaneously etching the stacked structure and the semiconductor substrate along a plurality of fourth openings, forming the semiconductor substrate in the semiconductor substrate Several second grooves are formed in the substrate, fins are formed between adjacent second grooves, and the depth of the second grooves is smaller than that of the first grooves. 2. The method for forming a semiconductor structure according to claim 1, wherein the materials of the first material layer and the second material layer are different, and the etching selectivity ratio of the first material layer relative to the second material layer Greater than 1:1 and less than or equal to 5:1. 3. The method for forming a semiconductor structure according to claim 2, wherein the etching selectivity ratio of the semiconductor substrate relative to the first material layer and the second material layer is 2:1˜15:1. 4. The method for forming a semiconductor structure according to claim 2, wherein the material of the first material layer is silicon dioxide, and the material of the second material layer is silicon nitride. 5. The method for forming a semiconductor structure according to claim 4, wherein the thickness of the first material layer is 20-100 nanometers, and the thickness of the second material layer is 20-100 nanometers. 6. The method for forming a semiconductor structure as claimed in claim 3 or 4, wherein the gas used in the first plasma etching process is CHF ₃ and Ar, the etching chamber pressure is 5-20 mTorr, radio frequency The power is 200-400 watts, the bias power is 20-40 watts, and the etching temperature is 5-30 degrees Celsius. 7. The method for forming a semiconductor structure as claimed in claim 3 or 4, wherein the gases used in the second plasma etching process are _CCl4 and Ar, and the etching chamber pressure is 5 to 20 millitorr, The RF power is 500-700 watts, the bias power is 20-40 watts, and the etching temperature is 5-30 degrees Celsius. 8. The method for forming a semiconductor structure according to claim 1, wherein the depth of the first groove is 100-500 nanometers. 9. The method for forming a semiconductor structure according to claim 1, wherein the depth of the second groove is 50-300 nanometers. 10. The method for forming a semiconductor structure according to claim 8 or 9, wherein the difference between the depth of the first groove and the depth of the second groove is greater than or equal to 50 nanometers. 11. The method for forming a semiconductor structure according to claim 1, wherein the width of the fins is 10-50 nanometers, and the distance between adjacent fins is 10-60 nanometers. 12 . The method for forming a semiconductor structure according to claim 1 , further comprising: rounding the opening of the first groove. 13 . The method for forming a semiconductor structure according to claim 12 , characterized in that, the circularization process adopts isotropic microwave dry etching power. 14 . 14. The method for forming a semiconductor structure according to claim 13, wherein the frequency of the microwave dry etching process is 2.3-2.5 GHz, the power is 900-1100 watts, and the etching gas is CF ₄ , _O2 and _N2 . 15. The method for forming a semiconductor structure according to claim 1, further comprising: filling the first groove and the second groove with an isolation material to form the first isolation structure and the second isolation structure. 16. The method for forming a semiconductor structure according to claim 1, wherein the material of the mask layer is photoresist.

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