CN103578958A - Semiconductor grid structure and forming method thereof - Google Patents

Abstract

The invention provides a semiconductor grid structure and a forming method thereof. The method comprises the following steps that a Ge layer is provided to serve as a surface substrate; a Sn layer is formed on the Ge layer, and an interface between the Ge layer and the Sn layer is a GeSn layer; the Sn layer is removed to expose the GeSn layer; sulfidizing is carried out on the GeSn layer to form a GeSnSx passivation layer; a grid stacking structure is formed on the GeSnSx passivation layer. According to the semiconductor grid structure and the forming method, electrical properties of the Ge-based grid stacking structure can be improved, for example, the interface trap density and grid leakage current density are low, and the semiconductor grid structure has the advantages of being easy and convenient to use and low in cost.

Description

Semiconductor gate structure and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor gate structure and a forming method thereof.

Background technique

The semiconductor Ge has high electron and hole mobility and is expected to realize higher-performance transistors at extremely small sizes, which has attracted a lot of attention as a channel material for advanced devices. However, the choice of gate dielectric must be faced when Ge is applied in metal-oxide-semiconductor field-effect transistors (MOSFETs). Ge oxides are thermally unstable, soluble in water, and have poor electrical properties, which are different from the ideal Si/SiO ₂ interface characteristics in traditional Si-based devices. Therefore, for Ge-based MOSFET devices, high-k dielectrics should be used to overcome this difficulty, and at the same time realize the reduction of the equivalent oxide layer thickness.

However, direct deposition of high-k dielectrics on Ge surfaces cleaned with dilute HF usually exhibit high interfacial charge trap density and poor leakage current characteristics, which are mainly caused by the poor relationship between high-k dielectrics and Ge Due to the interface characteristics, Ge and the high-k dielectric sometimes interact to make the interface characteristics worse. Therefore, the interface passivation between the high-k dielectric and the Ge substrate has always been the key to the realization of advanced Ge MOS devices.

Many methods have been proposed to solve this problem, such as adding GeO ₂ , GeO _x N _y , AlN and other interfacial layers between Ge and high-k dielectrics to achieve passivation of the Ge surface and isolation from high-k dielectrics, but these In the method, the improvement of the interface charge trap density and leakage current characteristics is still not ideal, or when the interface passivation effect is realized, the thickness of the interface layer is often large, and the dielectric constant is generally not high, thus affecting the thickness of the equivalent oxide layer. The reduction is not suitable for device applications in extremely small sizes.

Contents of the invention

The present invention aims to solve one of the above technical problems at least to a certain extent or at least provide a useful technical option.

Therefore, an object of the present invention is to provide a method for forming a semiconductor gate structure with a _GeSnSx passivation layer and good electrical properties.

Another object of the present invention is to provide a semiconductor gate structure with _GeSnSx passivation layer and good electrical properties.

The method for forming a semiconductor gate structure according to an embodiment of the present invention includes the following steps: providing a substrate with a Ge layer as a surface; forming a Sn layer on the Ge layer, wherein the gap between the Ge layer and the Sn layer is The interface of the GeSn layer is a GeSn layer; the Sn layer is removed to expose the GeSn layer; the GeSn layer is sulfurized to form a _GeSnSx passivation layer; and a gate stack structure is formed on the _GeSnSx passivation layer.

The method for forming the semiconductor gate structure according to the embodiment of the present invention can improve the electrical performance of the gate stack structure on the Ge base, such as low interface trap density and extremely low gate leakage current density, and has the advantages of simplicity and low cost.

In addition, the method for forming a semiconductor gate structure according to an embodiment of the present invention may also have the following additional technical features:

In one embodiment of the present invention, before removing the Sn layer, it further includes: strengthening the GeSn layer by annealing.

In one embodiment of the present invention, the sulfidation treatment is: annealing sulfidation in sulfur vapor, so that part or all of the GeSn layer becomes a _GeSnSx passivation layer.

In one embodiment of the present invention, the annealing and vulcanization temperature is 100-400°C.

In one embodiment of the present invention, the sulfidation treatment is: soaking in a solution containing sulfide ions for wet chemical sulfidation, so that part or all of the GeSn layer becomes a _GeSnSx passivation layer.

In one embodiment of the present invention, the solution containing sulfide ions contains one or more of ammonium sulfide, hydrogen sulfide, and sodium sulfide in combination.

In one embodiment of the present invention, the Sn layer is removed by cleaning with a solution having a high etch selectivity to GeSn and Sn to expose the GeSn layer.

In one embodiment of the present invention, the thickness of the GeSn layer remaining after the cleaning is 0.5-40 nm.

In one embodiment of the present invention, the substrate with the Ge layer as the surface includes: a pure Ge substrate or a substrate with a Ge thin film on the surface.

The semiconductor gate structure according to an embodiment of the present invention may include: a substrate having a Ge layer as a surface; a GeSn layer located on the Ge layer; a _GeSnSx passivation layer located on the GeSn layer; and a GeSn layer located on the GeSn layer; The gate stack structure above the GeSnS _x passivation layer.

The semiconductor gate structure according to the embodiment of the present invention can improve the electrical performance of the Ge-based gate stack structure, such as low interface trap density and extremely low gate leakage current density, and has the advantages of simple structure and low cost.

In addition, the semiconductor gate structure according to the embodiment of the present invention may also have the following additional technical features:

In one embodiment of the present invention, the GeSn layer is obtained by first forming a Sn layer on the Ge layer, and then forming naturally at the interface between the Ge layer and the Sn layer or strengthened by annealing .

In one embodiment of the present invention, the GeSnS _x passivation layer is obtained by annealing and sulfiding part or all of the GeSn layer in sulfur vapor.

In one embodiment of the present invention, the annealing and vulcanization temperature is 100-400°C.

In one embodiment of the present invention, the GeSnS _x passivation layer is obtained by soaking part or all of the GeSn layer in a solution containing sulfide ions and performing wet chemical vulcanization.

In one embodiment of the present invention, the solution containing sulfide ions contains one or more of ammonium sulfide, hydrogen sulfide, and sodium sulfide in combination.

In one embodiment of the present invention, the thickness of the GeSn layer is 0.5-40 nm.

In one embodiment of the present invention, the substrate with the Ge layer as the surface includes: a pure Ge substrate or a substrate with a Ge thin film on the surface.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

1 is a flowchart of a method for forming a semiconductor gate structure according to an embodiment of the present invention;

2 is a schematic structural diagram of a semiconductor gate structure according to an embodiment of the present invention;

Fig. 3 is the Cg-Vg curve of the MOS electric capacity of Ge/GeSnS _x /HfO ₂ /Al structure; With

Fig. 4 is a Jg-Vg characteristic curve of the MOS structure of Ge/GeSnS _x /HfO ₂ /Al structure.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

As shown in FIG. 1, the method for forming a semiconductor gate structure according to an embodiment of the present invention includes the following steps:

S1. Provide a substrate having a Ge layer as a surface.

Specifically, the provided substrate with the Ge layer as the surface can be a pure Ge substrate or a substrate with a Ge thin film on the surface, for example, a substrate with a Ge thin film surface on a Si substrate.

S2. Forming a Sn layer on the Ge layer, wherein the interface between the Ge layer and the Sn layer is a GeSn layer.

Generally, the Sn layer can be formed on the Ge layer by magnetron sputtering, electron beam evaporation and other processes. In these processes, the substrate temperature can be controlled between room temperature and 200°C. During the process, a GeSn layer is naturally formed at the Ge/Sn interface due to the diffusion of atoms between the two material interfaces. In a preferred embodiment of the present invention, the GeSn layer can also be strengthened by annealing. The temperature range of the annealing is 50-200° C., the higher the temperature, the thicker the GeSn layer formed.

The GeSn layer formed by diffusion is a solid solution, has the same crystal structure as Ge, and has good semiconductor properties, such as GeSn has higher hole mobility than Ge. Therefore, forming a GeSn layer on the Ge surface usually does not deteriorate the performance of Ge devices.

S3. Removing the Sn layer to expose the GeSn layer.

Specifically, the Sn layer is removed by cleaning with a solution having a high etch selectivity to GeSn and Sn to expose the GeSn layer. Common cleaning solutions include dilute hydrochloric acid, dilute sulfuric acid, ammonia or sodium hydroxide solutions. The GeSn layer remaining after cleaning has a thickness of 0.5-40 nm, preferably, the GeSn layer has a thickness of 0.5-10 nm.

S4. Sulfide the GeSn layer to form a _GeSnSx passivation layer.

Specifically, the sulfidation treatment may be annealing sulfidation in sulfur vapor, so that part or all of the GeSn layer becomes a _GeSnSx passivation layer. Because the GeSn layer has good semiconductor properties, even if there is an unsulfurized GeSn layer between the Ge layer and the GeSnS _x passivation layer, it usually not only does not deteriorate the performance of the Ge device, but may also improve the device performance.

Specifically, the annealing and vulcanization temperature is 100-400°C, and the optimum temperature range is 200-300°C.

The sulfidation treatment can also be wet chemical sulfidation by immersion in a solution containing sulfide ions, so that the GeSn layer becomes a _GeSnSx passivation layer. The solution containing sulfide ions may be an aqueous solution of one or more combinations of ammonium sulfide, hydrogen sulfide, and sodium sulfide. For example, 0.1-20wt.% ammonium sulfide aqueous solution can be selected, and the reaction temperature can be selected at 20-80°C.

S5. Forming a gate stack structure on the _GeSnSx passivation layer.

Specifically, the dielectric layer may be formed first and then the gate electrode layer may be formed to form a gate stack structure. In one embodiment of the present invention, the dielectric layer is made of high-k material HfO ₂ , Al ₂ O ₃ or ZrO ₂ , and the gate electrode layer is made of TiN or TaN. It should be noted that, in addition to the above examples, the selection and matching of the materials of the dielectric layer and the gate electrode layer can be flexibly matched according to the actual situation, which belongs to the common knowledge of those skilled in the art.

According to the method for forming the semiconductor gate structure of the embodiment of the present invention, a Sn metal layer is first sputtered on the Ge surface, and then the upper Sn layer is removed by a wet process such as dilute hydrochloric acid to obtain a GeSn layer, and the ultra-thin GeSn layer is partially or completely sulfurized. It is converted into a GeSnS _x passivation layer, thereby improving the electrical properties of the Ge-based gate stack structure, such as low interface trap density and extremely low gate leakage current density. This method also has the advantage of simplicity and ease of implementation.

As shown in Figure 2, the semiconductor gate structure according to the embodiment of the present invention includes: a substrate with a Ge layer 100 as its surface; a GeSn layer 200 on the Ge layer 100; a GeSnS _x passivation layer on the GeSn layer 200 layer 300 ; and a gate stack structure 400 (including gate dielectric 410 and gate electrode 420 ) located on GeSnS _x passivation layer 300 .

Wherein, the substrate with the Ge layer 100 as the surface includes: a pure Ge substrate or a substrate with a Ge thin film on the surface, for example, a substrate with a Ge thin film surface on a Si substrate.

Wherein, the GeSn layer 200 can be formed by forming a Sn layer on the Ge layer 100 (the Sn layer is finally sacrificed, so it is not drawn in FIG. 2 ), and then naturally formed at the interface between the Ge layer 100 and the Sn layer or Strengthened by annealing treatment. The annealing temperature range may be 50-200° C., the higher the temperature, the thicker the GeSn layer 200 formed. Because the GeSn layer formed by diffusion is a solid solution, has the same crystal structure as Ge and has good semiconductor properties (such as GeSn has a higher hole mobility than Ge), so the GeSn layer formed on the Ge surface usually not only does not Deteriorating the performance of Ge devices may also improve device performance.

Wherein, the GeSnS _x passivation layer 300 is obtained by partially sulfiding the surface layer of the GeSn layer 200 .

In an embodiment of the present invention, the GeSnS _x passivation layer 300 may be obtained by annealing and sulfiding the surface layer of the GeSn layer 200 in sulfur vapor. For example, annealing in sulfur vapor at a temperature of 100-500°C, the optimal temperature range is 200-400°C.

In an embodiment of the present invention, the GeSnS _x passivation layer 300 may also be obtained by soaking the surface layer of the GeSn layer 200 in a solution containing sulfur ions for wet chemical vulcanization. The solution containing sulfide ions may be an aqueous solution of one or more combinations of ammonium sulfide, hydrogen sulfide, and sodium sulfide. For example, 0.1-20wt.% ammonium sulfide aqueous solution can be selected, and the reaction temperature can be selected at 20-80°C.

It should be noted that the top portion of the GeSn layer 200 in contact with the _GeSnSx passivation layer 300 can be formed by using a solution with a high corrosion selectivity to GeSn and Sn (such as dilute hydrochloric acid, dilute sulfuric acid, ammonia or sodium hydroxide solution, etc. etc.) to remove the exposed Sn layer on the GeSn layer 200 after cleaning. Optionally, the thickness of the remaining GeSn layer 200 after cleaning is 0.5-40 nm, that is, the thickness of the GeSn layer 200 in the final semiconductor gate structure is 0.5-40 nm.

Wherein, the gate stack structure 400 generally includes a dielectric layer 410 and a gate electrode layer 420 . In an embodiment of the present invention, the dielectric layer may be high-k material HfO ₂ , Al ₂ O ₃ or ZrO ₂ , and the gate electrode layer may be TiN or TaN. It should be noted that, in addition to the above examples, the materials of the dielectric layer and the gate electrode layer can be flexibly selected and matched according to the actual situation, which belongs to the common knowledge of those skilled in the art.

According to the semiconductor gate structure of the embodiment of the present invention, there is a _GeSnSx passivation layer, and a high-performance GeSn semiconductor layer is also formed between Ge and _GeSnSx , and the thickness of the GeSn and _GeSnSx layers is controllable, thereby improving The electrical properties of the gate stack structure, such as low interface trap density and extremely low gate leakage current density, the semiconductor gate structure of this embodiment also has the advantages of simple structure and low cost.

In order for those skilled in the art to better understand the present invention, the inventor elaborates a specific embodiment as follows in conjunction with Fig. 3-Fig. 4: In the following embodiment, the high- _k dielectric and Ge interface between substrates. Sn was sputtered on the Ge substrate, then the top Sn layer was removed with dilute HCl, and the GeSn layer was sulfided to obtain a _GeSnSx layer. This technique yields an ultrathin layer of _GeSnSx , about 1nm thick. It was found that, compared with the Ge/HfO ₂ MOS capacitor device without the passivation layer, the MOS gate stack structure with GeSnS _x layer has better electrical performance. The measurement results show that the equivalent oxide thickness (EOT) and interface state density (D _it ) of Ge/GeSnS _x /HfO ₂ MOS capacitors are 2.4nm and 5.3×10 ¹¹ cm ^-2 ·eV ^-1 , respectively. specifically:

First, the provided substrate is a Sb-doped (100) plane n-type Ge wafer with a resistivity of 0.09Ω·cm. After rinsing the Ge substrate with dilute HF (1:50) and deionized water circulation, Sn was magnetron sputtered on the Ge substrate, and then the wafer was immersed in dilute HCl (10%) for 3 min to remove the top Sn layer, An ultrathin GeSn layer is left on the Ge surface. The wafer is then immersed in a 20% ammonium sulfide solution for 30 minutes to achieve surface sulfide treatment, and this ultra-thin GeSn layer will be converted into a _GeSnSx layer. Subsequently, a 5.5 nm thick _HfO2 layer was deposited by ALD using tetrabis(ethylmethylammonia) hafnium (TEMAH) and water as precursors. Finally, the gate electrode Al is evaporated and patterned to obtain a MOS capacitor. The characterization method of the MOS capacitor mainly includes measuring the capacitance-voltage (Cg-Vg) characteristic curve and the leakage current density-voltage (Jg-Vg) characteristic curve of the MOS capacitor with the Agilent B1500A semiconductor device analyzer, and analyzing its electrical characteristics.

Fig. 3 is a Cg-Vg curve of Ge/GeSnS _x /HfO ₂ /Al MOS capacitor. For the Ge/GeSnS _x /HfO ₂ /Al capacitor sample, the Cg-Vg curve presents a sharp slope with little warping in the inversion region, indicating that the interface state density is low. It can be seen that the GeSnS _x layer introduced into the high-k dielectric structure on the Ge substrate can have a better passivation effect. The interface state density of the Ge/GeSnS _x /HfO ₂ /Al capacitor sample is about 5.3×10 ¹¹ cm ^-2 ·eV ^-1 through conductometric measurement and analysis.

Fig. 4 is a Jg-Vg characteristic curve of the Ge/GeSnS _x /HfO ₂ /Al MOS structure. The leakage current density of Ge/GeSnS _x /HfO ₂ /Al samples is lower than 2.2×10 ^-7 A/cm ² in the voltage range of -1~1V. In general, the present invention electrically passivates the interface between the high-k dielectric and the Ge substrate by introducing an ultra-thin _GeSnSx layer. The preparation method of GeSnS _x is as follows: a GeSn layer is obtained by sputtering a Sn layer on a Ge substrate, the Sn layer is removed with dilute hydrochloric acid, and the GeSn layer is sulfurized to form a GeSnS _x layer. Compared with direct deposition of high-k materials on Ge substrates, the D _it and leakage current density of Ge/GeSnS _x /HfO ₂ /Al MOS capacitors are reduced, which are 5.3×10 ¹¹ eV ^-1 cm ^-2 and 2.2 ×10 ^-7 A/cm ² It can be seen that the GeSnS _x layer introduced into the high-k dielectric structure on the Ge substrate can have a better passivation effect.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments or portions of code comprising one or more executable instructions for implementing specific logical functions or steps of the process , and the scope of preferred embodiments of the invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order depending on the functions involved, which shall It is understood by those skilled in the art to which the embodiments of the present invention pertain.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations to the present invention. Variations, modifications, substitutions, and modifications to the above-described embodiments are possible within the scope of the present invention.

Claims (17)

1. A method for forming a semiconductor gate structure, comprising the following steps: providing a substrate with a Ge layer as the surface; forming a Sn layer on the Ge layer, wherein the interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; performing a sulfurization treatment on the GeSn layer to form a _GeSnSx passivation layer; and A gate stack structure is formed on the _GeSnSx passivation layer. 2 . The method for forming a semiconductor gate structure according to claim 1 , further comprising: strengthening the GeSn layer by annealing before removing the Sn layer. 3 . 3. The method for forming a semiconductor gate structure as claimed in claims 1 and 2, wherein the sulfidation treatment is: annealing and sulfidation in sulfur vapor, so that part or all of the GeSn layer becomes a _GeSnSx passivation layer . 4 . The method for forming a semiconductor gate structure according to claim 3 , wherein the annealing and sulfurization temperature is 100-400° C. 5. The method for forming a semiconductor gate structure according to claims 1 and 2, characterized in that the sulfurization treatment is: soaking in a solution containing sulfur ions for wet chemical sulfurization, so that the GeSn layer is partially or completely changed into a GeSnS _x passivation layer. 6 . The method for forming a semiconductor gate structure according to claim 5 , wherein the solution containing sulfide ions contains one or more of ammonium sulfide, hydrogen sulfide, and sodium sulfide in combination. 7 . The method for forming a semiconductor gate structure according to claim 1 , wherein the Sn layer is removed by cleaning with a solution having a high etch selectivity to GeSn and Sn to expose the GeSn layer. 8 . The method for forming a semiconductor gate structure according to claim 7 , wherein the GeSn layer remaining after the cleaning has a thickness of 0.5-40 nm. 9 . The method for forming a semiconductor gate structure according to claim 1 , wherein the substrate having a Ge layer as a surface comprises: a pure Ge substrate or a substrate whose surface layer is a Ge thin film. 10. A semiconductor gate structure, characterized in that it comprises: A substrate with a Ge layer as the surface; a GeSn layer on top of the Ge layer; a _GeSnS passivation layer overlying the GeSn layer; and A gate stack structure on the _GeSnSx passivation layer. 11. The semiconductor gate structure according to claim 10, characterized in that, the GeSn layer is firstly formed on the Ge layer with a Sn layer, and then naturally formed at the interface between the Ge layer and the Sn layer formed or strengthened by annealing. 12. The semiconductor gate structure according to claim 10 or 11, wherein the _GeSnSx passivation layer is obtained by annealing and sulfiding part or all of the GeSn layer in sulfur vapor. 13. The semiconductor gate structure according to claim 12, wherein the annealing and sulfurization temperature is 100-400°C. 14. The semiconductor gate structure according to claim 10 or 11, characterized in that, the _GeSnSx passivation layer is obtained by soaking part or all of the GeSn layer in a solution containing sulfide ions for wet chemical sulfidation. 15 . The semiconductor gate structure according to claim 14 , wherein the solution containing sulfide ions contains one or a combination of ammonium sulfide, hydrogen sulfide, and sodium sulfide. 16. The semiconductor gate structure according to claim 10, wherein the thickness of the GeSn layer is 0.5-40 nm. 17 . The semiconductor gate structure according to claim 10 , wherein the substrate with the Ge layer as the surface comprises: a pure Ge substrate or a substrate with a Ge thin film on the surface.

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