CN107248527A - The high low In components InGaAs of K/AlN/ mos capacitance preparation method - Google Patents

Abstract

The invention discloses a method for preparing a MOS capacitor with high K/AlN/low In composition InGaAs, which mainly solves the problem of high interface state density of existing similar devices, which includes from bottom to top: ohmic contact metal, substrate, GaAs buffer layer, InGaAs channel layer, AlN passivation layer, high K oxide layer and metal gate electrode. Among them, the doping concentration of the InGaAs channel layer is 1×10 ¹⁷ /cm ³ , and the thickness is 15-30nm, which is used to provide effective carriers; the thickness of the AlN passivation layer is 1-5nm, which is used to improve the high K/InGaAs interface defects ; The high-K oxide layer uses Al ₂ O ₃ or TiO ₂ oxide, and its thickness is 5-10nm, which is used to increase the breakdown field strength and reduce gate leakage. The invention reduces the interface state density of the device, improves the electrical characteristics of the device, and can be used in the manufacture of silicon-based complementary metal oxide semiconductor devices.

Description

Preparation method of MOS capacitor with high K/AlN/low In composition InGaAs

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a high-K/AlN/low-In InGaAs MOS capacitor with AlN as a passivation layer, which can be used in the manufacture of silicon-based complementary metal oxide semiconductor devices.

Background technique

In the past forty years, silicon-based complementary metal-oxide-semiconductor CMOS technology has followed Moore's Law, and has achieved great success by reducing the feature size and gate oxide thickness to improve performance, but the feature size of transistors has been reduced to 22nm. , Silicon-based CMOS technology to further reduce the size to improve performance is facing both physical and technical challenges. With the reduction of size, power consumption has become the main technical problem to be faced by the semiconductor industry.

In order to solve the power consumption problem of CMOS devices, the scientific research community and the industry have replaced Si with channel materials with high carrier mobility and saturation velocity, such as III-V compound semiconductors, which have larger and faster Channel drive current, which can reduce the dynamic power consumption of the device. Among many high field mobility MOSFETs, the reason why InGaAs has become a hotspot in the field of semiconductor device research is that its electron mobility is 6–18 times that of Si, and it has both GaAs low leakage characteristics and InAs’s excellent carrier transport characteristics. The high In and Ga components can make InGaAs material have low leakage characteristics and high carrier transport characteristics, so it has great potential as a conductive channel layer of field effect transistors.

Now, the higher interface defect density between high K/InGaAs has become an important factor affecting its electrical properties. The defect state density causes the Fermi level pinning, the hysteresis voltage increases, and the capacitance dispersion of the accumulation region hinders the InGaAs With the development of devices, it is an important issue to find ways to improve the high K/InGaAs interface state. For InGaAs with a high In composition, C. Weiland et al. used AlN as a passivation layer to improve the interface trap density, but for InGaAs with a low In composition, no one has studied the passivation effect of AlN on it.

Invention content:

The present invention aims to provide a high-K/AlN/low-In composition InGaAs MOS capacitor preparation method for InGaAs channel MOS devices with low In composition. By inserting an AlN passivation layer, the interface state density can be effectively reduced and the device can be improved. electrical properties.

To achieve the above object, the realization steps of the present invention include:

(1) The low In composition p-InGaAs epitaxial material is cleaned and pretreated in a dry N2 atmosphere in sequence;

(2) Put the pretreated sample into the ALD chamber, and deposit AlN with a thickness of 1-5 nm on its upper surface by PEALD process;

(3) Deposit a high-K oxide layer dielectric on the upper surface of the sample after AlN deposition by ALD process;

(4) Put the sample with the grown high-K oxide layer dielectric into an annealing furnace at a temperature of 400-500° C., and perform post-deposition annealing in an N2 atmosphere for 1-2 minutes;

(5) Deposit a gate electrode TiN with a thickness of 50-150 nm on the upper surface of the annealed sample by PVD process;

(6) Put the sample of the TiN grown gate electrode into an electron beam evaporation furnace, and deposit Ti/Pt/Au metal on its lower surface by an electron beam evaporation process to make an ohmic contact;

(7) Put the ohmic-contacted sample into a rapid annealing furnace at a temperature of 400-500° C., and perform rapid annealing in an atmosphere of 5% H2 and 95% N2 for 30-60 s.

Compared with the prior art, the present invention has the following advantages:

1. The present invention adopts AlN material to make passivation layer, has improved the interface state density of high K/low In composition InGaAs, thereby has improved device performance, as raising Ion/Ioff ratio, raising threshold voltage, raising channel effective mobility And improve the Fermi level pinning effect.

2. The present invention uses InGaAs material as the channel layer, which has the characteristics of high electron mobility, high electron saturation speed and low power consumption compared with ordinary Si-based devices, and is suitable for low power consumption and high frequency and other fields.

Description of drawings

Fig. 1 is a structure diagram of a MOS capacitor with high K/AlN/low In composition InGaAs of the present invention.

Fig. 2 is a flow chart of the present invention for making MOS capacitors with high K/AlN/low In composition InGaAs.

detailed description:

The present invention will be further described below in conjunction with accompanying drawing.

Referring to Fig. 1, the device structure of the present invention includes ohmic contact metal, P-type GaAs substrate, P-type GaAs buffer layer, P-type InGaAs channel layer, AlN passivation layer, high-K oxide layer and metal gate electrode from bottom to top ,in:

The substrate material is GaAs or InP or GaSb;

The P-type GaAs buffer layer on the substrate, with a doping concentration of 1×10 ¹⁷ /cm ³ and a thickness of 400-500nm, is used to provide a transition from the substrate to the P-type InGaAs channel layer, and the absorbing substrate is outward Diffused impurities and prevent substrate defects from extending to the P-type InGaAs channel layer;

The P-type InGaAs channel layer on the P-type GaAs buffer layer has a doping concentration of 1×10 ¹⁷ /cm ³ and a thickness of 15-30 nm for providing effective carriers;

The thickness of the AlN passivation layer is 1-5nm, which is used to reduce the interface defect state density and improve the electrical characteristics of the device. The high K oxide layer on the AlN passivation layer uses Al ₂ O ₃ or TiO ₂ oxide, and its thickness It is 5-10nm, which is used to increase the breakdown field strength and reduce gate leakage.

Referring to FIG. 2 , the present invention provides the following three embodiments of the method for fabricating MOS capacitors with high K/AlN/low In composition InGaAs.

Embodiment 1, fabricating a MOS capacitor with Al ₂ O ₃ as the high-K oxide, In _0.2 Ga _0.8 As as the channel layer, and GaAs as the substrate.

Step 1, pretreat the In _0.2 Ga _0.8 As epitaxial material, as in 2(a).

1.1) Degrease the In _0.2 Ga _0.8 As epitaxial material sample in acetone and isopropanol, and then rinse with deionized water;

1.2) Soak the rinsed sample in a 1% HF solution for 20 seconds to remove the intrinsic oxide on the surface, then soak it in an ammonium sulfide solution for 1 min, rinse it with deionized water after taking it out, and put it under N ₂ drying in the atmosphere.

Step 2, depositing an AlN passivation layer, as shown in Figure 2(b)

The pretreated In _0.2 Ga _0.8 As epitaxial material sample was deposited 1nm-thick AlN by PEALD process. The deposition process parameters were: the precursors were TMA and NH ₃ plasma, the power of the plasma was 2500W, and the gas The flow rate was 160 sccm and the temperature was 250°C.

Step 3, deposit Al ₂ O ₃ oxide layer, as shown in Figure 2(c).

On the upper surface of the sample after AlN deposition, 10nm thick Al ₂ O ₃ was deposited by ALD process, the deposition process parameters were: the precursors were TMA and H ₂ O, and the temperature was 250°C.

Step 4, post-deposition annealing.

The sample after depositing Al ₂ O ₃ was put into an annealing furnace at a temperature of 500° C., and post-deposition annealing was performed in N ₂ atmosphere for 1 minute.

Step 5, depositing a TiN gate electrode, as shown in Figure 2(d).

On the upper surface of the annealed sample, a 100nm thick TiN gate electrode was deposited by PVD process, the electrode diameters were 200um and 300um, and the distance between the two electrodes was 200um.

Step 6, deposit ohmic contact metal, as shown in Figure 2(e).

Put the grown TiN sample into an electron beam evaporation furnace, and deposit a Ti/Pt/Au metal layer on the lower surface of the sample with an electron beam evaporation process, the thickness of which is 40nm/40nm/200nm.

Step 7, rapid annealing.

Put the sample with deposited ohmic contact metal into a rapid annealing furnace at a temperature of 400° C., and perform rapid annealing in an atmosphere of 5% H ₂ and 95% N ₂ for 1 minute.

Example 2, making a MOS capacitor with TiO ₂ as the high-K oxide, In _0.2 Ga _0.8 As as the channel layer, and InP as the substrate.

Step 1, pretreating the In _0.2 Ga _0.8 As epitaxial material.

The specific realization of this step is the same as step 1 of embodiment 1

Step 2, depositing an AlN passivation layer.

The pretreated In _0.2 Ga _0.8 As epitaxial material sample was deposited 3nm-thick AlN by PEALD process. The deposition process parameters were: the precursors were TMA and NH ₃ plasma, the power of the plasma was 2800W, and the gas The flow rate was 180 sccm and the temperature was 300°C.

Step 3, depositing a TiO ₂ oxide layer.

On the upper surface of the sample after AlN deposition, 5nm thick TiO ₂ was deposited by ALD process, the deposition process parameters were as follows: the precursors were tetradimethylaminotitanium and H ₂ O, and the temperature was 250°C.

Step 4, post-deposition annealing

Put the sample after depositing TiO ₂ into an annealing furnace at a temperature of 400° C., and perform post-deposition annealing in N ₂ atmosphere for 90 seconds.

Step five, deposit TiN gate metal.

On the upper surface of the annealed sample, a 150nm thick TiN gate electrode was deposited by PVD process, the electrode diameters were 200um and 300um, and the distance between the two electrodes was 200um.

Step six, depositing ohmic contact metal.

Put the grown TiN sample into an electron beam evaporation furnace, and deposit a Ti/Pt/Au metal layer on the lower surface of the sample with an electron beam evaporation process, with a thickness of 30nm/30nm/150nm.

Step seven, rapid annealing.

Put the sample with deposited ohmic contact metal into a rapid annealing furnace at a temperature of 500° C., and perform rapid annealing for 30 seconds in an atmosphere of 5% H ₂ and 95% N ₂ .

Example 3, making a MOS capacitor whose high-K oxide is Al ₂ O ₃ , the channel layer is P-type In _0.3 Ga _0.7 As, and the substrate is GaSb.

Step A, pretreating the In _0.3 Ga _0.7 As epitaxial material.

The specific realization of this step is the same as step 1 of embodiment 1

Step B, depositing an AlN passivation layer.

The pretreated In _0.3 Ga _0.7 As epitaxial material sample was deposited 5nm thick AlN by PEALD process. The deposition process parameters were: the precursors were TMA and NH ₃ plasma, the plasma power was 2600W, and the gas The flow rate was 200 sccm and the temperature was 300°C.

Step C, depositing an Al ₂ O ₃ oxide layer.

On the upper surface of the sample after AlN deposition, 5nm thick Al ₂ O ₃ was deposited by ALD process, the deposition process parameters were: the precursors were TMA and H ₂ O, and the temperature was 200°C.

Step D, post-deposition annealing.

The sample after depositing Al ₂ O ₃ was put into an annealing furnace at a temperature of 400° C., and post-deposition annealing was performed in N ₂ atmosphere for 2 minutes.

Step E, depositing TiN gate metal.

On the upper surface of the annealed sample, a 90nm thick TiN gate electrode was deposited by PVD process, the electrode diameters were 200um and 300um, and the distance between the two electrodes was 200um.

Step F, depositing ohmic contact metal.

Put the grown TiN sample into an electron beam evaporation furnace, and deposit a Ti/Pt/Au metal layer on the lower surface of the sample with an electron beam evaporation process, with a thickness of 30nm/50nm/200nm.

Step G, rapid annealing.

Put the sample with deposited ohmic contact metal into a rapid annealing furnace at a temperature of 450° C., and perform rapid annealing for 40 seconds in an atmosphere of 5% H ₂ and 95% N ₂ .

The above descriptions are only three embodiments of the present invention, and do not constitute any limitation to the present invention. Anyone can make changes according to the concept and scheme of the present invention, such as replacing materials and changing parameters, but these are all included in the present invention. within the scope of protection.

Claims (10)

1. A MOS capacitor with high K/AlN/low In composition InGaAs, including ohmic contact metal, P-type GaAs substrate, P-type GaAs buffer layer, P-type InGaAs channel layer, and high-K oxide layer from bottom to top and a metal gate electrode, characterized by: Between the P-type InGaAs channel layer and the high-K oxide layer, an AlN passivation layer is added to reduce the interface defect state density and improve the electrical characteristics of the device; The P-type InGaAs channel layer, with a doping concentration of 1×10 ¹⁷ /cm ³ and a thickness of 15-30 nm, is used to provide effective carriers; The high-K oxide layer uses Al ₂ O ₃ or TiO ₂ oxide with a thickness of 5-10nm, which is used to increase the breakdown field strength and reduce gate leakage. 2. The capacitor according to claim 1, characterized in that the P-type GaAs buffer layer has a doping concentration of 1×10 ¹⁷ /cm ³ and a thickness of 400-500 nm, which is used to provide a channel from the substrate to the P-type InGaAs Layer transition, absorbing impurities diffused out of the substrate and preventing substrate defects from extending to the P-type InGaAs channel layer. 3. The capacitor according to claim 1, characterized in that the thickness of the AlN passivation layer is 1-5 nm. 4. The capacitor according to claim 1, the substrate material is GaAs or InP or GaSb. 5. A MOS capacitance preparation method of high K/AlN/low In composition InGaAs, comprising: (1) The low In composition p-InGaAs epitaxial material is cleaned and pretreated in a dry _N2 atmosphere in sequence; (2) Put the pretreated sample into the ALD chamber, and deposit AlN with a thickness of 1-5 nm on its upper surface by PEALD process; (3) Deposit a high-K oxide layer dielectric on the upper surface of the sample after AlN deposition by ALD process; (4) Put the sample with the grown high-K oxide layer dielectric into an annealing furnace at a temperature of 400-500° C., and perform post-deposition annealing in _N2 atmosphere for 1-2 minutes; (5) Deposit a gate electrode TiN with a thickness of 50-150 nm on the upper surface of the annealed sample by PVD process; (6) Put the sample of the TiN grown gate electrode into an electron beam evaporation furnace, and deposit Ti/Pt/Au metal on its lower surface by an electron beam evaporation process to make an ohmic contact; (7) Put the sample with ohmic contact into a rapid annealing furnace at a temperature of 400-500° C., and perform rapid annealing in an atmosphere of 5% H ₂ and 95% N ₂ for 30-60 s. 6. The method according to claim 5, wherein the low In composition p-InGaAs epitaxial material in step (1) is In _0.2 Ga _0.8 As or In _0.3 Ga _0.7 As. 7. the method for making MOS electric capacity according to claim 5, wherein adopt PEALD process to deposit AlN in the step (2), its process parameter is: The precursors are Al(CH ₃ ) ₃ (TMA) and NH ₃ plasma; The plasma power is 2500-2800W; NH ₃ gas flow rate is 160-200sccm; The temperature is 250-400°C. 8. The method according to claim 5, wherein the high-K oxide medium deposited by ALD process in the step (3) is Al ₂ O ₃ , and its process parameters are: The precursors are TMA and H ₂ O; Al ₂ O ₃ thickness is 5-10nm; The temperature is 100-250°C. 9. The method according to claim 5, wherein the high-K oxide layer medium adopting ALD process deposition in the step (3) is TiO ₂ , and its process parameters are: The precursor is titanium tetradimethylamide and H ₂ O; The thickness of _TiO2 is 5-10nm; The temperature is 100-250°C. 10. The method according to claim 5, wherein the thickness of the metal electrode Ti/Pt/Au in the step (6) is as follows: The thickness of Ti is 20-50nm; The thickness of Pt is 20-50nm; The thickness of Au is 150-300nm.