CN103559105A - ERC32 processor-based satellite-borne software system and reentry method thereof - Google Patents
ERC32 processor-based satellite-borne software system and reentry method thereof Download PDFInfo
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Abstract
An ERC32 processor-based satellite-borne software system comprises an exception trap entry, a fault information saving module, a faulty booting identifier setting module, a fault type judgment and processing module, a soft resetting module and an interrupt return module. When an exception trap interrupt enters the exception trap entry, the faulty booting identifier setting module is called to set a faulty booting identifier as a fixed value, and the fault type judgment and processing module is called to judge the fault trap type of an ERC32 processor; if the fault trap type belongs to an unrecoverable error, then soft resetting instruction rebooting is executed; if the fault trap type belongs to a recoverable error, then interrupt return is executed; after soft resetting instruction rebooting, a main program is started, a faulty booting identifier reading module is called to read the faulty booting identifier, and a faulty booting identifier judgment module is then called to judge the faulty booting identifier. The invention solves the problem on how to save system data after the satellite-borne software is abnormal, thus enhancing the fault-tolerant ability of the satellite-borne software, and moreover, on-orbit faults can be corrected in time.
Description
Technical field
The present invention relates to spaceborne software systems, particularly a kind of spaceborne software systems and re-access method thereof based on ERC32 processor.
Background technology
Spaceborne software is in space environment in orbit time, owing to there being the factors such as High energy particles Radiation, vacuum, elemental oxygen and the large temperature difference, may cause processor to occur all kinds of abnormal, in this case, the suitable processing that the spaceborne software of application ERC32 processor will be taked classification extremely for these, makes system recover normal operation.
ERC32 processor comprises an integer unit (IU), floating point unit (FPU), a memory controller and a dma controller, concerning real-time application, TSC695 provides the Watch Dog Timer of a high security, 2 timers and interruptable controller, parallel/serial communication interface, can select the measure of the parity check sum EDAC verification of inner/outer bus to carry out error detection, error correction.
ERC32 processor has abundant exception trap treatment mechanism, can support at most 256 synchronous traps and asynchronous interrupt, software can read tt field by internal register TBR and obtain fault type, according to the technical characterstic of processor, for the processing of these faults, can be divided into two large classes:
(1) recoverable error, takes to interrupt returning reentry system;
(2) fatal error, need to take to restart just can reentry system.
So just relate to software and need to judge software reset's reason in start-up code section, with judgement, resetting is because the satellite and the rocket are separated or cold machine turns the electrification reset that heat engine causes, still the software reset who causes due to fault, because rail control application software need to keep attitude state of a control before fault, most of variable, as clock, attitude angle, angular velocity all can not zero clearing, and should take respective handling according to judged result, all zero clearings during power-up initializing, but under failure condition, the value of this class variable needs to retain, do not do initialization zero clearing, and carry out three, get two recovery operations.
In orbit and based on the spaceborne software of ERC32 processor, mainly take the method for direct reduction reentry system what grind at present, but can not distinguish like this power-up initializing and fault initialization, because all variablees are cleared, attitude control software need to re-establish state of a control from the mode of initial state Direct to the sun or global attitude acquisition, cause the uncontinuity of attitude control, bring the unsettled potential safety hazard of system.
Summary of the invention
The invention provides a kind of spaceborne software systems based on ERC32 processor, it is characterized in that, comprise the exception trap entrance that is linked in sequence, preserve failure message module, put fault initiating identification module, fault type judging treatmenting module, warm reset module, interrupt returning that module, read failure start identification module, failure judgement starts identification module
Described exception trap entrance interrupts providing the entrance entering in ERC32 processor for exception trap, described preservation failure message module is for being saved in specified memory unit by the front interrupt spot of ERC32 processor fault, the described fault initiating Sign module of putting is for being arranged to fixed value by fault initiating sign, described fault type judging treatmenting module is for judging the fault trap type of ERC32 processor, if described fault trap type belongs to fatal error, described warm reset module execution warm reset instruction is restarted; If belong to recoverable error, terminal is returned to module and carry out to be interrupted returning;
After described warm reset module execution warm reset instruction, jumping to master routine starts, wherein said Read fault starts Sign module and starts sign for read failure, described failure judgement starts Sign module for fault initiating sign is judged, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
Preferably, described exception trap interrupts comprising maskable hard error, stack overflow, internal storage access protection, bus error, floating point unit mistake, illegal request mistake and the application exception of ERC32 definition.
Preferably, described fault initiating is designated the register that internal storage location or hardware provide, and when it powers on, by hardware initialization, is zero.
Preferably, fault initiating sign at least needs triplication redundancy storage, need to do three and get two majority voting when read failure starts sign.
Preferably, fault initiating sign represent malfunction fixed value choose must contain surpass 31.
Preferably, the fault type of fault type judge module judgement is taken from trap type field in the TBR register of ERC32 processor inside.
Preferably, can recover fault type and comprise that trap type is that restarted delay mistake and the trap type that the accurate mistake of restarting of 0x61 and trap type are 0x63 is 8, floating-point trap type is 6 floating-point recoverable error, and its type is unrecoverable failure type entirely.
Preferably, describedly restart the accurate wrong processing of doing directly to interrupt returning, described restart postpone wrong nPC and be set to PC, PC subtracts 4, then remakes and interrupts returning processing, described floating-point recoverable error does to interrupt returning processing after removing floating-point queuing register FQ.
The present invention also provides a kind of spaceborne software systems re-access method based on ERC32 processor, and it provides exception trap entrance, preserves failure message module, puts fault initiating identification module, fault type judging treatmenting module, warm reset module, terminal return to module, read failure starts identification module, failure judgement starts identification module;
When triggering exception trap, computer failure interrupts entering exception trap entrance, call failure message module, the front interrupt spot of ERC32 processor fault is saved in to specified memory unit, call and put fault initiating Sign module fault initiating sign is arranged to fixed value, call the fault trap type of fault type judging treatmenting module interpretation ERC32 processor; If belong to fatal error, carry out warm reset instruction and restart; If belong to recoverable error, interrupt returning;
Warm reset instruction jumps to master routine after restarting and starts, call Read fault and start Sign module read failure startup sign, then calling failure judgement startup Sign module judges fault initiating sign, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
The invention solves the preservation problem that rear system data occurs spaceborne software anomaly, obtained and improved spaceborne software fault-tolerant ability, correct in time the beneficial effects such as on-orbit fault.
Certainly, implement arbitrary product of the present invention and might not need to reach above-described all advantages simultaneously.
Accompanying drawing explanation
The spaceborne software systems re-access method process flow diagram that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 realizes exception trap to interrupt the process flow diagram of processing in the embodiment of the present invention;
Fig. 3 is the process flow diagram of realizing the judgement of master routine malfunction and initialization reentry in the embodiment of the present invention.
Specific embodiment
The present embodiment provides a kind of spaceborne software systems based on ERC32 processor, it comprises the exception trap entrance that is linked in sequence, preserve failure message module, put fault initiating identification module, fault type judging treatmenting module, warm reset module, interrupt returning that module, read failure start identification module, failure judgement starts identification module
Described exception trap entrance interrupts providing the entrance entering in ERC32 processor for exception trap, described preservation failure message module is for being saved in specified memory unit by the front interrupt spot of ERC32 processor fault, the described fault initiating Sign module of putting is for being arranged to fixed value by fault initiating sign, described fault type judging treatmenting module is for judging the fault trap type of ERC32 processor, if described fault trap type belongs to fatal error, described warm reset module execution warm reset instruction is restarted; If belong to recoverable error, terminal is returned to module and carry out to be interrupted returning;
After described warm reset module execution warm reset instruction, jumping to master routine starts, wherein said Read fault starts Sign module and starts sign for read failure, described failure judgement starts Sign module for fault initiating sign is judged, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
Wherein said exception trap interrupts comprising maskable hard error, stack overflow, internal storage access protection, bus error, floating point unit mistake, illegal request mistake and the application exception of ERC32 definition.
Described fault initiating is designated the register that internal storage location or hardware provide, and when it powers on, by hardware initialization, is zero.
Fault initiating sign at least needs triplication redundancy storage, need to do three and get two majority voting when read failure starts sign.
Fault initiating sign represent malfunction fixed value choose must contain surpass 31.
The fault type of fault type judge module judgement is taken from trap type field in the TBR register of ERC32 processor inside.
Can recover fault type and comprise that trap type is that restarted delay mistake and the trap type that the accurate mistake of restarting of 0x61 and trap type are 0x63 is 8, the floating-point recoverable error that floating-point trap type is 6, its type is unrecoverable failure type entirely.
Describedly restart the accurate wrong processing of doing directly to interrupt returning, described restart postpone wrong nPC and be set to PC, PC subtracts 4, then remakes and interrupts returning processing, described floating-point recoverable error does to interrupt returning processing after removing floating-point queuing register FQ.
The present embodiment provides a kind of spaceborne software systems re-access method based on ERC32 processor, and it provides exception trap entrance, preserves failure message module, puts fault initiating identification module, fault type judging treatmenting module, warm reset module, terminal return to module, read failure starts identification module, failure judgement starts identification module;
As shown in Figure 1, when triggering exception trap, computer failure interrupts entering exception trap entrance, call failure message module, the front interrupt spot of ERC32 processor fault is saved in to specified memory unit, call and put fault initiating Sign module fault initiating sign is arranged to fixed value, call the fault trap type of fault type judging treatmenting module interpretation ERC32 processor; If belong to fatal error, carry out warm reset instruction and restart; If belong to recoverable error, interrupt returning;
Warm reset instruction jumps to master routine after restarting and starts, call Read fault and start Sign module read failure startup sign, then calling failure judgement startup Sign module judges fault initiating sign, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
Fig. 2 realizes the process flow diagram that in the spaceborne software systems re-access method that the present invention is based on ERC32 processor, exception trap is processed.As shown in the embodiment of Fig. 2, abnormality processing is carried out according to following algorithm flow:
Computer failure triggers exception trap and interrupts entering exception trap entrance, and first exception trap handling procedure calls preserves failure message module, and the front interrupt spot of ERC32 processor fault is saved in to specified memory unit.Call and put fault initiating Sign module, fault initiating sign is arranged to 0xAAAAAAAA, and deposit sign in register (address 0x10000000,0x10000004,0x10000008) that three hardware provide.Call fault type judging treatmenting module, the fault trap type of interpretation ERC32 processor, if belong to fatal error, carries out warm reset instruction and restarts; If belong to recoverable error, interrupt returning.
Fig. 3 realizes the process flow diagram that in the spaceborne software systems re-access method that the present invention is based on ERC32 processor, master routine malfunction judges and initialization is reentried.As shown in Figure 3, master routine initialization is reentried and is carried out according to following algorithm flow:
Warm reset instruction is restarted rear program and is jumped to master routine and start, call Read fault and start Sign module, read 3 fault initiating signs, work three is got two votings and is got most values, then call failure judgement and start Sign module, if the indication of fault initiating sign is the hard reset that powers on, calls power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.Initialization finishes to proceed to normal operation to be controlled, and software is reentried and finished.
The invention solves the preservation problem that rear system data occurs spaceborne software anomaly, obtained and improved spaceborne software fault-tolerant ability, correct in time the beneficial effects such as on-orbit fault.
The disclosed preferred embodiment of the present invention is just for helping to set forth the present invention above.Preferred embodiment does not have all details of detailed descriptionthe, and also not limiting this invention is only described embodiment.Obviously, according to the content of this instructions, can make many modifications and variations.These embodiment are chosen and specifically described to this instructions, is in order to explain better principle of the present invention and practical application, thereby under making, technical field technician can understand and utilize the present invention well.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (9)
1. spaceborne software systems based on ERC32 processor; it is characterized in that, comprise the exception trap entrance that is linked in sequence, preserve failure message module, put fault initiating identification module, fault type judging treatmenting module, warm reset module, interrupt returning that module, read failure start identification module, failure judgement starts identification module;
Described exception trap entrance interrupts providing the entrance entering in ERC32 processor for exception trap, described preservation failure message module is for being saved in specified memory unit by the front interrupt spot of ERC32 processor fault, the described fault initiating Sign module of putting is for being arranged to fixed value by fault initiating sign, described fault type judging treatmenting module is for judging the fault trap type of ERC32 processor, if described fault trap type belongs to fatal error, described warm reset module execution warm reset instruction is restarted, if belong to recoverable error, terminal is returned to module and carry out to be interrupted returning,
After described warm reset module execution warm reset instruction, jumping to master routine starts, described Read fault starts Sign module and starts sign for read failure, described failure judgement starts Sign module for fault initiating sign is judged, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
2. spaceborne software systems based on ERC32 processor as claimed in claim 1; it is characterized in that, described exception trap interrupts comprising maskable hard error, stack overflow, internal storage access protection, bus error, floating point unit mistake, illegal request mistake and the application exception of ERC32 definition.
3. the spaceborne software systems based on ERC32 processor as claimed in claim 1, is characterized in that, described fault initiating is designated the register that internal storage location or hardware provide, and when it powers on, by hardware initialization, are zero.
4. the spaceborne software systems based on ERC32 processor as claimed in claim 3, is characterized in that, fault initiating sign at least needs triplication redundancy storage, need to do three and get two majority voting when read failure starts sign.
5. the spaceborne software systems based on ERC32 processor as claimed in claim 3, is characterized in that, fault initiating sign represent the fixed value of malfunction contain surpass 31.
6. the spaceborne software systems based on ERC32 processor as claimed in claim 1, is characterized in that, the fault type of fault type judge module judgement is taken from trap type field in the TBR register of ERC32 processor inside.
7. spaceborne software systems based on ERC32 processor as claimed in claim 1, it is characterized in that, can recover fault type and comprise that trap type is that restarted delay mistake and the trap type that the accurate mistake of restarting of 0x61 and trap type are 0x63 is 8, floating-point trap type is 6 floating-point recoverable error, and its type is unrecoverable failure type entirely.
8. spaceborne software systems based on ERC32 processor as claimed in claim 7, it is characterized in that, describedly restart the accurate wrong processing of doing directly to interrupt returning, described restart postpone wrong nPC and be set to PC, PC subtracts 4, then remake and interrupt returning processing, described floating-point recoverable error does to interrupt returning processing after removing floating-point queuing register FQ.
9. the spaceborne software systems re-access method based on ERC32 processor, is characterized in that,
Exception trap entrance be provided, preserve failure message module, put fault initiating identification module, fault type judging treatmenting module, warm reset module, terminal return to module, read failure starts identification module, failure judgement starts identification module;
When triggering exception trap, computer failure interrupts entering exception trap entrance, call failure message module, the front interrupt spot of ERC32 processor fault is saved in to specified memory unit, call and put fault initiating Sign module fault initiating sign is arranged to fixed value, call the fault trap type of fault type judging treatmenting module interpretation ERC32 processor; If belong to fatal error, carry out warm reset instruction and restart; If belong to recoverable error, interrupt returning;
Warm reset instruction jumps to master routine after restarting and starts, call Read fault and start Sign module read failure startup sign, then calling failure judgement startup Sign module judges fault initiating sign, if the indication of fault initiating sign is the hard reset that powers on, call power-up initializing module all RAM and IO are carried out to initialization, otherwise call fault initialization, only minority critical data is carried out to three and get two attended operations.
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| CN104090788A (en) * | 2014-06-27 | 2014-10-08 | 上海航天电子通讯设备研究所 | Method and system for configuring and running satellite-borne software on basis of load |
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| CN105760241A (en) * | 2014-12-18 | 2016-07-13 | 联想(北京)有限公司 | Exporting method and system for memory data |
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| CN104090788A (en) * | 2014-06-27 | 2014-10-08 | 上海航天电子通讯设备研究所 | Method and system for configuring and running satellite-borne software on basis of load |
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| CN112231710B (en) * | 2020-10-16 | 2022-11-01 | 同济大学 | QNX BSP startup verification method and startup verification module |
| CN112905392A (en) * | 2021-05-07 | 2021-06-04 | 湖南华自信息技术有限公司 | System, method and computer storage medium for updating device memory |
| CN115583206A (en) * | 2022-09-30 | 2023-01-10 | 重庆长安汽车股份有限公司 | Vehicle abnormity eliminating method and device, electronic equipment and storage medium |
| CN115964249A (en) * | 2022-12-29 | 2023-04-14 | 苏州市欧冶半导体有限公司 | Embedded system software interception program design system and method |
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