CN103532531A - Power-on resetting circuit and method - Google Patents

Abstract

The invention discloses a power-on reset circuit and method. The power-on reset circuit specifically includes a linear sampling voltage divider circuit for sampling the power supply voltage, a comparator, a first inverter, a second inverter and a counter, and a linear sampling divider. The output terminal of the voltage circuit is connected to the negative input terminal of the comparator, the positive input terminal of the comparator is connected to the bandgap reference voltage, the output terminal of the comparator is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second inverter. The input terminals of the two inverters, the output terminal of the second inverter are connected to one input terminal of the counter, the other input terminal of the counter is connected to the clock signal, and the output terminal of the counter is connected to the power-on reset signal. The present invention can avoid the deviation of the resistance and capacitance caused by the manufacturing process, and output the control count enable signal by comparing the voltage division of the power supply with the bandgap reference voltage, and delay the reset signal backward by counting the clock, and wait for the After stabilization, the power-on reset signal is output, which can better ensure the correct initialization and normal operation of the chip.

Description

A power-on reset circuit and method

technical field

The invention relates to the field of chip reset circuits, and more specifically, to a reliable power-on reset circuit and method.

Background technique

When the chip is powered on, it will perform a series of initialization operations, including initializing registers, initializing various hardware, etc. In order to ensure stable and reliable operation of the circuit in the chip, the reset circuit is an essential part. The first function of the reset circuit is Power-on reset.

A typical power-on reset circuit is shown in Figure 1. The upper capacitor is connected to a high level, the lower resistor is connected to ground, and the middle bit is connected to a reset signal. This reset circuit is a high level reset. When the power is turned on, the two ends of the capacitor are equivalent to a short circuit, so the reset signal terminal is at a high level, and then the power supply charges the capacitor through the resistor, and the voltage at the reset signal terminal begins to drop slowly until it reaches a certain level, which is a low level, and the chip starts normal work. However, this rough power-on reset circuit uses only resistors and capacitors, and is affected by manufacturing process deviations, resulting in unstable power-on reset signals, which in turn affects the instability of the entire system. In view of the shortcomings of typical power-on reset circuits, comparator-type power-on reset circuits are widely used at present, as shown in Figure 2. When power-on reset, due to the formation of an RC low-pass network, the voltage of the positive-phase input terminal of the comparator is delayed by a certain time compared with the input voltage of the negative-phase terminal, and the time constant of the negative-phase terminal network of the comparator is much smaller than that of the positive-phase terminal RC. The time constant of the network, so when the positive terminal voltage has not exceeded the negative terminal voltage, the comparator outputs a low level, and generates a high level after passing through the inverter. The width of the reset pulse mainly depends on the speed of normal voltage rise. Due to the large time constant of the discharge circuit of the negative terminal voltage, it is not sensitive to the fluctuation of the power supply voltage, but it is prone to the following two unfavorable phenomena:

(1) When the interval between the secondary switching of the power supply is short, the reset is unreliable;

(2) When there is a surge phenomenon in the power supply voltage, the reset pulse may not be generated after the surge disappears.

Based on the analysis of typical power-on reset circuits, in order to ensure the stable operation of the chip, it is necessary to design a simple, stable and reliable power-on reset circuit.

Contents of the invention

The main purpose of the present invention is to overcome the problem of the reset circuit in the above-mentioned prior art, and to propose a reliable power-on reset circuit. The present invention adopts the form of transistor voltage divider power supply voltage, which avoids the deviation of resistance and capacitance caused by the manufacturing process. , and compare the power supply voltage with the bandgap reference voltage to output the control count enable signal. By counting the clock, the reset signal is delayed, and the power-on reset signal is output after the power supply voltage is stable.

In order to solve the problems of the technologies described above, the technical solution of the present invention is:

A power-on reset circuit, comprising a linear sampling voltage divider circuit for sampling the power supply voltage, a comparator, a first inverter, a second inverter and a counter, the output terminal of the linear sampling voltage divider circuit is connected to a comparison The negative input terminal of the comparator, the positive input terminal of the comparator is connected to the bandgap reference voltage, the output terminal of the comparator is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter , the output terminal of the second inverter is connected to one input terminal of the counter, the other input terminal of the counter is connected to the clock signal, and the output terminal of the counter is connected to the power-on reset signal.

According to the comparison between the output voltage of the linear sampling voltage divider circuit and the bandgap reference voltage, when the power is turned on, the output voltage rises with the power supply voltage, when the output voltage is higher than the bandgap reference voltage, the comparator outputs a low level, and after two An inverter is shaped into a counting enable signal and enters the counter, and the counter starts counting the clock. After the power supply voltage has stabilized, the counting is completed and a power-on reset signal is issued. Based on this, the chip can accurately initialize the register.

Furthermore, the linear sampling voltage divider circuit includes a transistor M0 and a transistor M1, the drain and gate of the transistor M0 are connected to the power supply voltage, and the source is connected to the drain of the transistor M1, and the drain of the transistor M1 is linear sampling At the output end of the voltage divider circuit, the gate end of the transistor M1 is connected to the power supply voltage, and the source end is grounded.

Furthermore, both the transistor M0 and the transistor M1 are NMOS transistors.

The gate terminals of the above two transistors are connected to the power supply voltage. Since the transistor M1 is in the linear region, the current of the sampling voltage divider circuit is very small, the power consumption is very low, and the output voltage is only related to the size and power supply of the transistor M0 and transistor M1. The voltage value is related. When the size of the two transistors is fixed, there is a good linear relationship between the output voltage and the power supply voltage.

That is, the size of the transistor M0 is W ₀ /L ₀ , the size of the transistor M1 is W ₁ /L ₁ , and the linear relationship between the output voltage V1 of the linear sampling voltage divider circuit and the power supply voltage VDD is:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; /</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span>$

Another object of the present invention is to propose a power-on reset method, specifically:

The linear sampling voltage divider circuit samples the power supply voltage output voltage V1, compares it with the bandgap reference voltage through a comparator, uses two series inverters to shape the comparison result, and obtains the input enable signal of the counter, and the other input of the counter The signal is a clock signal, and a sufficient delay is generated by counting the clock signal by the counter, and a power-on reset signal is issued when the power supply voltage becomes stable.

Furthermore, the linear sampling voltage divider circuit includes a transistor M0 and a transistor M1, the drain and gate of the transistor M0 are connected to the power supply voltage, and the source is connected to the drain of the transistor M1, and the drain of the transistor M1 is linear sampling At the output end of the voltage divider circuit, the gate end of the transistor M1 is connected to the power supply voltage, and the source end is grounded.

Further, the size of the transistor M0 is W ₀ /L ₀ , the size of the transistor M1 is W ₁ /L ₁ , the linear relationship between the output voltage V1 of the linear sampling voltage divider circuit and the power supply voltage VDD is:

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; /</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span>$

Compared with the prior art, the invention has the beneficial effects of avoiding the deviation of the resistance and capacitance caused by the manufacturing process, and outputting the control count enable signal by comparing the voltage division of the power supply with the bandgap reference. Counting, delaying the reset signal, and outputting the power-on reset signal after the power supply voltage is stable, can ensure the correct initialization and normal operation of the chip, and has good design advantages.

Description of drawings

Figure 1 is a schematic diagram of a typical resistor-capacitor reset circuit.

Figure 2 is a schematic diagram of a typical comparator reset circuit.

FIG. 3 is a schematic diagram of a reset circuit architecture adopted in the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings, but the embodiments of the present invention are not limited thereto.

As shown in Figure 3, a power-on reset circuit includes a linear sampling voltage divider circuit for sampling the power supply voltage, a comparator, a first inverter, a second inverter and a counter, the linear sampling voltage divider circuit The output terminal is connected to the negative input terminal of the comparator, the positive input terminal of the comparator is connected to the bandgap reference voltage, the output terminal of the comparator is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second inverter The input terminal of the inverter, the output terminal of the second inverter is connected to one input terminal of the counter, the other input terminal of the counter is connected to the clock signal, and the output terminal of the counter is connected to the power-on reset signal.

Wherein the linear sampling voltage divider circuit includes a transistor M0 and a transistor M1, the drain terminal and the gate terminal of the transistor M0 are connected to the power supply voltage, and the source terminal is connected to the drain terminal of the transistor M1, and the drain of the transistor M1 is the output of the linear sampling voltage divider circuit terminal, the gate terminal of the transistor M1 is connected to the power supply voltage, and the source terminal is grounded. Both the transistor M0 and the transistor M1 are NMOS transistors.

Specifically, one of the steps of the present invention is to use NMOS transistors M0 and M1 to form a power supply voltage sampling and dividing circuit. The drain terminal and the gate terminal of the transistor M0 are connected to the power supply voltage, and the source terminal is connected to the drain terminal V1 of the transistor M1; the gate terminal of the transistor M1 is connected to the power supply voltage, and the source terminal is grounded. According to the derivation of the formula, it can be seen that the relationship between the V1 voltage and the power supply voltage VDD is shown in formula (1). It can be seen from the expression that when the transistor M0 size (W/L) ₀ and the transistor M1 size (W/L) ₁ After fixing, V1 has a good linear relationship with VDD.

$\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; /</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The second step of the present invention is to use the divided voltage V1 to compare with the bandgap reference voltage, and output the comparison result, and use the comparison output as the input enabling signal of the counter after being shaped by two inverters, and another input signal of the counter For the clock signal, the counter counts the clock signal to generate enough delay, and when the power supply voltage becomes stable, a power-on reset signal is issued. This can avoid the shortcoming that the digital circuit cannot work normally because the power-on voltage is too low; at the same time, it can also avoid the problem of reset failure caused by the short interval between two power-on times.

The power supply voltage output is sampled by the linear sampling voltage divider circuit, and the counter is jointly controlled by the bandgap reference. The reset mechanism that delays the power-on reset signal according to the number of clock cycles has good stability, which can ensure the correct initialization of the chip and normal operation. work, with good design advantages.

The embodiments of the present invention described above are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims (7)

1. A power-on reset circuit, characterized in that, comprises a linear sampling voltage divider circuit, a comparator, a first inverter, a second inverter and a counter for sampling the supply voltage, and the linear sampling voltage divider The output terminal of the circuit is connected to the negative input terminal of the comparator, the positive input terminal of the comparator is connected to the bandgap reference voltage, the output terminal of the comparator is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second The input terminal of the inverter, the output terminal of the second inverter are connected to one input terminal of the counter, the other input terminal of the counter is connected to the clock signal, and the output terminal of the counter is connected to the power-on reset signal. 2. The power-on reset circuit according to claim 1, wherein the linear sampling voltage divider circuit comprises a transistor M0 and a transistor M1, the drain terminal and the gate terminal of the transistor M0 are connected to the power supply voltage, and the source terminal is connected to the transistor The drain terminal of M1, the drain of transistor M1 is the output terminal of the linear sampling voltage divider circuit, the gate terminal of transistor M1 is connected to the power supply voltage, and the source terminal is grounded. 3. The power-on reset circuit according to claim 2, wherein the transistor M0 and the transistor M1 are both NMOS transistors. 4. The power-on reset circuit according to claim 2, wherein the size of the transistor M0 is W ₀ /L ₀ , the size of the transistor M1 is W ₁ /L ₁ , and the output voltage of the linear sampling voltage divider circuit is The linear relationship between V1 and the power supply voltage VDD is: $\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; /</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span>$ 5. A power-on reset method, characterized in that, the linear sampling voltage divider circuit samples the power supply voltage output voltage V1, compares it with the bandgap reference voltage by a comparator, and adopts two series-connected inverters to shape the comparison result, Obtain the input enable signal of the counter, and the other input signal of the counter is a clock signal. The counter counts the clock signal to generate enough delay. When the power supply voltage becomes stable, a power-on reset signal is issued. 6. The power-on reset method according to claim 5, wherein the linear sampling voltage divider circuit includes a transistor M0 and a transistor M1, the drain terminal and the gate terminal of the transistor M0 are connected to the power supply voltage, and the source terminal is connected to the transistor The drain terminal of M1, the drain of transistor M1 is the output terminal of the linear sampling voltage divider circuit, the gate terminal of transistor M1 is connected to the power supply voltage, and the source terminal is grounded. 7. The power-on reset method according to claim 6, wherein the size of the transistor M0 is W ₀ /L ₀ , the size of the transistor M1 is W ₁ /L ₁ , and the output voltage of the linear sampling voltage divider circuit is The linear relationship between V1 and the power supply voltage VDD is: $\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; /</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; .</span>$

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