CN103531524A - Preparation method of interconnection structure with air gap - Google Patents
Preparation method of interconnection structure with air gap Download PDFInfo
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- CN103531524A CN103531524A CN201210225939.9A CN201210225939A CN103531524A CN 103531524 A CN103531524 A CN 103531524A CN 201210225939 A CN201210225939 A CN 201210225939A CN 103531524 A CN103531524 A CN 103531524A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
The present invention discloses a preparation method of an interconnection structure with an air gap, which comprises the following steps: depositing a dielectric layer on a substrate, wherein the dielectric layer is made of a carbon-containing material; selectively etching the dielectric layer for forming a plurality of groove patterns in the dielectric layer, and forming a loose first separating layer on the side walls of the groove patterns; forming filling dielectric in the groove patterns; forming a plurality of interconnected channels on the substrate, wherein the interconnected channels are staggered from the first separating layer; filling conductive material in the interconnected channels; and removing the first separating layer for forming the air gap at the side wall of each groove pattern. The method of the invention is used for reducing dielectric constant of the dielectric layer, reducing RC delay and settling a problem of low interconnection reliability.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly relate to a kind of preparation method of the interconnection structure that contains air-gap.
Background technology
Integrity problem in very lagre scale integrated circuit (VLSIC) (Very Large Scale Integration is called for short VLSI) is subject to the impact of device and interconnection technique.Along with characteristic size (Critical Dimension) is dwindled when device gate delay is reduced, also make the interconnection performance of circuit reduce.This is that the ghost effect that resistance, electric capacity, inductance cause will have a strong impact on the performance of circuit because dwindling of characteristic size will cause reducing of interconnection line cross-sectional area and distance between centers of tracks.Therefore, the integrity problem of interconnection has become the key factor of system for restricting reliability.Improve the common method of interlinking reliability for reducing for making the dielectric constant k of interlayer dielectric (ILD) material of conductive metal wire electric insulation, thereby make resistance-capacitance (RC) postpone to reduce, interconnected signal can pass conductor quickly.
At present, the method of common reduction dielectric layer material k value is mainly by following two kinds: one, adopt porous material to prepare dielectric layer, use porous material and increase its porosity and can effectively reduce its dielectric constant, and had certain improvement in mechanical properties, but adopt problems such as having in this way chemico-mechanical polishing damage, etching loss and Vapor adsorption, two, use air-gap (Air gap) to replace porous material filling around metal connecting line, in the prior art, to the method for introducing air-gap in dielectric layer, be after metal deposition and planarization, ground floor dielectric layer between etching metal interconnecting wires, form groove, deposit afterwards second layer dielectric layer, in deposition process, the groove top that dielectric layer material forms in etching is in advance pinch off gradually, so just cavity is retained in ground floor dielectric layer, but this method is difficult to, and the whole etchings of low K dielectrics layer material between metal interconnecting wires are clean, and the cavity size of adopting in the ground floor dielectric layer obtaining in this way can not be controlled, when etching second layer metal through hole, there will be to carve and wear the empty phenomenon in ground floor dielectric layer, cause serious integrity problem.
Therefore, how to provide a kind of preparation method of low k value dielectric layer, thereby improve the reliability of interconnection, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of preparation method of the interconnection structure that contains air-gap (Air gap) is provided, for reducing the dielectric constant of dielectric layer, reduce RC and postpone, solved the problem of interlinking reliability.
For solving the problems of the technologies described above, the invention provides a kind of preparation method of the interconnection structure that contains air-gap, comprising:
Dielectric layer deposition on substrate, the material of described dielectric layer is carbonaceous material;
Dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and removes the carbon of the dielectric layer be arranged in described groove pattern sidewall areas, to form the first loose interlayer on the sidewall of described groove pattern;
In described groove pattern, form filling dielectric;
On described substrate, form some interconnecting channels, described some interconnecting channels are arranged at least one of described dielectric layer and described filling dielectric, and described interconnecting channel and described the first interlayer are staggered;
Filled conductive material in described interconnecting channel; And
Remove described the first interlayer, with the side-walls at described groove pattern, form air-gap.
Further, adopt dielectric layer described in dry etch process selective etch, the etching gas of described dry etch process comprises a kind of or combination in fluorine base gas and oxygen base gas.
Further, in described dielectric layer, form the step of some groove patterns and in described groove pattern, form between the step of filling dielectric, also comprise burin-in process step, continue to remove the carbon of the dielectric layer that is arranged in described groove pattern sidewall areas, to adjust the thickness of described the first interlayer.
Further, the reacting gas of described burin-in process step comprises oxygen base gas.
Further, after removing the step of described the first interlayer, described interconnecting channel has described air-gap each other.
Further, after removing the step of described the first interlayer, the quantity of described adjacent interconnecting channel described air-gap is each other more than or equal to 1.
Further, this preparation method also comprises:
When forming some interconnecting channels on described substrate, remove the dielectric layer of sidewall areas of described interconnecting channel or the carbon in filled media, to form the second loose interlayer on the sidewall of described interconnecting channel;
Filled conductive material in described interconnecting channel; And
When removing described the first interlayer, remove described the second interlayer, with the side-walls at described interconnecting channel, form interconnecting channel air-gap.
Further, on substrate, before dielectric layer deposition step, also comprise: deposition-etch stop-layer on described substrate.
Further, the step of dielectric layer deposition and forming in described dielectric layer between the step of some groove patterns on substrate, also comprises: deposition oxide protective layer and hard mask layer successively on described dielectric layer.
Further, the low-dielectric material that the material of described dielectric layer is carbon containing.
Further, the material of described filling dielectric is identical with the material of described dielectric layer.
Further, described interconnecting channel is a kind of or combination in raceway groove and through hole.
Further, describedly by the step that electric conducting material is filled described interconnecting channel, comprise:
Metal barrier and the Seed Layer of in described interconnecting channel, preparing described electric conducting material;
Deposit described electric conducting material to fill described interconnecting channel; And
Described in planarization, electric conducting material is to expose described dielectric layer.
Further, adopt wet-etching technology to remove described the first interlayer.
Further, the etching liquid of described wet-etching technology is the hydrofluoric acid of dilution.
Compared with prior art, the preparation method of the interconnection structure that contains air-gap provided by the invention has the following advantages:
1, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, then after electric conducting material is filled described interconnecting channel, remove described the first interlayer to form air-gap, described air-gap has reduced the dielectric constant of dielectric layer, reduces RC and postpones.
2, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, then after electric conducting material is filled described interconnecting channel, remove described the first interlayer to form air-gap, so forming the process of air-gap can not exert an influence to interconnecting channel, avoided the conducting of air-gap and interconnecting channel, the reliability that improves interconnection structure is high.
3, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, the thickness of the first interlayer is nanoscale, the gauge of the air-gap forming so remove afterwards described the first interlayer is little, and the gauge of air-gap, length dimension, quantity, arrangement mode and shape are all adjustable, so the mechanicalness of the interconnection structure that employing the method obtains can be controlled.
Accompanying drawing explanation
Fig. 1 is the preparation method's of the interconnection structure that contains air-gap in one embodiment of the invention flow chart;
Fig. 2 a-Fig. 2 f is the preparation method's of the interconnection structure that contains air-gap in one embodiment of the invention schematic diagram;
The schematic diagram of the interconnection structure that the preparation method that Fig. 3 a-Fig. 3 c is the employing interconnection structure that contains air-gap of the present invention obtains.
Embodiment
Below in conjunction with schematic diagram, the preparation method of the interconnection structure that contains air-gap of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to the restriction of relevant system or relevant business, by an embodiment, change into another embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with reference to accompanying drawing, with way of example, the present invention is more specifically described.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of preparation method of the interconnection structure that contains air-gap is provided, dielectric layer deposition on substrate, the material of described dielectric layer is carbonaceous material, dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, removal is arranged in the carbon of the dielectric layer of described groove pattern sidewall areas, to form the first loose interlayer on the sidewall of described groove pattern, in described groove pattern, form filling dielectric, the sidewall of described filling dielectric and described groove pattern separates by described the first interlayer, after conductive interconnection passage forms, remove described the first interlayer, with the side-walls at described groove pattern, form air-gap, described air-gap has reduced the dielectric constant of dielectric layer, and the gauge of air-gap, length dimension, quantity, arrangement mode and shape are all adjustable, so the mechanicalness of this interconnection structure can be controlled.
Please refer to Fig. 1, Fig. 1 is the preparation method's of the interconnection structure that contains air-gap in one embodiment of the invention flow chart, in conjunction with Fig. 1 and core concept of the present invention, the invention provides a kind of preparation method of the interconnection structure that contains air-gap, comprises the following steps:
Step S01, dielectric layer deposition on substrate, the material of described dielectric layer is carbonaceous material;
Step S02, dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and remove the carbon of the dielectric layer be arranged in described groove pattern sidewall areas, to form the first loose interlayer on the sidewall of described groove pattern;
Step S03 forms filling dielectric in described groove pattern;
Step S04, on described substrate, form some interconnecting channels, described some interconnecting channels are arranged in described dielectric layer or described filling dielectric, or lay respectively in described dielectric layer and described filling dielectric, and described interconnecting channel and described the first interlayer are staggered;
Step S05, filled conductive material in described interconnecting channel;
Step S06, removes described the first interlayer, with the side-walls at described groove pattern, forms air-gap.
Below please refer to the detailed process that Fig. 1 and Fig. 2 a-Fig. 2 f describe the preparation method of the interconnection structure that contains air-gap of the present invention in detail, wherein, Fig. 2 a-Fig. 2 f is the preparation method's of the interconnection structure that contains air-gap in one embodiment of the invention schematic diagram.
First carry out step S01, on substrate 101, dielectric layer deposition 102, wherein substrate 101 comprises necessary device and interconnection, described substrate 101 can be for having the Semiconductor substrate of source area, drain region and isolation structure, can also be for comprising the structure of the multilayer interconnection layer in above-mentioned Semiconductor substrate and Semiconductor substrate.In the present embodiment, before step S01, also be included in the step of deposition-etch stop-layer 201 on substrate 101, so first adopt conventional method deposition-etch stop-layer 201 on substrate 101, described etching stop layer 201 can play etching stopping effect in subsequent etching forms the process of groove pattern 103.Then on etching stop layer 201, adopt conventional method dielectric layer deposition 102, see Fig. 2 a.The material of dielectric layer 102 is carbonaceous material, to guarantee can to obtain easily the first interlayer 104 in subsequent step, preferably select the low-dielectric material of carbon containing, as a kind of of the silicon nitride of the fluorine silex glass of the silicon dioxide of carbon dope, carbon dope and carbon dope and combination thereof, but other carbonaceous material also can be used as the material of dielectric layer 102 also within thought range of the present invention.
Then carry out step S02, in described dielectric layer 102, form some groove patterns 103, and remove the carbon of the dielectric layer 102 be arranged in groove pattern 103 sidewall 104 regions, to there is the first interlayer 104 on the sidewall 131 at groove pattern 103, see Fig. 2 b.Adopt conventional dry etch process selective etch dielectric layer 102, to form groove pattern 103 in dielectric layer 102, in etching dielectric layer 102, plasma cognition in dry etch process is bombarded the sidewall 131 of groove pattern 103, so the carbon in the gas of dry etch process and the dielectric layer 102 in groove pattern 103 sidewall 131 regions reacts, make the material on the sidewall 131 of groove pattern 103 become more loose, form the first interlayer 104.Preferably, in dry etch process, add fluorine base gas or oxygen base gas, or add fluorine base gas and oxygen base gas simultaneously, because fluorine base gas and oxygen base gas can with carbon react, and retain the non-carbon in the dielectric layer 102 in groove pattern 103 sidewall 131 regions, so that the material on the sidewall 131 of groove pattern 103 becomes more loose, form the first interlayer 104.Can as gas flow, pressure, voltage, power etc., control the amount of removing carbon by regulating the technological parameter of dry etch process, can control the thickness of the first interlayer 104 simultaneously.The degree of depth of groove pattern 103 can be controlled, and can be equal to or less than the height of dielectric layer 102, thereby is penetrated or partly pass the first interlayer 104 of dielectric layer 102.
In preferred embodiment, between step S02 and step S03, also comprise burin-in process step, burin-in process step is further removed the carbon in the dielectric layer in groove pattern 103 sidewall 131 regions, to control the thickness of the first interlayer 104.Burin-in process step is using plasma dry etch process preferably, wherein preferably reacting gas adopts the gas containing aerobic base, make in burin-in process step, plasma continuation meeting is bombarded the sidewall 131 of groove pattern 103, oxygen base gas continuation in plasma is reacted with the carbon in the dielectric layer in sidewall 131 regions of groove pattern 103, carbonoxide element, increases the loose part of the sidewall 131 of groove pattern 103, obtains the thickness of the first interlayer 104 of needs.Can as gas flow, pressure, voltage, power etc., control the amount of removing carbon by regulating the technological parameter of plasma dry etch process, the thickness of the first interlayer 104 is controlled.
Then carry out step S03, form filling dielectric 105 in groove pattern 103, filling dielectric 105 separates by the first interlayer 104 with the sidewall 131 of groove pattern 104, sees Fig. 2 c.Adopt conventional method in groove pattern 103, to deposit filling dielectric 105, then through planarization, make filling dielectric 105 equal with dielectric layer 102, in the structure obtaining, filling dielectric 105 separates by the first interlayer 104 with dielectric layer 102.The material of filling dielectric 105 is preferably selected the material identical with dielectric layer 102, but not identical material, as long as the material of filling dielectric 105 is dielectric substance, all within thought range of the present invention.
Carry out subsequently step S04, form some interconnecting channels 106, some interconnecting channels 106 are arranged in dielectric layer 102 or filling dielectric 105, or wherein some are arranged in dielectric layer 102 and other is arranged in filling dielectric 105, and interconnecting channel 106 and the first interlayer 104 are staggered.Preferably, interconnecting channel 106 has the first interlayer 104 each other, and the quantity of interconnecting channel 106 the first interlayer 104 is each other more than or equal to 1.Interconnecting channel 106 is a kind of or combination in raceway groove and through hole, for the interconnection connection of metal.In the present embodiment, adopt conventional lithographic method etching in filling dielectric 105 to form interconnecting channel 106, interconnecting channel 106 both sides have the first interlayer 104, see Fig. 2 d.Owing to being also provided with in the present embodiment etching stop layer 201, so interconnecting channel 106 is through etching stop layer 201, to guarantee that the interconnection of electric conducting material 107 is communicated with.
Then carry out step S05, with electric conducting material 107, fill interconnecting channel 106, this step comprises: in interior metal barrier and the Seed Layer of preparing electric conducting material 107 of interconnecting channel 106, to improve the filling quality of electric conducting material 107; Deposits conductive material 107 is to fill interconnecting channel 106; And planarize conductive material 107 is to expose dielectric layer 102.
Finally carry out step S06, remove the first interlayer 104, with sidewall 131 places at groove pattern 103, form air-gap 108.Adopt conventional wet-etching technology to remove the first interlayer 104, at sidewall 131 places of groove pattern 103, form empty gap, thereby form air-gap 108.Preferably, wet-etching technology adopts the hydrofluoric acid of dilution, and (percentage of dilution 100: 1～1000: 1) does not cause damage to other structure to remove the first interlayer 104.By controlling the degree of depth of groove pattern 103, thereby penetrated or partly through the first interlayer 104 of dielectric layer 102, further can control the degree of depth of air-gap 108, air-gap 108 can penetrate or part is passed dielectric layer 102.Position and the quantity of air-gap 108 in interconnection structure can arrange as required, because the thickness of air-gap 108 can be accomplished nanoscale, so the mechanicalness of the interconnection structure that employing the method obtains is good, because gauge, length dimension, the quantity of air-gap 108 are adjustable, so the dielectric constant of the interconnection structure that employing the method obtains can regulate as required.
The present invention is not limited to above-described embodiment, can increase some steps as between step S01 and step S02, can also be on dielectric layer 102 deposition oxide protective layer and hard mask layer successively, protective oxide film and hard mask layer are for improving the precision of etching and reducing the damage of etching process to dielectric layer 102, to improve the quality of etching, and can in the planarization process in step S03, remove, can also be in carrying out step S04, the position of the some interconnecting channels 106 that form, and the quantity of interconnecting channel 106 the first interlayer 104 each other can be different from above-described embodiment, as interconnecting channel 106 is arranged in dielectric layer 102, or wherein some are arranged in dielectric layer 102 and other is arranged in filling dielectric 105, the quantity of interconnecting channel 106 the first interlayer 104 each other, more than 1, is shown in Fig. 3 a, Fig. 3 b, in addition, the sidewall that can also be included in interconnecting channel 106 in this preparation method's step forms air-gap 108, the step that forms interconnecting channel air-gap 118 at the sidewall of interconnecting channel 106 comprises: when carrying out step S04, remove the dielectric layer of sidewall areas of described interconnecting channel 106 or the carbon in filled media, to form the second loose interlayer on the sidewall at interconnecting channel 106, then carry out step S05, finally carry out S06, when removing described the first interlayer, remove described the second interlayer, with the side-walls at interconnecting channel 106, form interconnecting channel air-gap 118, see Fig. 3 c, can be by the technological parameter of dry etch process in regulating step S04, as gas flow, pressure, voltage, power etc. are controlled the amount of removing carbon, can control the thickness of the second interlayer simultaneously, this while forms the method for air-gap 108 at the sidewall of groove pattern 103 and the sidewall of interconnecting channel 106, in the situation that not increasing processing step, can further increase the quantity of air-gap, reduce the dielectric constant between interconnection structure, improve the reliability of interconnection.
In sum, the invention provides a kind of preparation method of the interconnection structure that contains air-gap, dielectric layer deposition on substrate, the material of described dielectric layer is carbonaceous material, dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, removal is arranged in the carbon of the dielectric layer of described groove pattern sidewall areas, to form the first loose interlayer on the sidewall of described groove pattern, in described groove pattern, form filling dielectric, the sidewall of described filling dielectric and described groove pattern separates by described the first interlayer, after conductive interconnection passage forms, remove described the first interlayer, with the side-walls at described groove pattern, form air-gap, described air-gap has reduced the dielectric constant of dielectric layer, and the gauge of air-gap, length dimension, quantity, arrangement mode and shape are all adjustable, so the mechanicalness of this interconnection structure can be controlled.Compared with prior art, the preparation method of the interconnection structure that contains air-gap provided by the invention has the following advantages:
1, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, then after electric conducting material is filled described interconnecting channel, remove described the first interlayer to form air-gap, described air-gap has reduced the dielectric constant of dielectric layer, reduces RC and postpones.
2, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, then after electric conducting material is filled described interconnecting channel, remove described the first interlayer to form air-gap, so forming the process of air-gap can not exert an influence to interconnecting channel, avoided the conducting of air-gap and interconnecting channel, the reliability that improves interconnection structure is high.
3, the preparation method of the interconnection structure that contains air-gap provided by the invention, first to form the first interlayer before forming interconnecting channel, the thickness of the first interlayer is nanoscale, the gauge of the air-gap forming so remove afterwards described the first interlayer is little, and the gauge of air-gap, length dimension, quantity, arrangement mode and shape are all adjustable, so the mechanicalness of the interconnection structure that employing the method obtains can be controlled.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (15)
1. a preparation method who contains the interconnection structure of air-gap, comprising:
Dielectric layer deposition on substrate, the material of described dielectric layer is carbonaceous material;
Dielectric layer described in selective etch, to form some groove patterns in described dielectric layer, and removes the carbon of the dielectric layer be arranged in described groove pattern sidewall areas, to form the first loose interlayer on the sidewall of described groove pattern;
In described groove pattern, form filling dielectric;
On described substrate, form some interconnecting channels, described some interconnecting channels are arranged at least one of described dielectric layer and described filling dielectric, and described interconnecting channel and described the first interlayer are staggered;
Filled conductive material in described interconnecting channel; And
Remove described the first interlayer, with the side-walls at described groove pattern, form air-gap.
2. the preparation method of the interconnection structure that contains air-gap as claimed in claim 1, it is characterized in that, dielectric layer described in employing dry etch process selective etch, the etching gas of described dry etch process comprises a kind of or combination in fluorine base gas and oxygen base gas.
3. the preparation method of the interconnection structure that contains air-gap as claimed in claim 1, it is characterized in that, in described dielectric layer, form the step of some groove patterns and in described groove pattern, form between the step of filling dielectric, also comprise burin-in process step, continue to remove the carbon of the dielectric layer that is arranged in described groove pattern sidewall areas, to adjust the thickness of described the first interlayer.
4. the preparation method of the interconnection structure that contains air-gap as claimed in claim 3, is characterized in that, the reacting gas of described burin-in process step comprises oxygen base gas.
5. the preparation method of the interconnection structure that contains air-gap as claimed in claim 1, is characterized in that, after removing the step of described the first interlayer, described interconnecting channel has described air-gap each other.
6. the preparation method of the interconnection structure that contains air-gap as claimed in claim 5, is characterized in that, after removing the step of described the first interlayer, the quantity of described adjacent interconnecting channel described air-gap is each other more than or equal to 1.
7. the preparation method of the interconnection structure that contains air-gap as described in any one in claim 1-6, is characterized in that, this preparation method also comprises:
When forming some interconnecting channels on described substrate, remove the dielectric layer of sidewall areas of described interconnecting channel or the carbon in filled media, to form the second loose interlayer on the sidewall of described interconnecting channel;
Filled conductive material in described interconnecting channel; And
When removing described the first interlayer, remove described the second interlayer, with the side-walls at described interconnecting channel, form interconnecting channel air-gap.
8. the preparation method of the interconnection structure that contains air-gap as described in any one in claim 1-6, is characterized in that, on substrate, before dielectric layer deposition step, also comprises: deposition-etch stop-layer on described substrate.
9. the preparation method of the interconnection structure that contains air-gap as described in any one in claim 1-6; it is characterized in that; the step of dielectric layer deposition and forming in described dielectric layer between the step of some groove patterns on substrate, also comprises: deposition oxide protective layer and hard mask layer successively on described dielectric layer.
10. the preparation method of the interconnection structure that contains air-gap as described in any one in claim 1-6, is characterized in that, the low-dielectric material that the material of described dielectric layer is carbon containing.
The preparation method of 11. interconnection structures that contain air-gap as described in any one in claim 1-6, is characterized in that, the material of described filling dielectric is identical with the material of described dielectric layer.
The preparation method of 12. interconnection structures that contain air-gap as described in any one in claim 1-6, is characterized in that, described interconnecting channel is a kind of or combination in raceway groove and through hole.
The preparation method of 13. interconnection structures that contain air-gap as described in any one in claim 1-6, is characterized in that, describedly by the step that electric conducting material is filled described interconnecting channel, comprises:
Metal barrier and the Seed Layer of in described interconnecting channel, preparing described electric conducting material;
Deposit described electric conducting material to fill described interconnecting channel; And
Described in planarization, electric conducting material is to expose described dielectric layer.
The preparation method of 14. interconnection structures that contain air-gap as described in any one in claim 1-6, is characterized in that, adopts wet-etching technology to remove described the first interlayer.
The preparation method of 15. interconnection structures that contain air-gap as claimed in claim 14, is characterized in that, the etching liquid of described wet-etching technology comprises hydrofluoric acid.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826279A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| US11587977B2 (en) | 2016-02-22 | 2023-02-21 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
Families Citing this family (1)
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| US12165967B2 (en) | 2021-02-03 | 2024-12-10 | Changxin Memory Technologies, Inc. | Interconnection structure and manufacturing method thereof and semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028575A1 (en) * | 2000-09-01 | 2002-03-07 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
| US20050179140A1 (en) * | 2002-11-21 | 2005-08-18 | Goodner Michael D. | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
| US20060177990A1 (en) * | 2003-09-30 | 2006-08-10 | Interuniversitair Microelektronica Centrum (Imec Vzw) | Methods for selective integration of airgaps and devices made by such methods |
| CN101231969A (en) * | 2007-01-26 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method for forming integrated circuit structure |
| CN101589459A (en) * | 2007-01-26 | 2009-11-25 | 应用材料股份有限公司 | Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild |
-
2012
- 2012-07-02 CN CN201210225939.9A patent/CN103531524B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028575A1 (en) * | 2000-09-01 | 2002-03-07 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
| US20050179140A1 (en) * | 2002-11-21 | 2005-08-18 | Goodner Michael D. | Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide |
| US20060177990A1 (en) * | 2003-09-30 | 2006-08-10 | Interuniversitair Microelektronica Centrum (Imec Vzw) | Methods for selective integration of airgaps and devices made by such methods |
| CN101231969A (en) * | 2007-01-26 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method for forming integrated circuit structure |
| CN101589459A (en) * | 2007-01-26 | 2009-11-25 | 应用材料股份有限公司 | Uv curing of pecvd-deposited sacrificial polymer films for air-gap ild |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826279A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN105826279B (en) * | 2015-01-06 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US11587977B2 (en) | 2016-02-22 | 2023-02-21 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
| US11770938B2 (en) | 2016-02-22 | 2023-09-26 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
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