CN103516179B - Switching Regulator Control Circuit with Multiple Clock Signal Frequency Setting Modes - Google Patents

Abstract

One of the control circuits of the switching regulator provided in this patent includes: the control pin is used for being coupled with an external resistor; the resistance detector is used for detecting the resistance value of the external resistor when the control pin is coupled with the external resistor; the current generation module is used for generating corresponding control current according to the detection result of the resistance detector; the oscillator is coupled to the control pin and the current generation module and used for generating a clock pulse signal; and a mode switching circuit. When the mode switching circuit sets the oscillator to operate in the resistance control mode, the oscillator generates a clock signal according to the control current, so that the frequency of the clock signal corresponds to the resistance value of the external resistor. When the mode switching circuit sets the oscillator to operate in the signal control mode, the oscillator generates a clock signal according to an external synchronization signal coupled to the control pin, so that the clock signal is synchronized with the external synchronization signal. The control circuit only needs to be provided with a single control pin, and two different clock signal frequency setting modes can be provided.

Description

Switching Regulator Control Circuit with Multiple Clock Signal Frequency Setting Modes

technical field

The present invention relates to a control circuit of a switching voltage stabilizer, especially a control circuit with multiple clock signal frequency setting modes.

Background technique

The control circuit of some switching regulators will set a frequency setting pin and a synchronization signal pin at the same time. The signal pin is used to receive an external synchronous signal for the control circuit to set the internal clock signal to be synchronous with the external synchronous signal.

Although arranging two pins on the control circuit can provide a higher selection flexibility for the frequency setting method of the clock signal of the control circuit, it needs to occupy more chip packaging area. If the chip packaging area of the control circuit of the switching regulator can be further reduced, it is obviously necessary to further reduce the number of pins of the control circuit.

Contents of the invention

In view of this, how to effectively reduce the number of pins of the control circuit of the switching regulator without affecting the selection flexibility of the frequency setting method of the internal clock signal of the control circuit is a problem to be solved in the industry.

The present invention provides an embodiment of a control circuit for a switching regulator, which includes: a control pin for coupling an external resistor; a resistance detector coupled to the control pin , for detecting the resistance value of the external resistor when the control pin is coupled to the external resistor; a current generating module, coupled to the resistance detector, for detecting according to the resistance detector The test result generates a corresponding control current; an oscillator, coupled to the control pin and the current generation module, is used to generate a clock signal; and a mode switching circuit, coupled to the control pin and the current generation module. An oscillator; wherein when the mode switching circuit sets the oscillator to operate in a resistance control mode, the oscillator generates the clock signal according to the control current, so that the frequency of the clock signal corresponds to the resistance value of the external resistor , and when the mode switching circuit sets the oscillator to operate in a signal control mode, the oscillator will generate the clock signal according to an external synchronization signal coupled to the control pin, so that the clock signal is synchronized with the external synchronization signal.

One of the advantages of the above control circuit is that the mode switching circuit can automatically detect whether an external synchronization signal is coupled to the control pin, and switch the operation mode of the oscillator accordingly.

Another advantage of the above control circuit is that it only needs to set a single control pin to provide two different clock signal frequency setting methods, which not only endows the control circuit with higher flexibility in use, but also effectively simplifies the required chips package area.

Another advantage of the above-mentioned control circuit is that it can effectively prevent the operation mode of the oscillator from being incorrectly switched by the mode switching circuit due to noise on the control pin.

Description of drawings

FIG. 1 is a simplified functional block diagram of an embodiment of the power converter of the present invention.

FIG. 2 is a simplified functional block diagram of an embodiment of the control circuit in FIG. 1 .

3 to 4 are simplified timing diagrams of different operation embodiments of the control circuit in FIG. 2 .

FIG. 5 is a simplified functional block diagram of another embodiment of the control circuit in FIG. 1 .

FIG. 6 is a simplified timing diagram of an operation embodiment of the control circuit in FIG. 5 .

detailed description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar elements or processes/steps.

Certain terms are used in the specification and following claims to refer to particular elements. It should be understood by those skilled in the art that the same element may be referred to by different names. This description and the subsequent claims do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. "Includes" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to...". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that a first element is coupled to a second element, it means that the first element can be directly (including through electrical connection or wireless transmission, optical transmission and other signal connection methods) connected to the second element, or It is indirectly electrically or signally connected to the second element through other elements or connection means.

The description of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in this specification, any singular term also includes plural meanings.

FIG. 1 is a simplified functional block diagram of a power converter 100 according to an embodiment of the present invention. The power converter 100 includes a control circuit 110 , a switching regulator 120 , a resistor 130 , an external switch 140 , and a switch controller 150 . The control circuit 110 is coupled to the switching regulator 120 for controlling the switching regulator 120 to stabilize the input voltage so as to provide the operating voltage required by the subsequent circuit. The resistor 130 and the switch 140 are coupled to the control circuit 110 , and the switch controller 150 is coupled to the switch 140 for controlling the operation of the switch 140 . During operation, the power converter 100 can use the switch controller 150 to determine whether to couple the external synchronization signal EXT to the control circuit 110 to change the way the control circuit 110 generates the clock signal CLK. When the switch controller 150 turns off the switch 140 , the frequency of the clock signal CLK generated by the control circuit 110 depends on the resistance value of the external resistor 130 . When the switch controller 150 turns on the switch 140 to couple the external synchronization signal EXT to the control circuit 110 , the control circuit 110 will synchronize the clock signal CLK with the external synchronization signal EXT.

In this embodiment, the control circuit 110 includes a control pin (control pin) 111, a resistance detector 112, a current generating module 113, an oscillator 114, a mode-switching circuit (mode-switching circuit) 115, and a pulse width modulation inverter (PWM modulator) 116 . The control pin 111 is used for coupling the external resistor 130 and the external switch 140 . The resistance detector 112 is coupled to the control pin 111 for detecting the resistance value of the resistor 130 when the control pin 111 is coupled to the resistor 130 . The current generation module 113 is coupled to the resistance detector 112 for generating a corresponding control current Iosc according to the detection result of the resistance detector 112 . The oscillator 114 is coupled to the control pin 111 and the current generating module 113 for generating the clock signal CLK. The mode switching circuit 115 is coupled to the control pin 111 and the oscillator 114 for switching the oscillator 114 between a resistor-controlled mode and a signal-controlled mode. The pulse width modulator 116 is coupled to the oscillator 114 for generating a pulse width modulation signal PWM according to the clock signal CLK output by the oscillator 114 to control the switching frequency of the switching regulator 120 .

When the mode switching circuit 115 sets the oscillator 114 to operate in the resistance control mode, the oscillator 114 generates the clock signal CLK according to the control current Iosc, so that the frequency of the clock signal CLK corresponds to the resistance value of the external resistor 130 . When the mode switching circuit 115 sets the oscillator 114 to operate in the signal control mode, the oscillator 114 generates the clock signal CLK according to the external synchronization signal EXT, so that the clock signal CLK is synchronized with the external synchronization signal EXT.

In practice, different functional blocks in the control circuit 110 can be integrated into a single circuit chip, or implemented with different circuit chips. For example, the pulse width modulator 116 in the control circuit 110 can be separated and implemented as an independent circuit chip, and other functional blocks in the control circuit 110 can be integrated in another circuit chip.

FIG. 2 is a simplified functional block diagram of an embodiment of the control circuit 110 in FIG. 1 . In this embodiment, the resistance detector 112 includes a first comparator 223 , a transistor 225 , and a first switch 227 . The transistor 225 and the switch 227 are coupled between the current generating module 113 and the control pin 111 . The output terminal of the comparator 223 is coupled to the control terminal of the transistor 225 , and the input terminal of the comparator 223 is coupled to the control pin 111 and the first reference voltage Vf1 . The comparator 223 is used to compare the voltage VP on the control pin 111 with the first reference voltage Vf1, and control the sense current Ir flowing through the transistor 225 according to the comparison result. The mode switching circuit 115 is coupled to the control end of the switch 227 for controlling switching of the switch 227 .

The oscillator 114 in this embodiment includes a first capacitor 241 , a second switch 243 , a second comparator 245 , and a combinational logic circuit 247 . The switch 243 is coupled between the capacitor 241 and the current generating module 113 , and the control terminal of the switch 243 is coupled to the mode switching circuit 115 . The switch 243 is used for selectively conducting the control current Iosc to the capacitor 241 according to the control of the mode switching circuit 115 . The comparator 245 is coupled to the capacitor 241 and the second reference voltage Vf2 for comparing the voltage across the capacitor 241 with the second reference voltage Vf2 to generate a comparison signal CMP. The combinational logic circuit 247 is coupled to the control pin 111 , the mode switching circuit 115 , the pulse width modulator 116 , and the comparator 245 , and is used to determine the generation mode of the clock signal CLK according to the control of the mode switching circuit 115 .

In the embodiment of FIG. 2 , the mode switching circuit 115 includes a sync signal detector (sync signal detector) 251 and an in-phase signal generator (in-phase signal) 253 . The synchronous signal detector 251 is coupled to the control pin 111, the resistance detector 112, and the oscillator 114, and is used for detecting the voltage VP on the control pin 111, and controlling the resistance detector 112 and the oscillator 114 operate. The in-phase signal generator 253 is coupled to the synchronous signal detector 251 and the oscillator 114 for generating the in-phase signal WS with the same phase as the clock signal CLK according to the clock signal CLK output by the oscillator 114 . For example, the in-phase signal generator 253 can generate a corresponding pulse wave with a narrower pulse width as the in-phase signal WS each time the rising edge of the clock signal CLK is triggered.

The operation of the control circuit 110 will be further described below with reference to FIGS. 3-4 .

FIG. 3 is a simplified timing diagram 300 of an operational embodiment of the control circuit 110 in FIG. 2 . As shown in FIG. 3 , when the switch controller 150 sets the control signal CS to a low level to turn off the switch 140 , for example, in a period before time T1 , the external synchronization signal EXT is not coupled to the control pin 111 . At this moment, the voltage VP on the control pin 111 is equal to the reference voltage Vf1 of the comparator 223 . In this phase, the synchronous signal detector 251 in the mode switching circuit 115 sets the oscillator 114 to operate in the resistance control mode, and sets the control signal RCM to a high level to turn on the switch 227 . At this time, the comparator 223 , the transistor 225 and the switch 227 form a negative feedback path, so that the magnitude of the induced current Ir flowing through the transistor 225 is inversely proportional to the resistance of the external resistor 130 .

Therefore, the resistance detector 112 can be used to detect the resistance value of the external resistor 130 to determine the corresponding induced current Ir. The current generation module 113 generates a control current Iosc corresponding to the magnitude of the current Ir flowing through the transistor 225 . Since the magnitude of the current Ir corresponds to the resistance of the external resistor 130 , the magnitude of the control current Iosc also corresponds to the resistance of the external resistor 130 .

In practice, the current generating module 113 can be realized by current mirror circuits of various structures, and is used to copy the current Ir to generate the control current Iosc which is the same or proportional to the current Ir. For example, in the embodiment of FIG. 3 , the current generating module 113 includes transistors 231 , 233 , and a second capacitor 235 . The first end of the transistor 231 is coupled to the first end of the transistor 233 and is coupled to a fixed potential VCC. The second terminal and the control terminal of the transistor 231 are coupled to the resistance detector 112 . The control terminal of the transistor 233 is coupled to the control terminal of the transistor 231 to form a current mirror structure for replicating the current Ir flowing through the resistance detector 112 to the second terminal of the transistor 233 to generate the control current Iosc. One terminal of the capacitor 235 is coupled to the first terminal of the transistor 231 , and the other terminal of the capacitor 235 is coupled to the control terminals of both the transistors 231 and 233 .

When the synchronous signal detector 251 in the mode switching circuit 115 sets the oscillator 114 to operate in the resistance control mode, the synchronous signal detector 251 will set the control signal SCM to a low potential to turn on the oscillator 114 The switch 243 conducts the control current Iosc to the capacitor 241 in the oscillator 114 . At this time, the synchronous signal detector 251 also uses the control signal SCM to set the combinational logic circuit 247 in the oscillator 114 to generate the clock signal CLK according to the comparison signal CMP output by the comparator 245, so that the clock signal CLK The frequency will correspond to the magnitude of the control current Iosc. Since the control current Iosc corresponds to the resistance of the external resistor 130 , the frequency of the clock signal CLK generated by the combinational logic circuit 247 depends on the resistance of the external resistor 130 .

In order to automatically switch the generation mode of the clock signal CLK, the synchronous signal detector 251 in the mode switching circuit 115 detects the change of the voltage VP on the control pin 111 . Once the voltage VP deviates from a predetermined range, for example, from the range of Vt1-Vt2, the synchronous signal detector 251 will monitor the voltage VP for a period of time to further determine whether the change of the voltage VP is caused by the external synchronous signal EXT being coupled. Received to the control pin 111, it is still caused by noise.

In the embodiment of FIG. 3, when the switch controller 150 switches the control signal CS to a high potential at time T1 to couple the external synchronization signal EXT to the control pin 111 through the switch 140, the voltage VP on the control pin 111 It will rise under the influence of the waveform of the external synchronization signal EXT and begin to show periodic changes. When the synchronous signal detector 251 detects that the voltage VP on the control pin 111 exceeds the preset upper limit Vt1 at time T1, it will enter an observation period (observation period), and monitor whether the voltage VP begins to appear periodic high and low potentials Transition.

When the synchronous signal detector 251 is in the observation period, in order to prevent the change of the voltage VP on the control pin 111 from affecting the stability of the control current Iosc generated by the current generating module 113, the synchronous signal detector 251 can enter During the observation period (that is, when it is detected that the voltage VP deviates from the predetermined range), the control signal RCM is switched to a low potential to turn off the switch 227 . At this time, the control current Iosc can be kept constant by discharging the capacitor 235 . In this way, the frequency of the clock signal CLK output by the oscillator 114 can be maintained at the same level or close to that when the oscillator 114 operates in the resistance control mode.

The synchronous signal detector 251 can determine that the external synchronous signal EXT is coupled to the control pin 111 when detecting one or more periodic high-to-low level transitions of the voltage VP. For example, the synchronous signal detector 251 in this embodiment will determine that the external synchronous signal EXT is coupled to the control pin 111 when it detects that the voltage VP has 4 high-to-low transitions. When the phases of the square wave of the voltage VP and the in-phase signal WS generated by the in-phase signal generator 253 are the same or the difference is smaller than a threshold value, the synchronization signal detector 251 will leave the observation period. In practice, the synchronization signal detector 251 can determine that the phases of the two are the same when the rising edges of the square wave of the voltage VP and the in-phase signal WS are aligned, or when the rising edges of the square wave of the voltage VP fall on When the pulse width of the in-phase signal WS is within the range, the phase difference between the square wave of the dispatch voltage VP and the in-phase signal WS is smaller than a critical value.

In the embodiment of FIG. 3 , when the synchronization signal detector 251 detects that the rising edges of the square wave of the voltage VP and the in-phase signal WS are aligned at time T2 , the observation period will be left. When the synchronization signal detector 251 leaves the observation period, it will switch the oscillator 114 to the signal control mode. As shown in the timing diagram 300, the synchronous signal detector 251 will switch the control signal SCM to a high potential at this time, so as to set the combinational logic circuit 247 in the oscillator 114 to generate a synchronous clock signal according to the external synchronous signal EXT CLK, and stop generating the clock signal CLK according to the output of the comparator 245, so that the clock signal CLK generated by the oscillator 114 in the signal control mode will be synchronized with the external synchronization signal EXT.

When the synchronous signal detector 251 switches the oscillator 114 to the signal control mode, the synchronous signal detector 251 can use the control signal SCM to turn off the switch 243 in the oscillator 114, so that the control current Iosc stops conducting into the oscillator 114 The capacitor 241 is used to save the current consumption of the oscillator 114 and the control circuit 110 in the signal control mode. In addition, the in-phase signal generator 253 in the mode switching circuit 115 can also generate the in-phase signal WS only when the synchronization signal detector 251 is in the observation period, so as to further improve the power saving effect of the control circuit 110 .

FIG. 4 is a simplified timing diagram 400 of another operational embodiment of the control circuit 110 in FIG. 2 . The embodiment of FIG. 4 is very similar to the embodiment of FIG. 3 , the difference is that when the switch controller 150 switches the control signal CS to a high potential at time T3 to couple the external synchronization signal EXT to the control pin 111 through the switch 140, The voltage VP on the control pin 111 will drop under the influence of the waveform of the external synchronous signal EXT and begin to show periodic changes.

When the synchronous signal detector 251 in the mode switching circuit 115 detects that the voltage VP on the control pin 111 exceeds the preset lower limit Vt2 at time T3, it will enter the observation period and monitor whether the voltage VP begins to periodically rise and fall. Potential conversion.

When the synchronous signal detector 251 in this embodiment detects the fifth periodic high-to-low transition of the voltage VP at time T4 , it will determine that the external synchronous signal EXT is coupled to the control pin 111 . When the phases of the square wave of the voltage VP and the in-phase signal WS generated by the in-phase signal generator 253 are the same (for example, when the rising edges of the two are aligned) or the difference is less than a threshold value, the synchronous signal detector 251 will leave the observation period.

In the embodiment of FIG. 4 , when the synchronous signal detector 251 detects at time T5 that the rising edge of the square wave of the voltage VP falls within the pulse width range of the in-phase signal WS, the observation period will be left.

Other descriptions about the operation of the control circuit 110 in the above-mentioned embodiments are also applicable to the embodiment of FIG. 4 , so they will not be repeated here.

In some embodiments, the in-phase signal generator 253 in the mode switching circuit 115 can also be omitted. In these embodiments, after the synchronization signal detector 251 detects that the voltage VP on the control pin 111 deviates from a predetermined range and enters an observation period, the synchronization signal detector 251 may detect that the voltage VP appears for one or more times. During the sub-periodic high-low potential transition, it is determined that the external synchronous signal EXT is coupled to the control pin 111 . At this point, the synchronization signal detector 251 can leave the observation period without waiting for the edges of the square wave of the voltage VP to be aligned with the in-phase signal WS generated by the in-phase signal generator 253 .

In the aforementioned embodiment of FIG. 2, the transistor 225 in the resistance detector 112 is arranged on the current path between the current generating module 113 and the control pin 111, and the switch 227 is arranged between the transistor 225 and the control pin 111. on the current path between pins 111. But this is just an example, not an actual implementation of the localized resistance detector 112 . In practice, the switch 227 can also be arranged on the current path between the current generating module 113 and the transistor 225 . In addition, the number of switches in the resistance detector 112 can also be increased according to the needs of the circuit design, and is not limited to the number in the embodiment shown in FIG. 2 .

The method of setting the observation period by the mode switching circuit 115 can be adjusted according to the requirements of the circuit design, and is not limited to the method of the foregoing embodiments. For example, the mode switching circuit 115 may set the observation period to a fixed time length.

FIG. 5 is a simplified functional block diagram of another embodiment of the control circuit 110 in FIG. 1 . The control circuit 110 in FIG. 5 is very similar to the control circuit 110 in FIG. 2 . One of the differences between the two embodiments is that the current generating module 113 in FIG. 5 further includes a bias circuit 537 , but the capacitor 235 is omitted. The bias circuit 537 is coupled to the control terminal of the transistor 233 and the mode switching circuit 115 , and is used for selectively applying a predetermined bias voltage to the control terminal of the transistor 233 according to the control of the mode switching circuit 115 .

The mode switching circuit 115 in FIG. 5 further includes a notification signal generator 555, coupled to the control pin 111 and the synchronous signal detector 251, for detecting the square wave period of the voltage VP on the control pin 111, and When the notification signal generator 555 detects that the period of the square wave of the voltage VP exceeds a predetermined length, it generates a corresponding notification signal Tout to the synchronization signal detector 251 .

When the synchronization signal detector 251 in the mode switching circuit 115 sets the oscillator 114 to operate in the signal control mode, the notification signal generator 555 will record the individual time lengths of a plurality of square wave cycles of the voltage VP, and the synchronization signal detection The detector 251 switches the control signal SCM to a high potential to control the bias circuit 537 to start applying a predetermined bias voltage to the control terminal of the transistor 233 .

The operation of the control circuit 110 in FIG. 5 will be further described below with reference to FIG. 6 .

As shown in FIG. 6 , after the switch controller 150 sets the control signal CS to a low level at time T6 to turn off the switch 140 , the external synchronous signal EXT stops being coupled to the control pin 111 . When the notification signal generator 555 detects that the length of a square wave cycle of the voltage VP is longer than the previous square wave cycle at time T7 , it generates a notification signal Tout to notify the synchronization signal detector 251 .

When receiving the notification signal Tout, the synchronization signal detector 251 will enter the observation period, and switch the control signal SCM to a low potential to turn on the switch 243 in the oscillator 114, and the combinational logic circuit in the oscillator 114 247 is configured to generate the clock signal CLK according to the comparison signal CMP output by the comparator 245 . At this time, the control current Iosc is conducted to the capacitor 241 in the oscillator 114 , and the magnitude of the control current Iosc is determined by the bias voltage applied by the bias circuit 537 to the control terminal of the transistor 233 . Therefore, the frequency of the clock signal CLK output by the oscillator 114 also depends on the bias voltage applied by the bias circuit 537 to the control terminal of the transistor 233 .

If the voltage VP falls within a predetermined range continuously for more than a predetermined number of cycles of the clock signal CLK, the sync signal detector 251 can determine that the external sync signal EXT has stopped being coupled to the control pin 111 .

For example, in the embodiment shown in FIG. 6 , when the synchronous signal detector 251 detects that the voltage VP continuously falls within the voltage range Vp1˜Vp2 for more than two periods of the clock signal CLK, for example, at time T8, It is determined that the external synchronization signal EXT has been decoupled from the control pin 111 . At this time, as shown in the timing diagram 600 , the sync signal detector 251 leaves the observation period and switches the oscillator 114 to the resistance control mode. At the same time, the synchronous signal detector 251 will switch the control signal RCM to a high potential to control the bias circuit 537 to stop applying bias voltage to the control terminal of the transistor 233, and turn on the switch 227 in the resistance detector 112, so that the resistance detector 112 The detector 112 starts to detect the resistance value of the external resistor 130 to determine the magnitude of the current Ir and the control current Iosc.

In the embodiment of FIG. 6, since the oscillator 114 has already started to operate when the synchronization signal detector 251 enters the observation period (that is, time T7), so when the synchronization signal detector 251 leaves the observation period (that is, time T7) T8 ), the oscillator 114 can quickly reach a steady state operation, so that the frequency of the clock signal CLK output by the oscillator 114 will correspond to the resistance value of the external resistor 130 .

As mentioned above, the synchronous signal detector 251 will control the bias voltage circuit 537 to apply a predetermined bias voltage to the control terminal of the transistor 233 when the oscillator 114 operates in the signal control mode until the oscillator 114 is switched to the resistance control mode. only to stop. In addition, by using the bias circuit 537 to apply a predetermined bias voltage to the control terminal of the transistor 233, the frequency of the clock signal CLK generated during the switching of the oscillator 114 from the signal control mode to the resistance control mode can also be kept stable. This avoids malfunctioning of the pulse width modulator 116 affecting the subsequent stage.

In the embodiment of FIG. 6 , the bias voltage applied by the bias circuit 537 to the control terminal of the transistor 233 will cause the control current Iosc received by the oscillator 114 when it is initially switched to the resistance control mode to be slightly higher than the oscillation 114 reaches the size at which it operates in steady state. In practice, the bias voltage applied by the bias circuit 537 to the control terminal of the transistor 233 can also be designed so that the control current Iosc received by the oscillator 114 when it is initially switched to the resistance control mode is slightly lower than that of the oscillator 114. 114 to reach the size of steady-state operation.

The description about the operation of the control circuit 110 in FIG. 2 when the oscillator 114 is switched from the resistance control mode to the signal control mode is also applicable to the embodiment of FIG. 5 , so it will not be repeated here. In practice, the synchronous signal detector 251 can also control the bias circuit 537 to apply a predetermined bias voltage to the control terminal of the transistor 233 during the observation period when the oscillator 114 is switched from the resistance control mode to the signal control mode, so as to The frequency of the clock signal CLK generated during the switching of the oscillator 114 from the resistance control mode to the signal control mode can be kept stable, so as to avoid malfunctioning of the subsequent pulse width modulator 116 .

In the foregoing description, the notification signal generator 555 will send the notification signal Tout to the synchronous signal detector 251 as long as it detects that the length of a certain square wave cycle of the voltage VP is longer than the previous square wave cycle. This is just an example, and does not limit the actual implementation of the notification signal generator 555 . For example, the notification signal generator 555 may also detect that the length of a certain square wave cycle of the voltage VP is longer than the previous square wave cycle by a predetermined degree, for example, when it is multiple times longer than the previous square wave cycle. Send the notification signal Tout to the sync signal detector 251 . Alternatively, the notification signal generator 555 can also send the notification signal Tout to the synchronous signal detector 251 when it detects that the length of a certain square wave period of the voltage VP exceeds the acceptable limit of the design specification of the control circuit 110 .

In the foregoing embodiments, the control signals of some functional blocks such as the switch 140, the switch 227, and the bias circuit 537 are expressed in the form of active high, while the control signals of some functional blocks such as the switch 243 are represented by The form of active low (active low) is only for the convenience of illustration, and does not limit the actual implementation of the control signals of these functional blocks.

In addition, the current mirror architecture used to implement the current generating module 113 in the foregoing embodiments is only one of many ways to generate the control current Iosc, rather than limiting the actual implementation of the current generating module 113 . In practice, more transistors can also be used to form current mirrors with different architectures, so as to realize the function of the aforementioned current generating module 113 .

It can be seen from the foregoing description that even if the switch controller 150 does not actively notify the control circuit 110 when switching the external switch 140, the mode switching circuit 115 in the aforementioned control circuit 110 will automatically detect whether there is an external synchronization signal EXT coupled to the control lead. pin 111, and switch the operating mode of the oscillator 114 accordingly. Therefore, the control circuit 110 proposed in this case only needs to set a single control pin 111 to provide two different clock signal frequency setting methods, which not only endows the control circuit 110 with higher flexibility in use, but also effectively simplifies the required chip package area.

In addition, when the oscillator 114 operates in the signal control mode, the combinational logic circuit 247 is used to generate the synchronous clock signal CLK directly according to the external synchronous signal EXT, instead of using a phase-locked loop (PLL) or a delay-locked loop (DLL). ) and the like feedback control architecture to lock the external synchronization signal EXT. Therefore, when the mode switch circuit 115 switches the oscillator 114 to the signal control mode, the oscillator 114 can quickly synchronize the clock signal CLK with the external synchronization signal EXT, and achieve better power saving effect. Moreover, the circuit area required by the aforementioned oscillator 114 is much smaller than that of a clock generator implemented by using a phase-locked loop or a delay-locked loop, which is more conducive to reducing the circuit area required by the control circuit 110 .

Furthermore, since the aforementioned mode switching circuit 115 enters the observation period to further monitor the variation of the voltage VP when the voltage VP on the control pin 111 deviates from the predetermined range, and only when it detects that the voltage VP appears one or The mode switching circuit will determine that the external synchronous signal EXT is coupled to the control pin 111 when there are multiple periodic high-low potential transitions. Therefore, it is possible to effectively prevent the mode switching circuit 115 from erroneously switching the operation mode of the oscillator 114 due to the noise on the control pin 111 .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (19)

1., for a control circuit for switching type voltage stabilizer, it includes:

One controls pin, is used for coupling a non-essential resistance；

One resistance detector, is coupled to this control pin, for being coupled to this external electrical at this control pin During resistance, detect the resistance value of this non-essential resistance；

One electric current produces module, is coupled to this resistance detector, for the detecting according to this resistance detector Result produces a corresponding control electric current；

One agitator, is coupled to this control pin and this electric current produces module, for producing a clock signal； And

One mode switching circuit, is coupled to this control pin and this agitator；

Wherein when this mode switching circuit arranges this oscillator operation in a resistance control model, this vibration Device can produce this clock signal according to this control electric current, makes the frequency of this clock signal corresponding to this external electrical The resistance value of resistance, and when this mode switching circuit arranges this oscillator operation in a control pattern signal, This agitator can produce this clock signal according to the outer synchronous signal that this control pin is coupled, and makes this Clock signal is synchronized with this outer synchronous signal；

Wherein this agitator includes:

One first electric capacity；

One second switch, is coupled to this first electric capacity and this electric current produces between module, for according to this mould The control of formula switching circuit, optionally by this control current lead-through to this first electric capacity；

One second comparator, is coupled to this first electric capacity and one second reference voltage, for by this first electricity The cross-pressure held compares with this second reference voltage, to produce a comparison signal；And

One combinational logic circuit, is coupled to this control pin, this mode switching circuit and this second ratio Relatively device, for the control according to this mode switching circuit, produces this clock signal.

2. control circuit as claimed in claim 1, wherein controls in this resistance when this oscillator operation During pattern, this mode switching circuit can be coupled to this outer synchronous signal at this control pin and reach a period of time After, this agitator is switched to this control pattern signal.

3. control circuit as claimed in claim 2, wherein controls in this signal when this oscillator operation During pattern, this mode switching circuit can stop being coupled to this outer synchronous signal at this control pin and reach one section After time, this agitator is switched to this resistance control model.

4. control circuit as claimed in claim 3, wherein this resistance detector includes:

One first comparator, is coupled to this control pin and one first reference voltage, for this control being drawn Voltage on foot compares with this first reference voltage；

One transistor, coupled in series produces between module and this control pin in this electric current, and this transistor The end that controls be coupled to an outfan of this first comparator；And

One first switch, coupled in series produces between module and this control pin in this electric current, and is arranged at On current path between this control pin of this transistor AND gate, or being arranged at this electric current produces module and is somebody's turn to do On current path between transistor；

Wherein before this control pin is coupled to this outer synchronous signal, this mode switching circuit can turn on this First switch, and when the change in voltage on this control pin is more than a preset range, this pattern switching electricity This first switch can be ended in road.

5. control circuit as claimed in claim 4, wherein this transistor is arranged at this electric current and produces mould On current path between group and this control pin.

6. control circuit as claimed in claim 5, wherein this electric current produces this control that module produces Electric current is identical with the faradic current size flowing through this transistor or proportional relation.

7. control circuit as claimed in claim 3, wherein this electric current generation module includes:

One current mirror, includes multiple transistor；And

One bias circuit, is coupled to this mode switching circuit, for the control according to this mode switching circuit, The control end of one of them transistor of this current mirror is applied a predetermined bias.

8. control circuit as claimed in claim 7, wherein when this mode switching circuit is by this agitator Being arranged to operate when this control pattern signal, this mode switching circuit can control this bias circuit to this electricity The control end of one of them transistor of stream mirror applies a predetermined bias.

9. control circuit as claimed in claim 8, wherein at this mode switching circuit by this agitator A scheduled time slot from this resistance control mode switch to this control pattern signal, this pattern switching electricity It is predetermined partially to the control end applying one of one of them transistor of this current mirror that road can control this bias circuit Pressure.

10. control circuit as claimed in claim 9, wherein this electric current generation module has additionally comprised:

One second electric capacity, is coupled to the control end of one of them transistor of this current mirror.

11. control circuits as claimed in claim 1, wherein when this mode switching circuit is by this agitator When being arranged to operate in this resistance control model, this mode switching circuit can turn on this second switch, and will This combinational logic circuit is arranged to according to this comparison signal to produce this clock signal.

12. control circuits as claimed in claim 1, wherein when this mode switching circuit is by this agitator When being arranged to operate in this control pattern signal, this mode switching circuit can end this second switch, and will This combinational logic circuit is arranged to according to this outer synchronous signal to produce this clock signal.

13. control circuits as claimed in claim 3, wherein this mode switching circuit includes:

One synchronous signal detection device, is coupled to this control pin, this resistance detector and this agitator, For detecting the voltage on this control pin, and control the running of this resistance detector and this agitator.

14. control circuits as claimed in claim 13, wherein this synchronous signal detection device can be in detecting When the conversion of the most periodic high electronegative potential occurs in voltage on this control pin, by this agitator Switch to this control pattern signal.

15. control circuits as claimed in claim 13, wherein this mode switching circuit has additionally comprised:

One in-phase signal generator, is coupled to this synchronous signal detection device and this agitator, for according to being somebody's turn to do Clock signal produces an in-phase signal identical with this clock signal phase place；

Wherein can there is week one or more times in the voltage detected on this control pin in this synchronous signal detection device The high electronegative potential conversion of phase property, and the phase of the square wave of the voltage on this control pin and this in-phase signal When position is identical or gap is less than a marginal value, this agitator is switched to this control pattern signal.

16. control circuits as claimed in claim 15, wherein this mode switching circuit has additionally comprised:

One notification signal generator, is coupled to this control pin and this synchronous signal detection device, is used for detecting The square-wave cycle of the voltage on this control pin, and the square-wave cycle of the voltage on this control pin exceedes During one predetermined length, produce the notification signal of a correspondence to this synchronous signal detection device；

Wherein when this synchronous signal detection device receives this notification signal, this agitator can be switched to this electricity Resistance control model.

17. control circuits as claimed in claim 13, wherein this mode switching circuit has additionally comprised:

One notification signal generator, is coupled to this control pin and this synchronous signal detection device, is used for detecting The square-wave cycle of the voltage on this control pin, and the square-wave cycle of the voltage on this control pin exceedes During one predetermined length, produce the notification signal of a correspondence to this synchronous signal detection device；

Wherein when this synchronous signal detection device receives this notification signal, this agitator can be switched to this electricity Resistance control model.

18. 1 kinds of control circuits for switching type voltage stabilizer, it includes:

One controls pin, is used for coupling a non-essential resistance；

One resistance detector, is coupled to this control pin, for being coupled to this external electrical at this control pin During resistance, detect the resistance value of this non-essential resistance；

One electric current produces module, is coupled to this resistance detector, for the detecting according to this resistance detector Result produces a corresponding control electric current；

One agitator, is coupled to this control pin and this electric current produces module, for producing a clock signal； And

One mode switching circuit, is coupled to this control pin and this agitator；

Wherein when this mode switching circuit arranges this oscillator operation in a resistance control model, this vibration Device can produce this clock signal according to this control electric current, makes the frequency of this clock signal corresponding to this external electrical The resistance value of resistance, and when this mode switching circuit arranges this oscillator operation in a control pattern signal, This agitator can produce this clock signal according to the outer synchronous signal that this control pin is coupled, and makes this Clock signal is synchronized with this outer synchronous signal；

Wherein when this oscillator operation is in this resistance control model, this mode switching circuit can be in this control Pin is coupled to after this outer synchronous signal reaches a period of time, this agitator switch to this signal and controls mould Formula；

Wherein when this oscillator operation is in this control pattern signal, this mode switching circuit can be in this control Pin stops being coupled to after this outer synchronous signal reaches a period of time, this agitator switching to this resistance control Molding formula；

Wherein this resistance detector includes:

One first comparator, is coupled to this control pin and one first reference voltage, for this control being drawn Voltage on foot compares with this first reference voltage；

One transistor, coupled in series produces between module and this control pin in this electric current, and this transistor The end that controls be coupled to an outfan of this first comparator；And

One first switch, coupled in series produces between module and this control pin in this electric current, and is arranged at On current path between this control pin of this transistor AND gate, or being arranged at this electric current produces module and is somebody's turn to do On current path between transistor；

Wherein before this control pin is coupled to this outer synchronous signal, this mode switching circuit can turn on this First switch, and when the change in voltage on this control pin is more than a preset range, this pattern switching electricity This first switch can be ended in road.

19. 1 kinds of control circuits for switching type voltage stabilizer, it includes:

One controls pin, is used for coupling a non-essential resistance；

One resistance detector, is coupled to this control pin, for being coupled to this external electrical at this control pin During resistance, detect the resistance value of this non-essential resistance；

One electric current produces module, is coupled to this resistance detector, for the detecting according to this resistance detector Result produces a corresponding control electric current；

One agitator, is coupled to this control pin and this electric current produces module, for producing a clock signal； And

One mode switching circuit, is coupled to this control pin and this agitator；

Wherein when this mode switching circuit arranges this oscillator operation in a resistance control model, this vibration Device can produce this clock signal according to this control electric current, makes the frequency of this clock signal corresponding to this external electrical The resistance value of resistance, and when this mode switching circuit arranges this oscillator operation in a control pattern signal, This agitator can produce this clock signal according to the outer synchronous signal that this control pin is coupled, and makes this Clock signal is synchronized with this outer synchronous signal；

Wherein when this oscillator operation is in this resistance control model, this mode switching circuit can be in this control Pin is coupled to after this outer synchronous signal reaches a period of time, this agitator switch to this signal and controls mould Formula；

Wherein when this oscillator operation is in this control pattern signal, this mode switching circuit can be in this control Pin stops being coupled to after this outer synchronous signal reaches a period of time, this agitator switching to this resistance control Molding formula；

Wherein this mode switching circuit includes:

One synchronous signal detection device, is coupled to this control pin, this resistance detector and this agitator, For detecting the voltage on this control pin, and control the running of this resistance detector and this agitator；With And

One in-phase signal generator, is coupled to this synchronous signal detection device and this agitator, for according to being somebody's turn to do Clock signal produces an in-phase signal identical with this clock signal phase place；

Wherein can there is week one or more times in the voltage detected on this control pin in this synchronous signal detection device The high electronegative potential conversion of phase property, and the phase of the square wave of the voltage on this control pin and this in-phase signal When position is identical or gap is less than a marginal value, this agitator is switched to this control pattern signal.