CN103500708B - A kind of graphic method reducing bonding cavity - Google Patents

Abstract

The invention relates to semiconductor device manufacturing technology, in particular to a patterning method for reducing bonding voids. The invention solves the problems that bonding voids and excessive thermal stress are easily produced in the existing chip bonding technology. A patterning method for reducing bonding voids, which is realized by the following steps: (1) selecting a GaAs substrate; growing an N-GaAs layer on the GaAs substrate; growing a quantum well layer on the N-GaAs layer; Grow a P-GaP layer on the quantum well layer; (2) Make a current diffusion layer on the P-GaP layer; (3) Make an ohmic contact layer on the current diffusion layer; (4) Use photolithography on the ohmic contact layer Make graphics; (5) select the substrate; make a material bonding layer on the substrate; (6) make a material reflection layer on the material bonding layer; (7) bond the material reflection layer and the ohmic contact layer; (8) The GaAs substrate is removed by chemical etching. The invention is applicable to the manufacture of semiconductor devices.

Description

A Graphical Approach to Reducing Bonding Voiding

technical field

The invention relates to semiconductor device manufacturing technology, in particular to a patterning method for reducing bonding voids.

Background technique

Continuously optimizing the parameters and structures of semiconductor devices to obtain better performance of semiconductor devices has always been the goal pursued by the field of semiconductor devices. Semiconductor devices are usually made of a variety of semiconductor materials, so only by combining the excellent characteristics of various semiconductor materials can semiconductor devices achieve better performance. At present, when a semiconductor device is manufactured using a variety of semiconductor materials with lattice matching, the semiconductor device is mainly manufactured by epitaxial growth on a substrate. However, when using various semiconductor materials with high lattice mismatch and large differences in thermal expansion coefficients to manufacture semiconductor devices, wafer bonding is mainly used to manufacture semiconductor devices. Under the current technical conditions, wafer bonding mainly includes three steps: surface treatment, pre-bonding, and annealing. The quality of these three links is directly related to the performance of semiconductor devices. Practice has shown that the existing wafer bonding technology has the following problems due to its own principle limitations: First, in the surface treatment process, due to the presence of particles and fluctuations on the wafer surface, it is easy to cause bonding voids at the bonding interface, and the bonding voids directly Affect the quality of bonding, thereby affecting the performance of semiconductor devices. Second, in the pre-bonding process, due to the large difference in thermal expansion coefficient between the chips, it is easy to cause excessive thermal stress between the chips, and the concentration of the thermal stress will further lead to thermal stress cracks at the bonding interface. Stress cracks will destroy the integrity of the bonding interface, thereby directly affecting the quality of bonding, thereby affecting the performance of semiconductor devices. Third, in the annealing process, due to the high bonding temperature, the residual water on the surface of the wafer is likely to evaporate and form bubbles. The bubbles cannot escape the bonding interface smoothly, which further leads to bonding voids at the bonding interface. The bonding voids directly Affect the quality of bonding, thereby affecting the performance of semiconductor devices. Based on this, it is necessary to invent a brand-new wafer bonding technology to solve the problems of bonding voids and excessive thermal stress in the existing wafer bonding technology.

Contents of the invention

The invention provides a patterning method for reducing bonding voids in order to solve the problems that bonding voids and excessive thermal stress are easily produced in the existing wafer bonding technology.

The present invention is realized by adopting the following technical scheme: a patterning method for reducing bonding voids, which is realized by adopting the following steps: (1) selecting a GaAs substrate; growing an N-GaAs layer on the GaAs substrate; Grow a quantum well layer on the N-GaAs layer; grow a P-GaP layer on the quantum well layer; (2) make a current diffusion layer on the P-GaP layer; (3) make an ohmic contact layer on the current diffusion layer; (4) ) using photolithography to make graphics on the ohmic contact layer; (5) selecting the substrate; making a material bonding layer on the substrate; (6) making a material reflection layer on the material bonding layer; (7) combining the material reflection layer with Ohmic contact layer for bonding; (8) Remove the GaAs substrate by chemical etching.

Compared with the existing wafer bonding technology, a patterning method for reducing bonding voids described in the present invention has the following advantages by making a pattern on the bonding interface: First, in the surface treatment process, the pattern on the one hand It effectively prevents bonding voids at the bonding interface, and on the other hand, makes the surface of the wafer form dangling bonds, which is beneficial to the formation of a chemical bonding network at the bonding interface, thus effectively ensuring the quality of bonding and thus ensuring the performance of semiconductor devices. Second, in the pre-bonding process, the pattern effectively prevents excessive thermal stress between the chips, that is, effectively prevents thermal stress cracks at the bonding interface, thereby effectively ensuring the quality of the bonding, thereby ensuring the semiconductor device performance. Third, in the annealing process, this pattern effectively prevents the residual moisture on the wafer surface from evaporating and forming bubbles, that is, effectively prevents bonding voids from forming on the bonding interface, thereby effectively ensuring the quality of bonding, thereby ensuring the reliability of the semiconductor device. performance. In summary, a patterning method for reducing bonding voids described in the present invention effectively solves the problems of bonding voids and excessive thermal stress in the existing wafer bonding technology, thereby effectively ensuring the reliability of bonding. quality, thereby ensuring the performance of semiconductor devices.

The invention effectively solves the problems that bonding voids and excessive thermal stress are easily produced in the existing wafer bonding technology, and is suitable for the manufacture of semiconductor devices.

Description of drawings

FIG. 1 is a schematic diagram of a patterning method for reducing bonding voids according to the present invention.

FIG. 2 is a schematic diagram of steps (1)-(4) of a patterning method for reducing bonding voids according to the present invention.

detailed description

A graphical method for reducing bond voids is achieved using the following steps:

(1) Select GaAs substrate; grow N-GaAs layer on GaAs substrate; grow quantum well layer on N-GaAs layer; grow P-GaP layer on quantum well layer;

(2) Fabricate a current diffusion layer on the P-GaP layer;

(3) Make an ohmic contact layer on the current diffusion layer;

(4) Make patterns on the ohmic contact layer by photolithography;

(5) Select the substrate; make a material bonding layer on the substrate;

(6) Make a material reflective layer on the material bonding layer;

(7) Bond the reflective layer of the material with the ohmic contact layer;

(8) Remove the GaAs substrate by chemical etching.

In the steps (2) and (3), the material of the current diffusion layer is ITO, and the thickness of the current diffusion layer is 1000-3000Å.

In the steps (3), (4) and (7), the material of the ohmic contact layer is Au/AuBe/Au, and the thickness of the ohmic contact layer is 5000-10000Å.

In the step (4), the shape of the pattern is striped, the width of the pattern is 100-200 μm, and the pitch of the pattern is 10-30 μm. The steps of the photolithography method are: coating photoresist, exposure, development, etching , to glue.

In the steps (5) and (6), the material of the material bonding layer is Pt and/or Ti.

In the steps (6) and (7), the material of the reflective layer is Au.

In the step (7), the bonding temperature is 200-350° C., and the bonding time is 50-250 ms.

In the step (4), after the graphics are made, the alloy annealing treatment is carried out _{on the ohmic contact layer with N 2 .} It is 5-10L.

Claims (1)

1. reduce the graphic method in bonding cavity, it is characterized in that: the method adopts following steps to realize:

(1) GaAs substrate is chosen; Grow N-GaAs layer on gaas substrates; Grown quantum well layer on N-GaAs layer; Quantum well layer grows P-GaP layer;

(2) on P-GaP layer, current-diffusion layer is made;

(3) on current-diffusion layer, ohmic contact layer is made;

(4) photoetching process is adopted to make figure on ohmic contact layer;

(5) substrate is chosen; Substrate makes material binds layer;

(6) on material binds layer, material reflects layer is made;

(7) material reflects layer and ohmic contact layer are carried out bonding;

(8) chemical corrosion method is adopted to remove GaAs substrate;

In described step (2), (3), the material of current-diffusion layer is ITO, and the thickness of current-diffusion layer is 1000-3000;

In described step (3), (4), (7), the material of ohmic contact layer is Au/AuBe/Au, and the thickness of ohmic contact layer is 15000-25000;

In described step (4), the shape of figure is bar shaped, and the width of figure is 100-200 μm, and the spacing of figure is 10-30 μm, and photolithographic step is followed successively by: resist coating, exposure, development, and etching, removes photoresist;

In described step (5), (6), the material of material binds layer is Pt and/or Ti;

In described step (6), (7), the material of material reflects layer is Au;

In described step (7), the temperature of bonding is 200-350 DEG C, and the time of bonding is 50-250ms;

In described step (4), after making figure, adopt N ₂carry out alloy annealing in process to ohmic contact layer, the temperature of alloy annealing in process is 380-480 DEG C, and the time of alloy annealing in process is 10-30min, N ₂flow be 5-10L.