CN103477423A - Encapsulation method for embedding chip into substrate and structure thereof - Google Patents
Encapsulation method for embedding chip into substrate and structure thereof Download PDFInfo
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- CN103477423A CN103477423A CN2011800701044A CN201180070104A CN103477423A CN 103477423 A CN103477423 A CN 103477423A CN 2011800701044 A CN2011800701044 A CN 2011800701044A CN 201180070104 A CN201180070104 A CN 201180070104A CN 103477423 A CN103477423 A CN 103477423A
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- contact surface
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- base plate
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- 239000000758 substrate Substances 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 72
- 238000005538 encapsulation Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 62
- 239000002184 metal Substances 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 54
- 238000012856 packing Methods 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 239000011889 copper foil Substances 0.000 claims description 14
- 238000003475 lamination Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims 2
- 239000010949 copper Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 14
- 238000004544 sputter deposition Methods 0.000 description 12
- 230000009977 dual effect Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 10
- 238000007747 plating Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000003801 milling Methods 0.000 description 8
- 238000011161 development Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000003780 insertion Methods 0.000 description 5
- 230000037431 insertion Effects 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 239000004643 cyanate ester Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Provided are an encapsulation method for embedding a chip into a substrate and a structure thereof. The method includes: providing at least one chip embedding part inside a substrate, the chip embedding part being a through-hole and/or a recess, the number of chip embedding parts being equal to that of the chip (107) to be encapsulated, the depth of the chip embedding part matched with the thickness of the chip (107) to be encapsulated; embedding the chip (107) into the chip embedding part; wiring on a first contact face and/or a second contact face of the chip (107), and wiring correspondingly on the substrate to form a wiring layer, so that the substrate and the chip (107) are electrically connected to each other.
Description
Chip buried method for packing and its technical field of structures
The present invention relates to the method for packing and its structure in chip package field, more particularly to a kind of chip buried base plate.
Background technology
With the development of information-intensive society, the information processing capacity of various electronic equipments constantly increases, and the demand for high frequency, high speed transmission of signals is growing.Semiconductor chip is embedded to package substrate, because it can effectively shorten the connection distance of semiconductor and package substrate, strong guarantee can be provided for high frequency, high speed transmission of signals, while a chip buried base plate can meet the growth requirement of encapsulating structure high integration and electronic product miniaturization.
In semiconductor package equipped with the special chip of a class, such as metal oxide semiconductor field effect tube
(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), the active device such as diode (diode) and transistor, with single or double connecting structure for electrical equipment, and variety classes active device has different thickness.
By the semiconductor buried base plate of different-thickness, the need for insulating properties, it is required that during the variable thickness sample of the thickness of substrate and a chip, because the processing procedures such as silk-screen printing need, it need to ensure that chip at least one side and substrate are coplanar, ensure that chip single or double and substrate have good electrical connection simultaneously, prior art is generally realized by way of lamination, very big pressure is needed during lamination, laser drill, the heavy process such as copper and plating is needed to realize electrical connection simultaneously, the integrity to a chip brings very big risk.
The content of the invention
The embodiments of the invention provide the method for packing of chip buried base plate and its structure, for solving the problems, such as electrical connection during chip overall package between chip and the coplanarity and chip contact surface and lower sandwich circuit of substrate, chip package reliability is improved.
A kind of method for packing of the chip buried base plate provided according to one embodiment of the invention, the chip has the first contact surface and the second contact surface, comprises the following steps：
Step S1:At least one chip buried portion is set in the substrate, the chip buried portion is through hole and/or groove, and the number in the chip buried portion is identical with the number of required encapsulation chip, and the depth in the chip buried portion is matched with the chip thickness of required encapsulation；
Step S2:By the chip buried chip buried portion；
Step S3:Connected up in the first contact surface of chip and/or the second contact surface, and correspondence wiring on substrate, form wiring layer so that be electrically connected between the substrate and the chip.
A kind of encapsulating structure of the chip buried base plate provided according to further embodiment of this invention, the encapsulating structure of the chip buried base plate includes substrate, chip and wiring layer,
The substrate is provided with least one chip buried portion, and the chip has the first contact surface and the second contact surface, and the chip buried portion is through hole and/or groove, the thickness matching of the depth in the chip buried portion and the chip of corresponding embedment,
The wiring layer includes being laid in the wiring of the contact surface of chip first and/or the second contact surface, and the wiring of the correspondence chip and lay be used to realize the wiring being electrically connected between the chip and substrate on substrate.
As can be seen from the above technical solutions, the embodiment of the present invention has advantages below：
(1) the different chip of thickness is placed by the different groove of depth, and the depth of groove is matched with the chip thickness of required embedment, it is ensured that the chip package of different-thickness enters keeps coplanar after the substrate；
(2) the different pad set-up modes for setting pad or two sides to be designed with pad according to chip one side select different connected modes to be electrically connected chip so that packaging technology has good autgmentability, strong applicability.
Brief description of the drawings
Fig. 1 is the method for packing schematic flow sheet of the chip buried base plate of the embodiment of the present invention one；Fig. 2 a to Fig. 2 g are the process schematic diagrames of the method for packing application example one of the chip buried base plate of the embodiment of the present invention one；
Fig. 3 a to Fig. 3 g are the process schematic diagrames of the method for packing application example two of the chip buried base plate of the embodiment of the present invention one；
Fig. 4 a to Fig. 4 h are the process schematic diagrames of method for packing application example three of the chip buried base plate of the embodiment of the present invention one；
Fig. 5 is the method for packing application example four steps schematic diagram of the chip buried base plate of the embodiment of the present invention one；
Fig. 6 is the method for packing schematic flow sheet of the chip buried base plate of the embodiment of the present invention two；Fig. 7 a to Fig. 7 c are the method for packing application example process schematic diagrames of the chip buried base plate of the embodiment of the present invention two；
Fig. 8 is the method for packing schematic flow sheet of the chip buried base plate of the embodiment of the present invention three；
Fig. 9 a to Fig. 9 d are the method for packing application example process schematic diagrames of the chip buried base plate of the embodiment of the present invention three；
Figure 10 is the encapsulating structure schematic diagram of the chip buried base plate of the embodiment of the present invention four；
Figure 11 is the encapsulating structure schematic diagram of the chip buried base plate of the embodiment of the present invention five；
Figure 12 is the encapsulating structure schematic diagram of the chip buried base plate of the embodiment of the present invention six.
Embodiment
The embodiments of the invention provide the method for packing of chip buried base plate and its structure, the high frequency and high-speed transfer of electric signal are realized in coplanarity and electrical connection for solving the problems, such as chip package chips and substrate.The implementation process of the present invention is described in detail below with reference to specific embodiment, some more common technology means are not described in detail to those skilled in the art, to avoid causing the limitation unnecessary to the present invention.
Embodiment one
With reference to Fig. 1, the method for packing schematic flow sheet of the present embodiment chip buried base plate is shown, a kind of method for packing of chip buried base plate, its chips have the first contact surface and the second contact surface, comprised the following steps：
S101, at least one chip buried portion is set in substrate, and chip buried portion is through hole and/or groove, and the number in chip buried portion is identical with the number of required encapsulation chip, and the depth in chip buried portion is matched with the chip thickness of required encapsulation；
5102, by chip buried portion；
5103, connected up in the first contact surface of chip and/or the second contact surface, and correspondence wiring on substrate, form wiring layer so that electrically connect between substrate and chip.
Be through hole and/or groove for chip buried portion, in different Application Examples, at least one chip buried portion can all be groove or through hole, can also groove and through hole have.Wherein substrate can be single sided board, dual platen or the multi-layer sheet for having processed internal layer circuit, and in order to more intuitively state process in embodiment, process is described in detail by taking dual platen as an example.
The concrete application example to chip buried base plate method for packing is described in more detail below, it is to be understood that the mode in following examples in each step can be used in combination.
With reference to Fig. 2 a to Fig. 2 g, the process schematic diagram encapsulated to one single chip is shown, its process is as follows：
Fig. 2 a, selection one has the substrate of the first metal layer 101, dielectric layer 100 and second metal layer 102, and substrate is opened into a groove from the first metal layer 101 to dielectric layer 100；
Wherein the first metal layer 101 and second metal layer 102 of substrate are that copper clad layers, i.e. substrate are copper-clad base plate, and aluminium or other metals can also be selected according to the requirement of practical application.
Dielectric layer 100 is insulating materials, can be epoxy resin（Epoxy Resin), cyanate（Cyanate Ester), glass fibre（Glass Fiber), polyimides（Polyimide), the mixture of Bismaleimide Triazine (Bismaleimide Triazine, BT) or more insulating materials, or other dielectrics.
The manufacture craft of groove uses controlled depth milling, so-called controlled depth milling is exactly a kind of milling machine technology for the depth for controlling Z-direction, due to being limited by milling machine Z directions controlled depth milling precision, in order to ensure the integrity of 102 layers of second metal layer, can also use milling machine milling to one insurance depth after, reuse laser ablation and grill thoroughly dielectric layer.The depth of groove is matched with the chip thickness of required embedment, the length of groove, the size of the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold.The shape of groove can for rule cuboid, or for prismatoid, or stepped, can be designed, be not limited herein according to actual technological requirement, in order to more intuitively state in Figure of description, the unified shape that groove is expressed as to cuboid.
Fig. 2 b, groove floor is coated on by non-conductive binding material, forms tack coat 103;
When such a coating method of tack coat 103 is contacted suitable for chip with groove floor, first contact surface of chip does not have the situation of pad, non-conductive binding material can be coated by steel mesh printing or point gum machine mode for dispensing glue, being adhered to by tack coat between the chip of substrate recess and substrate has bigger adhesive force so that the reliability of connection is higher.
Fig. 2 c, bonding is docked by the contact surface of chip 107 first with tack coat 103 so that chip 107 is embedded to groove；
By the step for, complete the step of chip 107 is preliminary to be fixed on the groove of substrate.
Fig. 2 d, coat photosensitive material on the first metal layer 101 and the contact surface of chip second, form photosensitive material coat 108;
The hole 109 of Fig. 2 e, groove and chip surrounding can also insert photosensitive material or is filled using other insulation filling materials；
By the filling to groove and chip surrounding hole the fixed effect between chip and substrate can be made more preferable.Fig. 2 f, the gap of the pad on the contact surface of chip second is stopped；
Expose, develop and solidify by photosensitive material coat 108, the gap of the pad on the contact surface of chip second is stopped, and stop the part that the need of the first metal layer 101 retain copper face.
Fig. 2 g, wiring is set in the first contact surface of chip and the second contact surface, and correspondence is set on substrate
Wiring is put, wiring layer is formed.
The technologies such as sputtering or heavy copper, plating, exposure, development, etching can be passed through, in the second contact surface of chip, wiring is set, and wiring is set in substrate the first metal layer 101 corresponding with the second contact surface, form wiring layer, simultaneously, set and connect up in tack coat 103, and wiring is set in substrate second metal layer 102 corresponding with tack coat 103, form wiring layer.Now, the making of dual platen has been completed, if necessary to increasing layer, and lamination or Layer increasing method just can be taken to continue to make multilayer line.
The situation for also having pad on the first contact surface for chip is described following two application examples.Also there is the electrical connection being also required on pad, the first contact surface with substrate on first contact surface, therefore can not be using non-conductive binding material directly is coated on into groove floor in application example one, the mode for forming tack coat is bonded to chip.
With reference to Fig. 3 a to Fig. 3 g, the process schematic diagram of the another application example of method for packing of the chip buried base plate of embodiment is shown, is comprised the following steps：
Fig. 3 a, selection one has the substrate of the first metal layer 101, dielectric layer 100 and second metal layer 102, and the groove from the insertion of the first metal layer 101 to dielectric layer 100 is opened up on substrate；
The depth of groove is matched with the chip thickness of required embedment, when the substrate need to be embedded with multiple thickness different chip, ensure that the chip package of different-thickness enters and keep coplanar after the substrate, the size of the length of groove, the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold.
First contact surface of chip has pad, the bottom surface of groove is communicated with second metal layer 102, i.e. groove insertion the first metal layer 101 and dielectric layer 100, arrive at second metal layer 102, can more easily realize the electrical connection of the first contact surface and substrate of follow-up chip.Certainly, when the first contact surface of chip has pad, the bottom surface of groove can not be also abutted to second metal layer 204, and the electrical connection of the contact surface of chip first and substrate is realized by using the mode of metal guide through hole.
Fig. 3 b, solder joint 104 is formed by conductive bonding material in the bottom surface of groove;
Silk-screen printing or point gum machine mode for dispensing glue can be used to form solder joint 104 in the bottom surface of groove in this step.
Fig. 3 c, dock bonding so that chip 107 is fixedly arranged on groove by the contact surface of chip 107 first with solder joint 104；
Fig. 3 d, coat photosensitive material on the first metal layer 101 and the contact surface of chip 107 second, form photosensitive material coat 108;
The hole 109 of Fig. 3 e, groove and the surrounding of chip 107 can also insert photosensitive material or using other
Insulation filling material is filled so that chip 107 is preferably fixed on the groove of substrate；Fig. 3 f, the gap between the pad on the contact surface of chip 107 second is stopped；
Expose, develop and solidify by photosensitive material coat 108 in this step and stop the gap between pad on the contact surface of chip second.
Fig. 3 g, by technologies such as sputtering or heavy copper, plating, etchings, wiring is set in the first contact surface of chip and/or the second contact surface, and wiring is correspondingly arranged on substrate, forms wiring layer.
The first contact surface and the second contact surface of the present embodiment chips 107 have pad, the technologies such as sputtering or heavy copper, plating, exposure, development, etching can be passed through, in the first contact surface of chip and the second contact surface, wiring is set, and the wiring for setting the corresponding wiring with chip to be connected on substrate, realize the electrical connection of chip and substrate.Now, the making of dual platen has been completed, and if necessary to increasing layer, just can take technology or Layer increasing method continuation making multilayer line that tradition is laminated.
With reference to Fig. 4 a to Fig. 4 h, the process schematic diagram of the another application example of method for packing of the chip buried base plate of embodiment is shown, is comprised the following steps：
Fig. 4 a, substrate of the selection with the first metal layer 101, dielectric layer 100 and second metal layer 102, open up the groove from the first metal layer 101 to dielectric layer 100 on substrate；
The depth of groove is matched with the chip thickness of required embedment, when substrate need to be embedded to the chip of multiple different-thickness, ensure different-thickness chip package enter it is coplanar after the groove of the substrate, the size of the length of groove, the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold.
First contact surface of chip has pad, and the bottom surface of groove is communicated with second metal layer 102, i.e. groove insertion the first metal layer 101 and dielectric layer 100, conveniently can subsequently realize the electrical connection of the contact surface of chip first and substrate.Certainly, when the first contact surface of chip has pad, the bottom surface of groove can not also be communicated with second metal layer 204, subsequently through the electrical connection that the contact surface of chip first and substrate are realized by the way of metal guide through hole.
Fig. 4 b, corresponding pit 105 is got in groove floor;
Pit 105 can be formed by laser drill technique or etching technique in groove floor.
Fig. 4 c, are implanted into conductive bonding material on tin ball or point in pit 105, form solder joint 106;
The present embodiment forms by the way of solder joint 106 contact area of the bonding for realizing follow-up chip 107 and solder joint 106, increase second metal layer 102 and solder joint 106 in the pit 105, and the bond effect of chip 107 and solder joint 106 is more preferable.
Fig. 4 d, dock bonding, so that chip 107 by the contact surface of chip 107 first with solder joint 106
It is embedded to groove；
Fig. 4 e, coat photosensitive material on the first metal layer 101 and the contact surface of chip second, form photosensitive material coat 108;
The hole 109 of Fig. 4 f, groove and chip surrounding can also insert photosensitive material or is filled using other insulation filling materials；
Fig. 4 g, the gap of the pad on the contact surface of chip second is stopped, and stops the part that the need of the first metal layer 101 retain copper face, is completed by processes such as photosensitive layer exposure, development and solidifications；Fig. 4 h, by technologies such as sputtering or heavy copper, plating, etchings, wiring is set in the first contact surface of chip and/or the second contact surface, and wiring is correspondingly arranged on substrate, forms wiring layer so that chip is electrically connected with substrate.
The first contact surface and the second contact surface of the present embodiment chips have pad, the technologies such as sputtering or heavy copper, plating, exposure, development, etching can be passed through, in the first contact surface of chip and the second contact surface, wiring is set, and the wiring for setting the corresponding wiring with chip to be connected on substrate, wiring layer is formed, the electrical connection of chip and substrate is realized.Now, the making of dual platen has been completed, if necessary to increasing layer, and lamination or Layer increasing method just can be taken to continue to make multilayer line.
With reference to Fig. 5, the process schematic diagram of the another application example of method for packing of the chip buried base plate of embodiment is shown, multiple chips for encapsulating different-thickness comprise the following steps：
Fig. 5 show the sectional view in the A-A faces of substrate 200, and substrate 200 is outputed into the different chip number identical grooves 201 with required encapsulation of depth from the first metal layer 203 to dielectric layer 202；
Groove is carved using controlled depth milling technique, the depth of groove is matched with the chip thickness of required embedment, the coplanarity of chip front side when can ensure to be embedded to multiple chips, the length of groove, the size of the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold.
When first contact surface of chip does not have pad, the bottom surface of groove communicates with second metal layer 204 or not communicated with second metal layer 204；When first contact surface of chip has pad, the bottom surface of groove is communicated with second metal layer 204, it can ensure that the first contact surface of chip easily forms electrical connection, certainly, when first contact surface of chip has pad, the bottom surface of groove can not also be communicated with second metal layer 204, but the electrical connection of the contact surface of chip first and substrate is realized by the way of metal guide through hole.
Because of the implementation process of following steps process ibid application example, therefore the schematic diagram of following steps is not provided, including：
First contact surface of the chip with the first contact surface and the second contact surface is connected with the first metal layer
The corresponding groove of the corresponding embedment of mode；
This step is identical with above-mentioned application examples, according to actual process demand, groove floor can be taken to coat non-conductive binding material, directly in groove floor formation solder joint or first corresponding pit is got in groove floor and re-form the mode of solder joint chip and substrate are bonded.
The technologies such as sputtering or heavy copper, plating, exposure, development, etching can be passed through, in the first contact surface of chip and the second contact surface, wiring layer is set, and the wiring layer for setting the corresponding wiring layer with chip to be connected on substrate, the electrical connection of chip and substrate is realized, wiring layer is constituted by sputtering Ti/Cu, deposition Cu, plating Cu or other conducting metals.
Embodiment two
With reference to Fig. 6, the schematic flow sheet of the another embodiment of method for packing of chip buried base plate is shown, chip has the first contact surface and the second contact surface, comprised the following steps：
S601, at least one through hole is opened by substrate, and the number of through hole is identical with the number of required encapsulation chip, through hole through substrate；
Wherein, substrate can be single sided board, dual platen or multi-layer sheet.
S602, takes thick copper foil to etch and is distributed consistent convex portion with lead to the hole site；
5603, substrate and thick copper foil are subjected to lamination connection by insulating medium layer, through hole forms groove with convex portion, the depth of groove is matched with the chip thickness of required embedment, when the substrate need to be embedded with multiple different-thickness chips, keep coplanar for ensureing the chip package of different-thickness to enter after the substrate；
5604, by chip buried groove；
S605, wiring is set in the first contact surface of chip and/or the second contact surface, and wiring is correspondingly arranged on substrate, forms wiring layer so that be electrically connected between substrate and chip.
The concrete application example of the present embodiment is described in more detail below in conjunction with Fig. 7 a to Fig. 7 e.
With reference to Fig. 7 a to Fig. 7 c, process encapsulation step schematic diagram is shown, a kind of method for packing for chip buried base plate that the present embodiment is provided, multiple chips for encapsulating different-thickness comprise the following steps：Fig. 7 a, the chip number identical through hole 301 with required encapsulation, through hole insertion the first metal layer 303, dielectric layer 302 and second metal layer 304 are outputed by substrate 300;Fig. 7 b, take thick copper foil 305 to etch and are distributed consistent convex portion with lead to the hole site；Wherein the height of convex portion is designed according to the thickness of chip, the height of convex portion and chip thickness into
Inversely prroportional relationship.Fig. 7 c, carry out lamination connection, through hole 301 forms groove with convex portion by substrate 300 and thick copper foil 305 by insulating medium layer 306；The depth of groove is matched with the chip thickness of required embedment, when the substrate need to be embedded with multiple thickness different chip, ensure that the chip package of different-thickness enters and keep coplanar after the substrate, the size of the length of groove, the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold.First contact surface of the chip with the first contact surface and the second contact surface is connected with the first metal layer, groove corresponding with chip is embedded to；Set in the first contact surface of chip and the second contact surface, and be correspondingly arranged to form wiring layer on substrate, the electrical connection for realizing substrate and chip.
Above-mentioned two step is identical with the embodiment of aforementioned applications example, so not illustrating, according to actual process demand, groove floor can be taken to coat non-conductive binding material, directly in groove floor formation solder joint or first corresponding pit is got in groove floor and re-form the mode of solder joint chip and substrate are bonded, further according to needing to realize the electrical connection between substrate and chip.The Fig. 8 of embodiment three show the schematic flow sheet of the another embodiment of method for packing of chip buried base plate, and chip has the first contact surface and the second contact surface, comprised the following steps：
5801, substrate is opened at least one through hole, the number of through hole is identical with the number of required encapsulation chip；
5802, face coats one layer of photosensitive material where second metal layer, forms photosensitive material layer；
5803, the second contact surface of chip is connected with photosensitive material layer so that chip buried through hole；
5804, binding material will be inserted in the gap of chip and through hole presence, for fixed chip；
5805, remove photosensitive material layer；
5806, print electrocondution slurry in the first contact surface；
5807, in the first contact surface of chip and/or the second contact surface, wiring is set, and on substrate
Wiring is correspondingly arranged, wiring layer is formed so that is electrically connected between the substrate and the chip.Above-mentioned steps are further described below in conjunction with Fig. 9 a to Fig. 9 d, it show the concrete application example process steps step schematic diagram of the another embodiment of method for packing of chip buried base plate, a kind of method for packing for chip buried base plate that the present embodiment is provided, comprises the following steps：Fig. 9 a, substrate 400 outputs the chip number identical through hole 401 with required encapsulation, through hole
401 insertion the first metal layers 403, dielectric layer 402 and second metal layer 404;
Fig. 9 b, are bonded one layer of UV film 405, UV films are a kind of membranaceous materials with bonding effect, and viscosity is lost after UV light irradiations in the place face of second metal layer 404；
Fig. 9 c, the second contact surface of chip 406 and UV films 405 are bonded；
Pass through the bonding between the second contact surface of coplanar UV films and different-thickness chip, it is ensured that the coplanarity of different-thickness chip.
Fig. 9 d, will insert binding material in the gap between chip 406 and through hole 401, filling bonding material layer 407 be formed, for fixed chip 406;Bonding material layer 407 is photosensitive resin or other binding materials, and the thermal conductivity of binding material or heat conduction are non-conductive, depending on being needed according to electrical connection.
Bonding material layer 407 is filled with after the fixation of chip 406, removing UV films 405;
Photosensitive resin is printed in the contact surface of chip second；Set in the first contact surface of chip and/or the second contact surface, and be correspondingly arranged to form wiring layer on substrate so that be electrically connected between substrate and chip.
The step identical with above-mentioned Application Example, will not be repeated here in above process.The encapsulating structure of chip buried base plate described further below.
A kind of encapsulating structure of chip buried base plate includes substrate, chip and wiring layer, substrate is provided with least one chip buried portion, chip has the first contact surface and the second contact surface, chip buried portion is through hole or groove, the thickness matching of the depth in chip buried portion and the chip of corresponding embedment, wiring layer includes being laid in the wiring of the contact surface of chip first and/or the second contact surface, and the wiring of correspondence chip and lay be used to realize the wiring being electrically connected between chip and substrate on substrate.
Be through hole and/or groove for chip buried portion, in different Application Examples, at least one chip buried portion can all be groove or through hole, can also groove and through hole have.Wherein substrate can be single sided board, dual platen or the multi-layer sheet for having processed internal layer circuit, and in order to more intuitively state in embodiment, chip buried base plate encapsulating structure is described in detail by taking dual platen as an example.The concrete application example to chip buried base plate encapsulating structure is described in more detail below, it is to be understood that corresponding each structure can be used in combination in following examples.Example IV refers to Figure 10, show the structural representation of the embodiment of encapsulating structure one of chip buried base plate, a kind of encapsulating structure of chip buried base plate, including：Substrate, with the first metal layer 101, dielectric layer 100 and second metal layer 102;
Groove, slots from the first metal layer 101 of substrate to dielectric layer 100 and is formed；The depth of groove is matched with the chip thickness of required embedment, it is ensured that chip coplanarity when being embedded to multiple chips, the length of groove, the size of the both greater than required embedment chip of width, so that groove can be large enough to hold the chip of required embedment.Chip 107, with the first contact surface and the second contact surface, the first contact surface of chip is connected with groove floor by the solder joint 103 for being arranged at groove floor, chip is tentatively embedded to groove, in order that the fixed effect for obtaining chip and groove is more preferable, the hole 109 of groove and chip surrounding is inserted photosensitive material or is filled using other insulation filling materials；
Wiring layer, sets wiring, and wiring formation is correspondingly arranged on substrate so that be electrically connected between substrate and chip in the first contact surface of chip and the second contact surface.Then the making of build-up circuit is carried out, insulating medium layer 110, line layer 111 is generated by sputtering copper or deposition copper, electro-coppering etc., or can also be made up of other conducting metals.The structure of the another embodiment of the encapsulating structure of the chip buried base plate of embodiment five includes：Substrate；At least one groove of substrate is opened in, the depth of groove is matched with the chip thickness of required embedment, when substrate need to be embedded to the chip of multiple different-thickness, it is ensured that the chip package of different-thickness enters this
It is coplanar after the groove of substrate, the length of groove, the size of the both greater than required embedment chip of width, so that the chip that groove is embedded to needed for being large enough to hold；At least one chip, chip has the first contact surface and the second contact surface, and chip is embedded in corresponding groove；Wiring layer, sets wiring, and wiring formation is correspondingly arranged on substrate so that be electrically connected between substrate and chip in the first contact surface of chip and/or the second contact surface.Substrate can be single sided board, dual platen or multi-panel, when the contact surface of chip first does not have pad, using non-conductive binding material in groove floor formation tack coat, be connected the first contact surface and groove floor by tack coat.When the contact surface of chip second has pad, in the second contact surface pad using conductive bonding material formation solder joint corresponding with pad, the first contact surface and groove floor are connected by solder joint, or etch pit corresponding with the second contact surface pad in second metal layer, conductive bonding material formation solder joint on tin ball or point is implanted into pit again, the second contact surface and groove floor are connected by solder joint, then connecting wiring layer and the second contact surface solder joint by way of metal blind hole.As shown in figure 11, chip buried base plate encapsulating structure includes：Substrate, it further comprises insulating barrier 300, the circuit 301 of second metal layer formation, the first metal layer is laminated after dielectric or the dielectric 303 being coated with other forms, exposed again to develop and the conducting circuit 302 by being formed after the processes such as sputtering, chemical deposition, plating, etching, circuit 301 and circuit 302 are made up of the first metal layer, sputtering Ti/Cu or other metals, chemical copper, electro-coppering etc.；Because the chip for needing to be embedded to has different thickness, being opened in four grooves of substrate has the depth matched with the chip of required embedment, the corresponding embedment one side conducting chip 306 of groove or double-side conduction chip 308, the gap underfill material 304 between groove and chip are filled.For the connection of the contact surface and circuit 301 with groove floor of realizing double-side conduction chip, it can directly be connected by setting solder joint 309 and guide through hole 310 to be connected with circuit 301, or by the solder joint of chip 308 with circuit 301.By setting via hole 307 to realize the electrical connection between circuit 301 and circuit 302.The depth that can be seen that groove by above encapsulating structure is matched with the chip thickness of required embedment, when substrate need to be embedded to the chip of multiple different-thickness, it is ensured that the chip package of different-thickness enters this
It is coplanar after the groove of substrate, and the electrical connection or two-sided while electrical connection with substrate of the one side and substrate of chip can easily be realized.
The encapsulating structure of a kind of chip buried base plate of embodiment six, it is characterised in that the encapsulating structure of chip buried base plate includes：Substrate, substrate has and required encapsulation chip number identical through hole；Copper foil, copper foil has is distributed consistent convex portion with lead to the hole site, and the height and chip thickness of convex portion are inversely；Insulating medium layer, for connecting substrate and copper foil, so that through hole and convex portion are fitted together to and form groove, the depth of groove is matched with the chip thickness of required embedment, when substrate need to be embedded to the chip of multiple different-thickness, ensure different-thickness chip package enter it is coplanar after the groove of the substrate, the length of groove, width both greater than needed for embedment chip size so that groove can be large enough to hold needed for embedment chip；At least one chip, chip has the first contact surface and the second contact surface, by chip buried groove by the way of the first contact surface is connected with groove floor；Wiring layer, sets wiring, and wiring formation is correspondingly arranged on substrate so that be electrically connected between the substrate and the chip in the first contact surface of chip and/or the second contact surface.Substrate can be single sided board, dual platen or multi-panel, when the contact surface of chip first does not have pad, using non-conductive binding material in groove floor formation tack coat, be connected the first contact surface and groove floor by tack coat.When the contact surface of chip second has pad, in the second contact surface pad using conductive bonding material formation solder joint corresponding with pad, the first contact surface and groove floor are connected by solder joint, or etch pit corresponding with the second contact surface pad in second metal layer, conductive bonding material formation solder joint on tin ball or point is implanted into pit again, the second contact surface and groove floor are connected by solder joint, then connecting wiring layer and the second contact surface solder joint by way of metal blind hole.As shown in figure 12, chip buried base plate encapsulating structure includes：Substrate, further comprise insulating barrier 300, the circuit 301 of second metal layer formation, the first metal layer is laminated after dielectric or the dielectric 303 being coated with other forms, it is exposed again to develop and the conducting circuit 302 by being formed after the processes such as sputtering, chemical deposition, plating, etching, circuit
301 and circuit 302 be made up of the first metal layer, sputtering Ti/Cu or other metals, chemical copper, electro-coppering etc.；Because the chip for needing to be embedded to has different thickness, being opened in four grooves of substrate has the depth matching matched with the chip of required embedment, the connection of the contact surface and circuit 301 with groove floor of corresponding embedment one side conducting chip 306 or double-side conduction conducting chip, by setting conductive bonding material layer 308 and the circuit 309 of thick copper foil formation to be connected with circuit 301, by setting via hole 307 to realize the electrical connection between circuit 301 and circuit 302, by setting conducting blind hole 310 to realize line layer 301 and external connection.
It can be seen that by above encapsulating structure, the depth of groove is matched with the chip thickness of required embedment, when substrate need to be embedded to the chip of multiple different-thickness, ensure that the chip package of different-thickness enters coplanar after the groove of the substrate, and the electrical connection or two-sided while electrical connection with substrate of the one side and substrate of chip can easily be realized.
Chip buried base plate method for packing provided by the present invention and its structure are described in detail above, for those of ordinary skill in the art, thought according to the embodiment of the present invention, it will change in specific embodiments and applications, in summary, this specification content should not be construed as limiting the invention.
Claims (1)
- Claim1st, a kind of method for packing of chip buried base plate, it is characterised in that the chip has the first contact surface and the second contact surface, comprises the following steps：Step S1:At least one chip buried portion is set in the substrate, the chip buried portion is through hole and/or groove, and the number in the chip buried portion is identical with the number of required encapsulation chip, and the depth in the chip buried portion is matched with the chip thickness of required encapsulation；Step S2:By the chip buried chip buried portion；Step S3:Connected up in the first contact surface of chip and/or the second contact surface, and correspondence wiring on substrate, form wiring layer so that be electrically connected between the substrate and the chip.2nd, the method for packing of chip buried base plate according to claim 1, it is characterised in that the chip of required encapsulation has different thickness.3rd, the method for packing of chip buried base plate according to claim 1, it is characterised in that the detailed process that the groove is formed in step S1 is：Take thick copper foil to etch and be distributed consistent convex portion with the lead to the hole site；The substrate and thick copper foil are subjected to lamination connection by insulating medium layer, the convex portion is chimeric with the through hole to form the groove；Or directly open up the groove in substrate.4th, the method for packing of chip buried base plate according to claim 1, it is characterised in that the detailed process by the chip buried groove is：Non-conductive binding material is coated on the groove floor, tack coat is formed；The contact surface of chip first is docked into bonding with the tack coat so that the chip buried groove.5th, the method for packing of chip buried base plate according to claim 1, it is characterised in that the detailed process by the chip buried groove is：By conductive bonding material point in the bottom surface of the groove, solder joint is formed in the bottom surface of the groove；The contact surface of chip first is docked into bonding with the solder joint so that the chip buried groove.6th, the method for packing of chip buried base plate according to claim 1, it is characterised in that：Detailed process by the chip buried groove is：Pit is got in the groove floor； Conductive bonding material on tin ball or point is implanted into the pit, solder joint is formed in the pit；The contact surface of chip first is docked into bonding with the solder joint so that the chip buried groove.7th, the method for packing of chip buried base plate according to claim 1, it is characterised in that step S2 is specially：Photosensitive material is coated on a surface of the substrate, photosensitive material layer is formed；Second contact surface of the chip is connected with the photosensitive material layer so that the chip is fixed on the logical lonely L;The binding material for fixing the chip is inserted in gap between the chip and the through hole；Remove the photosensitive material layer.8th, a kind of encapsulating structure of chip buried base plate, it is characterised in that the encapsulating structure of the chip buried base plate includes substrate, chip and wiring layer,The substrate is provided with least one chip buried portion, and the chip has the first contact surface and the second contact surface, and the chip buried portion is through hole and/or groove, the thickness matching of the depth in the chip buried portion and the chip of corresponding embedment,The wiring layer includes being laid in the wiring of the contact surface of chip first and/or the second contact surface, and the wiring of the correspondence chip and lay be used to realize the wiring being electrically connected between the chip and substrate on substrate.9th, chip-packaging structure according to claim 8, it is characterized in that, also include copper foil and insulating medium layer, the copper foil has is distributed consistent convex portion with the lead to the hole site, the height of the convex portion and the chip thickness are inversely, the insulating medium layer is arranged between the substrate and the copper foil to connect the substrate and the copper foil, and the through hole and the convex portion are fitted together to and form the groove.10th, chip-packaging structure according to claim 8, it is characterised in that at least one described chip has different thickness.11st, the encapsulating structure of chip buried base plate according to claim 8, it is characterised in that：When the contact surface of chip first does not have pad, using non-conductive binding material in groove floor formation tack coat, first contact surface and the groove floor are connected by the tack coat.12nd, the encapsulating structure of chip buried base plate according to claim 8, it is characterised in that：When the contact surface of chip second has pad, in the second contact surface pad using conductive bonding material formation solder joint corresponding with the pad, first contact surface and the groove floor are connected by the solder joint, And/orPit corresponding with the second contact surface pad is etched in the second metal layer, then conductive bonding material formation solder joint on tin ball or point is implanted into the pit, first contact surface and the groove floor is connected by the solder joint.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2011/079575 WO2013037102A1 (en) | 2011-09-13 | 2011-09-13 | Encapsulation method for embedding chip into substrate and structure thereof |
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| CN103477423B CN103477423B (en) | 2017-02-01 |
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| CN103477423B (en) | 2017-02-01 |
| WO2013037102A1 (en) | 2013-03-21 |
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