CN100514616C - Embedded chip packaging process and circuit substrate with embedded chip - Google Patents
Embedded chip packaging process and circuit substrate with embedded chip Download PDFInfo
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- CN100514616C CN100514616C CN 200610112234 CN200610112234A CN100514616C CN 100514616 C CN100514616 C CN 100514616C CN 200610112234 CN200610112234 CN 200610112234 CN 200610112234 A CN200610112234 A CN 200610112234A CN 100514616 C CN100514616 C CN 100514616C
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- layer
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- dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
The invention relates to an embedded chip packaging process and a circuit substrate with an embedded chip. The embedded chip packaging process comprises connecting a chip to a first circuit layer on a carrier plate, and laminating a laminate on a dielectric material to embed the chip in the dielectric material to form a circuit substrate with an embedded chip. The chip is provided with at least one bump, and the bump can be electrically connected with the bonding pad of the first circuit layer through solder. The flip chip bonding process can provide better chip bonding reliability and alignment precision, thereby replacing the conventional method of forming holes by laser and manufacturing circuit layers.
Description
Technical field
The invention relates to a kind of chip encapsulating manufacturing procedure and structure thereof, and particularly relevant for a kind of built-in type chip encapsulating manufacturing procedure and bury the circuit substrate of chip in having.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In these electronic products, can dispose a circuit substrate usually; this circuit substrate is in order to carry single chip or a plurality of chip; with data processing unit as electronic product; yet chip configuration can cause loaded area to increase on circuit substrate; thereby how chip is built in the circuit substrate, become current key technology.
Fig. 1 please refer to Fig. 1 for the existing profile that buries the circuit substrate of chip in having, and this circuit substrate 10 comprises a substrate 100, a plurality of chip 110, a dielectric layer 120, a line layer 130, anti oxidation layer 140 and welding cover layer 150.Wherein, a plurality of chips 110 are positioned on the substrate 100, and dielectric layer 120 then is formed on the substrate 100 and covers a plurality of chips 110.In addition, the conductive hole 122 that the weld pad 112 of each chip 110 is made by laser is connected with line layer 130, and line layer 130 again with corresponding conductive plunger 132 connections, to form a circuit substrate 10 that buries chip 110 in having.
By existing circuit substrate 10 as can be known, chip 110 adopts configuration arrangement mode at grade, and when increasing the number of chip 110 as if desire, then opposing substrates 100 areas also must increase thereupon.In addition, making conductive hole 122 with laser easily causes the skew of Aligning degree and yield is reduced.
Summary of the invention
Purpose of the present invention is providing a kind of built-in type chip encapsulating manufacturing procedure exactly, and it is by the chip bonding technology, to improve the yield of chip join.
A further object of the present invention provides a kind of circuit substrate with inner embedded component, and it is by the yield of chip package with the raising chip join.
The present invention proposes a kind of built-in type chip encapsulating manufacturing procedure, comprises the following steps: at first, provide a support plate and a sheet metal, and sheet metal is disposed on the support plate; The pattern metal sheet, to form one first line layer on support plate, first line layer comprises at least one joint sheet; Form a scolder on joint sheet; Dispose a chip on support plate, chip has at least one projection, and projection electrically connects by scolder and joint sheet; Cover a dielectric material on line layer, and chip buried-in is in this dielectric material; Provide a laminate and one second line layer, and second line layer is disposed on the laminate; And carry out a pressing step, make that second line layer on the laminate is pressed in the dielectric material.Above-mentioned dielectric material comprises a film, and film is formed by the gel of semi-solid preparation resin material.In addition, film has an opening corresponding to chip, and film is when being covered on the line layer, and chip is arranged in opening.
Described according to embodiments of the invention, above-mentioned dielectric material is covered in after the line layer, more comprises the heating dielectric material, makes it to solidify.In addition, dielectric material more comprises removing support plate and laminate after solidifying.In addition, after dielectric material solidifies, more comprise the consistent at least hole of formation in dielectric material, and insert a conducting resinl in perforation, and corresponding first line layer and second line layer of connecting in the two ends of perforation.Moreover first line layer disposes one first contact corresponding to an end of perforation, and second line layer disposes one second contact corresponding to the other end of perforation, and first contact and second contact are by the conducting resinl mutual conduction.
Described according to embodiments of the invention, the second above-mentioned line layer comprises a screen, and it is covered on the surface of dielectric material corresponding to chip, to prevent Electromagnetic Interference.
Described according to embodiments of the invention, above-mentioned support plate comprises a metallic plate or an insulation board, and sheet metal comprises a gum copper sheet.In addition, laminate comprises a metallic plate or an insulation board, and second line layer comprises a patterning gum copper layer.
The present invention proposes a kind of circuit substrate with inner embedded component in addition, and it comprises a substrate, an inner embedded component and a screen.Substrate comprises one first line layer, a dielectric layer and one second line layer, and first line layer lays respectively in relative two surfaces of dielectric layer with second line layer, and has a conductive through hole in the dielectric layer, and its conducting is in first line layer and second line layer.In addition, be embedded in the dielectric layer in the inner embedded component, and inner embedded component has at least one projection, the first line layer correspondence has a joint sheet, and above-mentioned joint sheet and above-mentioned projection layer electrically connect.In addition, screen is covered in dielectric layer corresponding to the surface of inner embedded component and can form in the lump with second line layer.
Described according to embodiments of the invention, the first above-mentioned line layer disposes one first contact corresponding to an end of conductive through hole, and second line layer disposes one second contact corresponding to the other end of conductive through hole, and first contact and second contact are by the conductive through hole mutual conduction.
Described according to embodiments of the invention, above-mentioned inner embedded component comprises chip, and chip has at least one projection, and the first line layer correspondence has a joint sheet, and itself and projection electrically connect.In addition, inner embedded component comprises electric capacity, resistance or inductance.
The present invention is because of adopting the chip bonding technology of high yield, earlier chip is connected to first line layer on the support plate, again via the pressing laminate on dielectric material so that chip buried-in is in dielectric material, and then replaces the laser punching and the circuit that bury chip in existing and make.Therefore, the present invention can improve the yield of chip join.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the existing profile that buries the circuit substrate of chip in having.
Fig. 2 A～Fig. 2 G illustrates the schematic flow sheet of the built-in type chip encapsulating manufacturing procedure of one embodiment of the invention respectively.
Fig. 3 illustrates the schematic diagram of the chip-packaging structure of one embodiment of the invention.
10,20: circuit substrate 100: substrate
110: chip 112: weld pad
120: dielectric layer 122: conductive hole
130: line layer 132: conductive plunger
140: anti oxidation layer 150: insulating barrier
200: support plate 210: sheet metal
Contact 220 in 216: the first: insulating barrier
222: scolder 230: dry film
240: chip 242: projection
244: the back side 250: dielectric material
252: opening 260: laminate
266: the second contacts of 262: the second line layers
270: dielectric layer 272: perforation
274: conducting resinl 280: screen
300: chip-packaging structure 310: dielectric layer
312: conductive hole 320: the surface lines layer
330: soldered ball
Embodiment
Fig. 2 A～Fig. 2 G illustrates the schematic flow sheet of the built-in type chip encapsulating manufacturing procedure of one embodiment of the invention respectively, wherein Fig. 2 A～Fig. 2 E illustrates chip and is disposed at step on the support plate in the mode of covering brilliant combination, and Fig. 2 F～Fig. 2 G illustrates the step that is shaped in a dielectric material and pressing chip buried.Though present embodiment is an example with the encapsulation procedure of one chip, the present invention also can be used on the encapsulation procedure of multicore sheet, cuts into the encapsulating structure that has one chip or have a plurality of chips afterwards again.
Please refer to Fig. 2 A～Fig. 2 B, a support plate 200 and a sheet metal 210 are provided earlier, and pattern metal sheet 210 is to form first line layer 212.Wherein, support plate 200 for example is metallic plate or the insulation board with intensity and supportive, but also can be soft film or film, in order to bearing metal sheet 210, and sheet metal 210 for example is gum Copper Foil or other conducting strip, and it is attached on the support plate 200, with expose, the step of patterning such as development, etching, so that first line layer 212 has at least one joint sheet 214, and the quantity of joint sheet 214 can decide according to the number of actual I/O signal.In the present embodiment, the dry-etching that can be traditional or the mode of Wet-type etching are carried out patterned etch to sheet metal 210, to form the first required line layer 212.
Then, please refer to Fig. 2 C～Fig. 2 D, form an insulating barrier (insulation layer) 220 on support plate 200, and cover a removable dry film 230, to carry out follow-up electroplating process or printing process.Wherein, insulating barrier 220 can appear the upper surface of the joint sheet 214 of first line layer 212, and dry film 230 is covered in other surface (for example surface of first contact 216) of first line layer 212, amasss in the upper surface of joint sheet 214 so that electroplate scolder 222 Shen.In the present embodiment, electroplating scolder 222 for example is leypewter or other low-melting alloy etc., and its purpose that is formed on the joint sheet 214 is projection 242 and the bond strength between the joint sheet 214 and the precision of strengthening on the chip 240 of contraposition.Certainly, the present invention can also print solder paste form a scolder 222 on joint sheet 214, and its purpose is identical with plating with effect.
Then, please refer to Fig. 2 E, remove dry film 230, and chip 240 is when being disposed on first line layer 212 in the mode of chip bonding, the projection 242 of chip 240 can interconnect by scolder 222 and joint sheet 214, with the media as the electric signal transmission.Because scolder 222 can prevent projection 242 contrapositions skew and increase the intensity that engages, thereby improve the reliability and the yield of chip bonding.In addition,, earlier chip 240 is connected to first line layer 212 on the support plate 200, also can avoids among existing Fig. 1 with laser punching and make the processing procedure of the chip 110 that line layer 130 buries in connecting by the chip bonding technology of high yield.
Then, please refer to Fig. 2 F, cover dielectric material 250 and be pressed on the dielectric material 250, so that be embedded in the dielectric material 250 in the chip 240 with a laminate 260.Wherein, dielectric material 250 for example is the BT resin (Bismaleimide Triazine Resin) or the PP resin insulating material such as (polypropylene) of semi-solid preparation (prepreg), it can react and reach the gel degree and form a film via monomer polymerization (polymerization), and dielectric material 250 optionally added glass cloth (glass fiber) to improve its intensity and supportive before polymerization reaction becomes film.In the present embodiment, when dielectric material 250 was covered on first line layer 212 with the film of semi-solid preparation, film can be pre-formed a suitable opening 252, and it is corresponding to the position at chip 240 places, and was enough to hold chip 240 in opening 252.The purpose of default opening 252 is to avoid in follow-up pressing step, and film is expressed to chip 240 and causes chip 240 to damage.
From the above, when being embedded in the dielectric material 250 in the chip 240, apply pressure to dielectric material 250 equably with laminate 260 again, so that chip 240 and projection 242 thereof intactly are coated in the dielectric material 250.Therefore at this moment, dielectric material 250 is solidified forming not, must carry out heat treated again, makes its molecule produce staggered link (Cross Linking) phenomenon and solidifies.
It should be noted that, laminate 260 is except in order to apply pressure to the dielectric material 250, more can make second line layer 262 in advance on laminate 260, its practice describes in detail at this no longer one by one as making first line layer 212 in Fig. 2 A～Fig. 2 B on a support plate 200.Wherein, laminate 260 for example is metallic plate or the insulation board with intensity and supportive, and second line layer 262 for example is gum copper layer or other metal level of patterning.When laminate 260 was pressed on dielectric material 250, second line layer 262 can be pressed in the dielectric material 250, shown in Fig. 2 F.
Then, please refer to Fig. 2 G, after dielectric material 250 full solidification, support plate 200 and laminate 260 can be by lifting off (lift off) or other the technology that divests is removed, only keep in relative two surfaces of first line layer 212 and the dielectric layer 270 of second line layer 262 after curing, to form a circuit substrate 20 that buries chip 240 in having.Wherein, more can form consistent at least hole 272 by laser punching in the dielectric layer 270, corresponding first line layer 212 and second line layer 262 of connecting in its two ends.In addition, first line layer 212 disposes one first contact 216 corresponding to an end of perforation 272, and second line layer 262 disposes one second contact 266 corresponding to the other end of perforation 272, and first contact 216 and second contact 266 conducting resinl 274 mutual conduction in the perforation 272 are to reach the purpose of signal transmission.
It should be noted that, this circuit substrate 20 is except transmitting the electric signal of chip 240 or other assembly by first and second line layer 212,262, more can comprise a screen 280, it is covered in the surface of the dielectric layer 270 of chip 240 tops, and contacts with the back side 244 maintenance one spacings of chip 240 or with the back side 244 of chip 240.The area of screen 280 is the best with the area more than or equal to chip 240, to stop the electromagnetic wave that is incident in chip 240, arrives the normal operation of chip 240 to avoid Electromagnetic Interference.In the present embodiment, screen 280 can be the metal of a bronze medal layer or other high conductivity, and screen 280 forms also can be via patterning second line layer 262 time in the lump, or independently is formed on the laminate 260 via the mode that attaches, and is pressed in the dielectric layer 270 again.
At last, please refer to the chip-packaging structure 300 of Fig. 3, it illustrates the schematic diagram of making at least one line layer and soldered ball on the circuit substrate 20 of Fig. 2 G, wherein dielectric layer 310 and surface lines layer 320 can be formed on the circuit substrate 20 in regular turn by Layer increasing method, and surface lines layer 320 can electrically connect by second contact 266 of the conductive hole in the dielectric layer 310 312 and second line layer 262.In addition, more configurable a plurality of soldered balls 330 on the surface lines layer 320 are to form the buried chip encapsulation structure 300 of ball lattice arrays (ball grid array).
Bury the chip 240 except interior, present embodiment also can be used in the encapsulation and structure of other inner embedded component, for example passive components such as electric capacity, resistance and inductance are replaced above-mentioned chip 240, can form circuit substrate with inner embedded component, its fabrication steps such as Fig. 2 A～Fig. 2 G are not described in detail in this.
In sum, the present invention is connected to chip first line layer on the support plate earlier because of adopting the chip bonding technology of high yield, again via the pressing laminate on dielectric material, so that chip buried-in is in dielectric material, and then replaces the laser punching and the circuit that bury chip in existing and make.Therefore, the present invention can improve the yield of chip join.In addition, the present invention above chip, preventing electromagnetic interference, thereby makes the chip can normal operation, to reduce the noise that electromagnetic interference was produced by the configuration screen.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appending claims person of defining.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610112234 CN100514616C (en) | 2006-08-29 | 2006-08-29 | Embedded chip packaging process and circuit substrate with embedded chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610112234 CN100514616C (en) | 2006-08-29 | 2006-08-29 | Embedded chip packaging process and circuit substrate with embedded chip |
Publications (2)
| Publication Number | Publication Date |
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| CN101136385A CN101136385A (en) | 2008-03-05 |
| CN100514616C true CN100514616C (en) | 2009-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200610112234 Expired - Fee Related CN100514616C (en) | 2006-08-29 | 2006-08-29 | Embedded chip packaging process and circuit substrate with embedded chip |
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Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100579339C (en) * | 2008-04-28 | 2010-01-06 | 日月光半导体制造股份有限公司 | Method for manufacturing circuit board and method for reducing thickness of electrode contact of embedded element in circuit board |
| CN102378502B (en) * | 2010-08-13 | 2013-11-27 | 欣兴电子股份有限公司 | Circuit board and its manufacturing method |
| CN103477423B (en) * | 2011-09-13 | 2017-02-01 | 深南电路有限公司 | Encapsulation method for embedding chip into substrate and structure thereof |
| WO2013055700A1 (en) * | 2011-10-13 | 2013-04-18 | Flipchip International, Llc | Wafer level applied rf shields |
| CN102545353A (en) * | 2012-01-11 | 2012-07-04 | 可富科技股份有限公司 | Flip Chip Technology and Structure of Soft Film Antenna for Wireless Charger |
| CN102637612B (en) * | 2012-05-03 | 2014-07-30 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN104851847B (en) * | 2014-02-14 | 2017-09-08 | 恒劲科技股份有限公司 | Packaging device and manufacturing method thereof |
| CN105789847B (en) * | 2014-12-15 | 2019-01-04 | 财团法人工业技术研究院 | Antenna integrated package structure and manufacturing method thereof |
| US9799636B2 (en) * | 2015-11-12 | 2017-10-24 | Nxp Usa, Inc. | Packaged devices with multiple planes of embedded electronic devices |
| CN107170731A (en) * | 2017-05-05 | 2017-09-15 | 华为技术有限公司 | Embedded substrate and its manufacture method |
| CN107567208A (en) * | 2017-09-07 | 2018-01-09 | 维沃移动通信有限公司 | A kind of printed circuit board (PCB) preparation method and printed circuit board (PCB) |
| CN110459509A (en) * | 2019-07-24 | 2019-11-15 | 浙江荷清柔性电子技术有限公司 | A kind of interconnection packaging method and interconnection package structure of chip |
| US11302537B2 (en) * | 2020-04-01 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure with conductive adhesive layer and method for forming the same |
| CN115295501A (en) * | 2022-08-22 | 2022-11-04 | 讯芯电子科技（中山）有限公司 | Embedded chip package and manufacturing method thereof |
| CN117886297B (en) * | 2024-01-19 | 2025-02-07 | 兴荣新源(厦门)科技有限公司 | A sodium iron fluorophosphate positive electrode material prepared by repairing and regenerating waste batteries |
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| CN1755929A (en) * | 2004-09-28 | 2006-04-05 | 飞思卡尔半导体公司 | Method for forming semiconductor package and its structure |
| CN1251560C (en) * | 2001-01-19 | 2006-04-12 | 松下电器产业株式会社 | Parts built in module and its making method |
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Patent Citations (4)
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| CN1251560C (en) * | 2001-01-19 | 2006-04-12 | 松下电器产业株式会社 | Parts built in module and its making method |
| US20050247665A1 (en) * | 2004-05-10 | 2005-11-10 | Shinko Electric Industries Co., Ltd. | Method of manufacturing an electronic parts packaging structure |
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| CN101136385A (en) | 2008-03-05 |
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