CN103456365A - Shift register unit, shift register and display device - Google Patents
Shift register unit, shift register and display device Download PDFInfo
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- CN103456365A CN103456365A CN2013103908150A CN201310390815A CN103456365A CN 103456365 A CN103456365 A CN 103456365A CN 2013103908150 A CN2013103908150 A CN 2013103908150A CN 201310390815 A CN201310390815 A CN 201310390815A CN 103456365 A CN103456365 A CN 103456365A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Crystallography & Structural Chemistry (AREA)
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- Computer Hardware Design (AREA)
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention relates to the technical field of display, and in particular relates to a shift register unit, a shift register and a display device. The shift register unit comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor. According to the shift register unit, noise reduction is realized with fewer transistors on the basis of the original signal transfer function, so that output errors which are probably caused by drift of threshold voltage of the transistors, interference of adjacent transistors and the like are effectively suppressed, a narrow bezel of a liquid crystal display is realized, the power consumption of a drive circuit is reduced, the output characteristic of the shift register is further improved, and the service life of the transistors is further prolonged.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register unit, a shift register and a display device.
Background
At present, a TFT-LCD driver mainly includes a gate driver and a data driver, wherein the gate driver applies an input clock signal to a gate line of a liquid crystal display panel after converting the clock signal through a shift register. The gate driving circuit has the same process as the formation of the TFT and is simultaneously formed on the LCD panel together with the TFT. The gate driving circuit includes a shift register having a plurality of stages, each of which is connected to a corresponding gate line to output a gate driving signal. The stages of the gate driving circuit are connected to each other, a start signal is input to a first pole of the stages and sequentially outputs gate driving signals to the gate lines, wherein an input terminal of a previous stage is connected to an output terminal of a previous stage, and an output terminal of a next stage is connected to a control terminal of the previous stage.
The gate driving circuit with the above structure is arranged on the right side of the LCD panel. However, the shift register signal output error and the self-life reduction may be caused by the drift of the threshold voltage of the transistor itself in the gate driving circuit and the interference of the adjacent transistor.
Therefore, in view of the above disadvantages, the present invention provides a shift register unit, a shift register and a display device.
Disclosure of Invention
The invention aims to solve the technical problems that the drift of the threshold voltage of a transistor in a grid driving circuit and the interference of adjacent transistors can cause the signal output error of a shift register and the service life of the shift register is reduced.
In order to solve the above technical problem, the present invention provides a shift register unit, which includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a storage capacitor; wherein,
the grid and the first pole of the first transistor are connected with an input signal end, and the second pole of the first transistor is connected with an upper pull node;
the grid electrode of the second transistor is connected with a reset signal end, the first pole of the second transistor is connected with the pull-up node, and the second pole of the second transistor is connected with a reference level line;
the grid electrode of the third transistor is connected with the pull-up node, the first pole of the third transistor is connected with a first clock signal, and the second pole of the third transistor is connected with an output signal end;
a grid electrode of the fifth transistor is connected with a pull-down node, a first pole of the fifth transistor is connected with the output signal end, and a second pole of the fifth transistor is connected with the reference level line;
a gate of the sixth transistor is connected to the pull-down node, a first pole of the sixth transistor is connected to the pull-up node, and a second pole of the sixth transistor is connected to the reference level line;
the grid and the first pole of the seventh transistor are connected with a second clock signal, and the second pole of the seventh transistor is connected with the pull-down node;
a grid electrode of the eighth transistor is connected with an input signal end, a first pole of the eighth transistor is connected with the pull-down node, and a second pole of the eighth transistor is connected with the reference level line;
and the first pole of the storage capacitor is connected with the pull-up node, and the second pole of the storage capacitor is connected with the output signal end.
The grid electrode of the fourth transistor is connected with the pull-up node, the first pole of the fourth transistor is connected with the pull-down node, and the second pole of the fourth transistor is connected with the reference level line.
Further, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all N-type TFT transistors.
Further, the reference level line is a low voltage level.
Further, the control method comprises the following steps:
in the first stage, the first clock signal is at a low level, the second clock signal is at a high level, the input signal end turns on the first transistor and charges the storage capacitor;
in the second stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal end is at a low level, the reset signal end is at a low level, the first clock signal turns on the third transistor, and the output signal end outputs a high level;
in the third stage, the first clock signal is at a low level, the second clock signal is at a high level, the reset signal end starts the second transistor, the storage capacitor is discharged through the second transistor, so that the first pole of the second transistor is reduced to be at the low level, the second clock signal starts the seventh transistor, the second pole of the seventh transistor is at a high potential, so that the fifth transistor and the sixth transistor respectively discharge the output signal end and the first pole of the second transistor, and the output signal end outputs the low level;
in the fourth stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal end is at a low level, the reset signal end is at a low level, the first transistor and the third transistor are both cut off, and the output signal end outputs a low level;
in the fifth stage, the first clock signal is at a low level, the second clock signal is at a high level, the input signal end is at a low level, the reset signal end is at a low level, the first transistor and the third transistor are both turned off, and the output signal end outputs at a low level.
The invention also provides a shift register, which comprises the shift register units which are cascaded in a multi-stage manner;
except the first stage, the input signal end of any other stage of shift register unit is connected with the signal output end of the first stage;
except the last stage, the reset signal end of any other stage of shift register unit is connected with the signal output end of the next stage.
The invention also provides a display device which comprises the shift register.
The technical scheme of the invention has the following advantages: the shift register unit of the invention realizes noise reduction processing by using fewer transistors on the basis of the original signal transmission function, thereby not only effectively inhibiting output errors possibly caused by the drift of the threshold voltage of the transistor, the interference of adjacent transistors and the like, but also realizing the narrow frame of the liquid crystal display, further reducing the power consumption of a driving circuit, and further improving the output characteristic of the shift register and the service life of the transistor.
Drawings
FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a logic sequence of a shift register unit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a shift register unit, which includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor C1; wherein,
the grid and the first pole of the first transistor M1 are connected with the input signal end G (N-1), and the second pole is connected with the upper pull node PU;
the gate of the second transistor M2 is connected to a reset signal terminal G (N + 1), the first pole is connected to the pull-up node PU, and the second pole is connected to a reference level line VSS;
the gate of the third transistor M3 is connected to the pull-up node PU, the first pole is connected to the first clock signal CLK, and the second pole is connected to the output signal terminal g (n);
a gate of the fourth transistor M4 is connected to the pull-up node PU, a first pole is connected to the pull-down node PD, and a second pole is connected to the reference level line VSS;
the gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole is connected to the output signal terminal g (n), and the second pole is connected to the reference level line VSS;
a gate of the sixth transistor M6 is connected to the pull-down node PD, a first pole is connected to the pull-up node PU, and a second pole is connected to the reference level line VSS;
the gate and the first pole of the seventh transistor M7 are connected to the second clock signal CLKB, and the second pole is connected to the pull-down node PD;
a gate of the eighth transistor M8 is connected to the input signal terminal G (N + 1), a first pole thereof is connected to the pull-down node PD, and a second pole thereof is connected to the reference level line VSS;
a first pole of the storage capacitor C1 is connected to the pull-up node PU, and a second pole is connected to the output signal terminal g (n).
The first clock signal CLK and the second clock signal CLKB are both connected to the IC driving circuit, and the output signal terminal g (n) is connected to the gate line.
The pull-up node PU has the same level as the second pole of the first transistor M1, and the pull-down node PD has the same level as the second pole of the seventh transistor M7.
The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all N-type TFT transistors.
The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be all P-type TFT transistors.
According to the shift register unit provided by the embodiment of the invention, on the basis of the prior art, a noise reduction design is added, the output error caused by the drift of the threshold voltage of the transistor and the interference of the adjacent transistor is effectively inhibited, and the output characteristic of the shift register and the service life of the transistor are further improved.
The invention also provides a shift register formed by cascading the shift register units, which comprises cascaded shift register units of each stage.
The input signal end of the first stage shift register unit is connected with the initial signal end, and the reset signal end of the first stage shift register unit is connected with the output signal end of the second stage shift register unit; the input signal end of the last stage of shift register unit is connected with the output signal end of the previous stage of shift register unit, and the reset bow end of the last stage of shift register unit is connected with the initial signal end; except the first stage and the last stage of shift register units, the input signal ends of the other shift register units at all stages are connected with the output signal end of the shift register unit at one stage, and the reset signal end is connected with the output signal end of the shift register unit at the next stage.
Specifically, the Shift Register includes M stages, where M is the number of gate lines, where M is a positive integer, and as Shift Register in the diagram shown in fig. 3 denotes each stage of Shift Register unit as described above, a start signal terminal STV is input as an input signal to the Shift Register unit of the first stage and sequentially outputs a gate drive signal to the gate lines, an input signal of the nth stage is supplied by an output signal of the nth-l stage, where N < M, a reset signal is supplied by an output signal of the nth + l stage, and a reset signal of the nth stage is supplied by an input signal of the first stage, that is, a start signal on the one hand as an input signal of the first pole and on the other hand also as a reset signal of the nth stage.
The following describes a control method of an nth (N < M, M is the number of stages of the shift register) stage shift register unit in the shift register according to an embodiment of the present invention with reference to a logic timing diagram shown in fig. 2, where all transistors are turned on at a high level and turned off at a low level.
First stage T1: the clock signal CLK is at a low level, the second clock signal CLKB is at a high level, the previous stage output signal G (N-1) as an input signal is at a high level, the next stage output signal G (N + 1) as a reset signal is at a low level, and VSS is a low level signal. The high-level input signal G (N-1) turns on the first transistor M1 and charges the storage capacitor C1 to raise the PU point to high level, at which time the gate switch of the third transistor M3 is turned on, but since the clock signal CLK is low level at this time, the third transistor M3 is not turned on, and the output signal terminal G (N) outputs low level;
in this stage, since the second clock signal CLKB and the preceding stage output signal G (N-1) as the input signal are at high level, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are all turned on, the fifth transistor M5 and the sixth transistor M6 are all in an off state, and the PD point potential is at low level, the storage capacitor C1 is effectively prevented from being insufficiently charged due to the drift of its threshold voltage and the leakage current of the interference of the adjacent transistors by the fifth transistor M5 and the sixth transistor M6.
Second stage T2: the clock signal CLK is at a high level, the second clock signal CLKB is at a low level, the input signal G (N-1) is at a low level, and the reset signal G (N + 1) is at a low level. At this time, the first transistor M1 is turned off, the storage capacitor C1 is stopped being charged, the third transistor M3 is turned on, and the output signal terminal g (n) outputs a high level;
in this stage, since the clock signals CLK and PU are at high level, the seventh transistor M7 and the eighth transistor M8 are both turned off, the gate switch of the fourth transistor M4 is kept at an on state, the PD point is subjected to noise release processing and kept at a low level, and the fifth transistor M5 and the sixth transistor M6 are prevented from finally causing an output error of the output signal terminal g (n) due to leakage of the storage capacitor C1 caused by noise at the PD point.
Third stage T3: the clock signal CLK is at a low level, the second clock signal CLKB is at a high level, the input signal G (N-1) is at a low level, and the reset signal G (N + 1) is at a high level. At this time, the second transistor M2 is turned on, the storage capacitor C1 quickly lowers the PU node to a low level by discharging through the second transistor M2, and the third transistor M3 is turned off. Because the second clock signal CLKB is at a high level, the input signal G (N-1) is at a low level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, and the PD point is at a high level, the fifth transistor M5 and the sixth transistor M6 respectively discharge the output terminal G (N) and the PU point quickly to ensure that the output signal terminal G (N) outputs at a low level, thereby implementing the reset function;
fourth stage T4: the clock signal CLK is at a high level, the second clock signal CLKB is at a low level, the input signal G (N-1) is at a low level, and the reset signal G (N + 1) is at a low level. At this time, the first transistor M1 is turned off, the PU node is at low level, the third transistor M3 is turned off, and the output signal terminal g (n) outputs low level.
In this stage, if the PU node generates noise due to crosstalk between adjacent transistors, the gate of the fourth transistor M4 is turned on to continuously discharge the PD node, so that the PD node is kept at a low voltage level, thereby preventing the fifth transistor M5 and the sixth transistor M6 from leaking the storage capacitor C1 due to the noise at the PD node, and finally causing an output error at the output signal terminal g (n).
Fifth stage T5: the clock signal CLK is low, the second clock signal CLKB is high, the input signal G (N-1) is low, and the reset signal G (N + 1) is low. At this time, the first transistor M1 is turned off, the PU node is at low level, the third transistor M3 is turned off, and the output signal terminal g (n) outputs low level;
in this stage, since the second clock signal CLKB is at a high level, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the PD point is at a high potential, and the gate switches of the fifth transistor M5 and the sixth transistor M6 are turned on to perform noise reduction processing on the PU point and the output signal terminal g (n), thereby preventing erroneous output that may be caused by drift of the threshold voltages of the transistors themselves and interference of adjacent transistors.
Before the next frame signal comes, with the periodic variation of the first clock signal CLK and the second clock signal CLKB, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 continuously perform noise releasing processing on the PU point, the PD point, and the output signal terminal g (n), so as to prevent erroneous output possibly caused by drift of the threshold voltage of the transistors themselves and interference of adjacent transistors, and ensure accuracy and stability of output.
In the shift register unit of the present invention, except for the seventh transistor M7, the remaining transistors are operated for a very short period of time during one-line signal scanning time. In addition, in the shift register unit of the invention, compared with the first transistor and the third transistor, the channel width of the rest transistors is much smaller, so although the seventh transistor works for a longer time in a signal scanning time of one row, the power consumption is not increased much, and the whole shift register realizes the great reduction of the power consumption.
In summary, the shift register unit of the present invention uses fewer transistors to implement noise reduction processing based on the original signal transmission function, thereby not only effectively suppressing the output error possibly caused by the drift of the threshold voltage of the transistor itself and the interference of the adjacent transistor, but also implementing the narrow frame of the liquid crystal display, further reducing the power consumption of the driving circuit, and further improving the output characteristics of the shift register and the service life of the transistor.
The above description is only a few preferred embodiments of the present invention, and it should be noted that, for those skilled in the art, many modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A shift register cell, comprising: the storage capacitor comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor; wherein,
the grid and the first pole of the first transistor are connected with an input signal end, and the second pole of the first transistor is connected with an upper pull node;
the grid electrode of the second transistor is connected with a reset signal end, the first pole of the second transistor is connected with the pull-up node, and the second pole of the second transistor is connected with a reference level line;
the grid electrode of the third transistor is connected with the pull-up node, the first pole of the third transistor is connected with a first clock signal, and the second pole of the third transistor is connected with an output signal end;
a grid electrode of the fifth transistor is connected with a pull-down node, a first pole of the fifth transistor is connected with the output signal end, and a second pole of the fifth transistor is connected with the reference level line;
a gate of the sixth transistor is connected to the pull-down node, a first pole of the sixth transistor is connected to the pull-up node, and a second pole of the sixth transistor is connected to the reference level line;
the grid and the first pole of the seventh transistor are connected with a second clock signal, and the second pole of the seventh transistor is connected with the pull-down node;
a grid electrode of the eighth transistor is connected with an input signal end, a first pole of the eighth transistor is connected with the pull-down node, and a second pole of the eighth transistor is connected with the reference level line;
and the first pole of the storage capacitor is connected with the pull-up node, and the second pole of the storage capacitor is connected with the output signal end.
2. The shift register cell of claim 1, wherein: the grid electrode of the fourth transistor is connected with the pull-up node, the first pole of the fourth transistor is connected with the pull-down node, and the second pole of the fourth transistor is connected with the reference level line.
3. The shift register cell of claim 2, wherein: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all N-type TFT transistors.
4. The shift register cell of claim 2, wherein: the reference level line is a low voltage level.
5. The shift register cell of any one of claims 2-4, wherein: the control method comprises the following steps:
in the first stage, the first clock signal is at a low level, the second clock signal is at a high level, the input signal end turns on the first transistor and charges the storage capacitor;
in the second stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal end is at a low level, the reset signal end is at a low level, the first clock signal turns on the third transistor, and the output signal end outputs a high level;
in the third stage, the first clock signal is at a low level, the second clock signal is at a high level, the reset signal end starts the second transistor, the storage capacitor is discharged through the second transistor, so that the first pole of the second transistor is reduced to be at the low level, the second clock signal starts the seventh transistor, the second pole of the seventh transistor is at a high potential, so that the fifth transistor and the sixth transistor respectively discharge the output signal end and the first pole of the second transistor, and the output signal end outputs the low level;
in the fourth stage, the first clock signal is at a high level, the second clock signal is at a low level, the input signal end is at a low level, the reset signal end is at a low level, the first transistor and the third transistor are both cut off, and the output signal end outputs a low level;
in the fifth stage, the first clock signal is at a low level, the second clock signal is at a high level, the input signal end is at a low level, the reset signal end is at a low level, the first transistor and the third transistor are both turned off, and the output signal end outputs at a low level.
6. A shift register, characterized by: a shift register cell according to any one of claims 1 to 5 comprising a cascade of a plurality of stages;
except the first stage, the input signal end of any other stage of shift register unit is connected with the signal output end of the first stage;
except the last stage, the reset signal end of any other stage of shift register unit is connected with the signal output end of the next stage.
7. A display device, characterized in that: comprising a shift register according to claim 6.
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| CN2013103908150A CN103456365A (en) | 2013-08-30 | 2013-08-30 | Shift register unit, shift register and display device |
| PCT/CN2013/089631 WO2015027628A1 (en) | 2013-08-30 | 2013-12-17 | Shift register unit, shift register and display device |
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| CN2013103908150A CN103456365A (en) | 2013-08-30 | 2013-08-30 | Shift register unit, shift register and display device |
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| CN104575419A (en) * | 2014-12-04 | 2015-04-29 | 上海天马微电子有限公司 | Shift register and driving method thereof |
| WO2015184659A1 (en) * | 2014-06-07 | 2015-12-10 | 深圳市华星光电技术有限公司 | Driving circuit and liquid crystal display device |
| CN106531112A (en) * | 2017-01-03 | 2017-03-22 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, shifting register and display apparatus |
| CN107146570A (en) * | 2017-07-17 | 2017-09-08 | 京东方科技集团股份有限公司 | Shift register cell, scan drive circuit, array base palte and display device |
| CN111524450A (en) * | 2020-04-29 | 2020-08-11 | 昆山国显光电有限公司 | Display device, binding impedance detection method thereof and screen crack detection method |
| CN111816127A (en) * | 2020-07-27 | 2020-10-23 | Oppo广东移动通信有限公司 | GOA unit and driving method thereof, GOA circuit and display panel |
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Application publication date: 20131218 |